1/*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#ifndef _ENA_ETH_IO_H_ 35#define _ENA_ETH_IO_H_ 36 37enum ena_eth_io_l3_proto_index { 38 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0, 39 40 ENA_ETH_IO_L3_PROTO_IPV4 = 8, 41 42 ENA_ETH_IO_L3_PROTO_IPV6 = 11, 43 44 ENA_ETH_IO_L3_PROTO_FCOE = 21, 45 46 ENA_ETH_IO_L3_PROTO_ROCE = 22, 47}; 48 49enum ena_eth_io_l4_proto_index { 50 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0, 51 52 ENA_ETH_IO_L4_PROTO_TCP = 12, 53 54 ENA_ETH_IO_L4_PROTO_UDP = 13, 55 56 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23, 57}; 58 59struct ena_eth_io_tx_desc { 60 /* 15:0 : length - Buffer length in bytes, must 61 * include any packet trailers that the ENA supposed 62 * to update like End-to-End CRC, Authentication GMAC 63 * etc. This length must not include the 64 * 'Push_Buffer' length. This length must not include 65 * the 4-byte added in the end for 802.3 Ethernet FCS 66 * 21:16 : req_id_hi - Request ID[15:10] 67 * 22 : reserved22 - MBZ 68 * 23 : meta_desc - MBZ 69 * 24 : phase 70 * 25 : reserved1 - MBZ 71 * 26 : first - Indicates first descriptor in 72 * transaction 73 * 27 : last - Indicates last descriptor in 74 * transaction 75 * 28 : comp_req - Indicates whether completion 76 * should be posted, after packet is transmitted. 77 * Valid only for first descriptor 78 * 30:29 : reserved29 - MBZ 79 * 31 : reserved31 - MBZ 80 */ 81 uint32_t len_ctrl; 82 83 /* 3:0 : l3_proto_idx - L3 protocol. This field 84 * required when l3_csum_en,l3_csum or tso_en are set. 85 * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and 86 * DF flags of the IPv4 header is 0. Otherwise must 87 * be set to 1 88 * 6:5 : reserved5 89 * 7 : tso_en - Enable TSO, For TCP only. 90 * 12:8 : l4_proto_idx - L4 protocol. This field need 91 * to be set when l4_csum_en or tso_en are set. 92 * 13 : l3_csum_en - enable IPv4 header checksum. 93 * 14 : l4_csum_en - enable TCP/UDP checksum. 94 * 15 : ethernet_fcs_dis - when set, the controller 95 * will not append the 802.3 Ethernet Frame Check 96 * Sequence to the packet 97 * 16 : reserved16 98 * 17 : l4_csum_partial - L4 partial checksum. when 99 * set to 0, the ENA calculates the L4 checksum, 100 * where the Destination Address required for the 101 * TCP/UDP pseudo-header is taken from the actual 102 * packet L3 header. when set to 1, the ENA doesn't 103 * calculate the sum of the pseudo-header, instead, 104 * the checksum field of the L4 is used instead. When 105 * TSO enabled, the checksum of the pseudo-header 106 * must not include the tcp length field. L4 partial 107 * checksum should be used for IPv6 packet that 108 * contains Routing Headers. 109 * 20:18 : reserved18 - MBZ 110 * 21 : reserved21 - MBZ 111 * 31:22 : req_id_lo - Request ID[9:0] 112 */ 113 uint32_t meta_ctrl; 114 115 uint32_t buff_addr_lo; 116 117 /* address high and header size 118 * 15:0 : addr_hi - Buffer Pointer[47:32] 119 * 23:16 : reserved16_w2 120 * 31:24 : header_length - Header length. For Low 121 * Latency Queues, this fields indicates the number 122 * of bytes written to the headers' memory. For 123 * normal queues, if packet is TCP or UDP, and longer 124 * than max_header_size, then this field should be 125 * set to the sum of L4 header offset and L4 header 126 * size(without options), otherwise, this field 127 * should be set to 0. For both modes, this field 128 * must not exceed the max_header_size. 129 * max_header_size value is reported by the Max 130 * Queues Feature descriptor 131 */ 132 uint32_t buff_addr_hi_hdr_sz; 133}; 134 135struct ena_eth_io_tx_meta_desc { 136 /* 9:0 : req_id_lo - Request ID[9:0] 137 * 11:10 : reserved10 - MBZ 138 * 12 : reserved12 - MBZ 139 * 13 : reserved13 - MBZ 140 * 14 : ext_valid - if set, offset fields in Word2 141 * are valid Also MSS High in Word 0 and bits [31:24] 142 * in Word 3 143 * 15 : reserved15 144 * 19:16 : mss_hi 145 * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1: 146 * Extended Metadata Descriptor 147 * 21 : meta_store - Store extended metadata in queue 148 * cache 149 * 22 : reserved22 - MBZ 150 * 23 : meta_desc - MBO 151 * 24 : phase 152 * 25 : reserved25 - MBZ 153 * 26 : first - Indicates first descriptor in 154 * transaction 155 * 27 : last - Indicates last descriptor in 156 * transaction 157 * 28 : comp_req - Indicates whether completion 158 * should be posted, after packet is transmitted. 159 * Valid only for first descriptor 160 * 30:29 : reserved29 - MBZ 161 * 31 : reserved31 - MBZ 162 */ 163 uint32_t len_ctrl; 164 165 /* 5:0 : req_id_hi 166 * 31:6 : reserved6 - MBZ 167 */ 168 uint32_t word1; 169 170 /* 7:0 : l3_hdr_len 171 * 15:8 : l3_hdr_off 172 * 21:16 : l4_hdr_len_in_words - counts the L4 header 173 * length in words. there is an explicit assumption 174 * that L4 header appears right after L3 header and 175 * L4 offset is based on l3_hdr_off+l3_hdr_len 176 * 31:22 : mss_lo 177 */ 178 uint32_t word2; 179 180 uint32_t reserved; 181}; 182 183struct ena_eth_io_tx_cdesc { 184 /* Request ID[15:0] */ 185 uint16_t req_id; 186 187 uint8_t status; 188 189 /* flags 190 * 0 : phase 191 * 7:1 : reserved1 192 */ 193 uint8_t flags; 194 195 uint16_t sub_qid; 196 197 uint16_t sq_head_idx; 198}; 199 200struct ena_eth_io_rx_desc { 201 /* In bytes. 0 means 64KB */ 202 uint16_t length; 203 204 /* MBZ */ 205 uint8_t reserved2; 206 207 /* 0 : phase 208 * 1 : reserved1 - MBZ 209 * 2 : first - Indicates first descriptor in 210 * transaction 211 * 3 : last - Indicates last descriptor in transaction 212 * 4 : comp_req 213 * 5 : reserved5 - MBO 214 * 7:6 : reserved6 - MBZ 215 */ 216 uint8_t ctrl; 217 218 uint16_t req_id; 219 220 /* MBZ */ 221 uint16_t reserved6; 222 223 uint32_t buff_addr_lo; 224 225 uint16_t buff_addr_hi; 226 227 /* MBZ */ 228 uint16_t reserved16_w3; 229}; 230 231/* 4-word format Note: all ethernet parsing information are valid only when 232 * last=1 233 */ 234struct ena_eth_io_rx_cdesc_base { 235 /* 4:0 : l3_proto_idx 236 * 6:5 : src_vlan_cnt 237 * 7 : reserved7 - MBZ 238 * 12:8 : l4_proto_idx 239 * 13 : l3_csum_err - when set, either the L3 240 * checksum error detected, or, the controller didn't 241 * validate the checksum. This bit is valid only when 242 * l3_proto_idx indicates IPv4 packet 243 * 14 : l4_csum_err - when set, either the L4 244 * checksum error detected, or, the controller didn't 245 * validate the checksum. This bit is valid only when 246 * l4_proto_idx indicates TCP/UDP packet, and, 247 * ipv4_frag is not set 248 * 15 : ipv4_frag - Indicates IPv4 fragmented packet 249 * 23:16 : reserved16 250 * 24 : phase 251 * 25 : l3_csum2 - second checksum engine result 252 * 26 : first - Indicates first descriptor in 253 * transaction 254 * 27 : last - Indicates last descriptor in 255 * transaction 256 * 29:28 : reserved28 257 * 30 : buffer - 0: Metadata descriptor. 1: Buffer 258 * Descriptor was used 259 * 31 : reserved31 260 */ 261 uint32_t status; 262 263 uint16_t length; 264 265 uint16_t req_id; 266 267 /* 32-bit hash result */ 268 uint32_t hash; 269 270 uint16_t sub_qid; 271 272 uint16_t reserved; 273}; 274 275/* 8-word format */ 276struct ena_eth_io_rx_cdesc_ext { 277 struct ena_eth_io_rx_cdesc_base base; 278 279 uint32_t buff_addr_lo; 280 281 uint16_t buff_addr_hi; 282 283 uint16_t reserved16; 284 285 uint32_t reserved_w6; 286 287 uint32_t reserved_w7; 288}; 289 290struct ena_eth_io_intr_reg { 291 /* 14:0 : rx_intr_delay 292 * 29:15 : tx_intr_delay 293 * 30 : intr_unmask 294 * 31 : reserved 295 */ 296 uint32_t intr_control; 297}; 298 299struct ena_eth_io_numa_node_cfg_reg { 300 /* 7:0 : numa 301 * 30:8 : reserved 302 * 31 : enabled 303 */ 304 uint32_t numa_cfg; 305}; 306 307/* tx_desc */ 308#define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0) 309#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16 310#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16) 311#define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23 312#define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23) 313#define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24 314#define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24) 315#define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26 316#define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26) 317#define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27 318#define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27) 319#define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28 320#define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28) 321#define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0) 322#define ENA_ETH_IO_TX_DESC_DF_SHIFT 4 323#define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4) 324#define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7 325#define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7) 326#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8 327#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8) 328#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13 329#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13) 330#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14 331#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14) 332#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15 333#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15) 334#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17 335#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17) 336#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22 337#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22) 338#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0) 339#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24 340#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24) 341 342/* tx_meta_desc */ 343#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0) 344#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14 345#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14) 346#define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16 347#define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16) 348#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20 349#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20) 350#define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21 351#define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21) 352#define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23 353#define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23) 354#define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24 355#define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24) 356#define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26 357#define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26) 358#define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27 359#define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27) 360#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28 361#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28) 362#define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0) 363#define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0) 364#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8 365#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8) 366#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16 367#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16) 368#define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22 369#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22) 370 371/* tx_cdesc */ 372#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0) 373 374/* rx_desc */ 375#define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0) 376#define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2 377#define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2) 378#define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3 379#define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3) 380#define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4 381#define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4) 382 383/* rx_cdesc_base */ 384#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0) 385#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5 386#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5) 387#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8 388#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8) 389#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13 390#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13) 391#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14 392#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14) 393#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15 394#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15) 395#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24 396#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24) 397#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25 398#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25) 399#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26 400#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26) 401#define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27 402#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27) 403#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30 404#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30) 405 406/* intr_reg */ 407#define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0) 408#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15 409#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15) 410#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30 411#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30) 412 413/* numa_node_cfg_reg */ 414#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0) 415#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31 416#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31) 417 418#if !defined(ENA_DEFS_LINUX_MAINLINE) 419static inline uint32_t get_ena_eth_io_tx_desc_length(const struct ena_eth_io_tx_desc *p) 420{ 421 return p->len_ctrl & ENA_ETH_IO_TX_DESC_LENGTH_MASK; 422} 423 424static inline void set_ena_eth_io_tx_desc_length(struct ena_eth_io_tx_desc *p, uint32_t val) 425{ 426 p->len_ctrl |= val & ENA_ETH_IO_TX_DESC_LENGTH_MASK; 427} 428 429static inline uint32_t get_ena_eth_io_tx_desc_req_id_hi(const struct ena_eth_io_tx_desc *p) 430{ 431 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT; 432} 433 434static inline void set_ena_eth_io_tx_desc_req_id_hi(struct ena_eth_io_tx_desc *p, uint32_t val) 435{ 436 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK; 437} 438 439static inline uint32_t get_ena_eth_io_tx_desc_meta_desc(const struct ena_eth_io_tx_desc *p) 440{ 441 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_DESC_META_DESC_SHIFT; 442} 443 444static inline void set_ena_eth_io_tx_desc_meta_desc(struct ena_eth_io_tx_desc *p, uint32_t val) 445{ 446 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_DESC_META_DESC_MASK; 447} 448 449static inline uint32_t get_ena_eth_io_tx_desc_phase(const struct ena_eth_io_tx_desc *p) 450{ 451 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_DESC_PHASE_SHIFT; 452} 453 454static inline void set_ena_eth_io_tx_desc_phase(struct ena_eth_io_tx_desc *p, uint32_t val) 455{ 456 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_DESC_PHASE_MASK; 457} 458 459static inline uint32_t get_ena_eth_io_tx_desc_first(const struct ena_eth_io_tx_desc *p) 460{ 461 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_DESC_FIRST_SHIFT; 462} 463 464static inline void set_ena_eth_io_tx_desc_first(struct ena_eth_io_tx_desc *p, uint32_t val) 465{ 466 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_DESC_FIRST_MASK; 467} 468 469static inline uint32_t get_ena_eth_io_tx_desc_last(const struct ena_eth_io_tx_desc *p) 470{ 471 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_LAST_MASK) >> ENA_ETH_IO_TX_DESC_LAST_SHIFT; 472} 473 474static inline void set_ena_eth_io_tx_desc_last(struct ena_eth_io_tx_desc *p, uint32_t val) 475{ 476 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_DESC_LAST_MASK; 477} 478 479static inline uint32_t get_ena_eth_io_tx_desc_comp_req(const struct ena_eth_io_tx_desc *p) 480{ 481 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT; 482} 483 484static inline void set_ena_eth_io_tx_desc_comp_req(struct ena_eth_io_tx_desc *p, uint32_t val) 485{ 486 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK; 487} 488 489static inline uint32_t get_ena_eth_io_tx_desc_l3_proto_idx(const struct ena_eth_io_tx_desc *p) 490{ 491 return p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK; 492} 493 494static inline void set_ena_eth_io_tx_desc_l3_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val) 495{ 496 p->meta_ctrl |= val & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK; 497} 498 499static inline uint32_t get_ena_eth_io_tx_desc_DF(const struct ena_eth_io_tx_desc *p) 500{ 501 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_DF_MASK) >> ENA_ETH_IO_TX_DESC_DF_SHIFT; 502} 503 504static inline void set_ena_eth_io_tx_desc_DF(struct ena_eth_io_tx_desc *p, uint32_t val) 505{ 506 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_DF_SHIFT) & ENA_ETH_IO_TX_DESC_DF_MASK; 507} 508 509static inline uint32_t get_ena_eth_io_tx_desc_tso_en(const struct ena_eth_io_tx_desc *p) 510{ 511 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TSO_EN_MASK) >> ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT; 512} 513 514static inline void set_ena_eth_io_tx_desc_tso_en(struct ena_eth_io_tx_desc *p, uint32_t val) 515{ 516 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT) & ENA_ETH_IO_TX_DESC_TSO_EN_MASK; 517} 518 519static inline uint32_t get_ena_eth_io_tx_desc_l4_proto_idx(const struct ena_eth_io_tx_desc *p) 520{ 521 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT; 522} 523 524static inline void set_ena_eth_io_tx_desc_l4_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val) 525{ 526 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK; 527} 528 529static inline uint32_t get_ena_eth_io_tx_desc_l3_csum_en(const struct ena_eth_io_tx_desc *p) 530{ 531 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT; 532} 533 534static inline void set_ena_eth_io_tx_desc_l3_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val) 535{ 536 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK; 537} 538 539static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_en(const struct ena_eth_io_tx_desc *p) 540{ 541 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT; 542} 543 544static inline void set_ena_eth_io_tx_desc_l4_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val) 545{ 546 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK; 547} 548 549static inline uint32_t get_ena_eth_io_tx_desc_ethernet_fcs_dis(const struct ena_eth_io_tx_desc *p) 550{ 551 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK) >> ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT; 552} 553 554static inline void set_ena_eth_io_tx_desc_ethernet_fcs_dis(struct ena_eth_io_tx_desc *p, uint32_t val) 555{ 556 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT) & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK; 557} 558 559static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_partial(const struct ena_eth_io_tx_desc *p) 560{ 561 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT; 562} 563 564static inline void set_ena_eth_io_tx_desc_l4_csum_partial(struct ena_eth_io_tx_desc *p, uint32_t val) 565{ 566 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK; 567} 568 569static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(const struct ena_eth_io_tx_desc *p) 570{ 571 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT; 572} 573 574static inline void set_ena_eth_io_tx_desc_req_id_lo(struct ena_eth_io_tx_desc *p, uint32_t val) 575{ 576 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK; 577} 578 579static inline uint32_t get_ena_eth_io_tx_desc_addr_hi(const struct ena_eth_io_tx_desc *p) 580{ 581 return p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK; 582} 583 584static inline void set_ena_eth_io_tx_desc_addr_hi(struct ena_eth_io_tx_desc *p, uint32_t val) 585{ 586 p->buff_addr_hi_hdr_sz |= val & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK; 587} 588 589static inline uint32_t get_ena_eth_io_tx_desc_header_length(const struct ena_eth_io_tx_desc *p) 590{ 591 return (p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK) >> ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT; 592} 593 594static inline void set_ena_eth_io_tx_desc_header_length(struct ena_eth_io_tx_desc *p, uint32_t val) 595{ 596 p->buff_addr_hi_hdr_sz |= (val << ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK; 597} 598 599static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_lo(const struct ena_eth_io_tx_meta_desc *p) 600{ 601 return p->len_ctrl & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK; 602} 603 604static inline void set_ena_eth_io_tx_meta_desc_req_id_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 605{ 606 p->len_ctrl |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK; 607} 608 609static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(const struct ena_eth_io_tx_meta_desc *p) 610{ 611 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK) >> ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT; 612} 613 614static inline void set_ena_eth_io_tx_meta_desc_ext_valid(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 615{ 616 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT) & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK; 617} 618 619static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_hi(const struct ena_eth_io_tx_meta_desc *p) 620{ 621 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT; 622} 623 624static inline void set_ena_eth_io_tx_meta_desc_mss_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 625{ 626 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK; 627} 628 629static inline uint32_t get_ena_eth_io_tx_meta_desc_eth_meta_type(const struct ena_eth_io_tx_meta_desc *p) 630{ 631 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK) >> ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT; 632} 633 634static inline void set_ena_eth_io_tx_meta_desc_eth_meta_type(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 635{ 636 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT) & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK; 637} 638 639static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_store(const struct ena_eth_io_tx_meta_desc *p) 640{ 641 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK) >> ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT; 642} 643 644static inline void set_ena_eth_io_tx_meta_desc_meta_store(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 645{ 646 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK; 647} 648 649static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_desc(const struct ena_eth_io_tx_meta_desc *p) 650{ 651 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT; 652} 653 654static inline void set_ena_eth_io_tx_meta_desc_meta_desc(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 655{ 656 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK; 657} 658 659static inline uint32_t get_ena_eth_io_tx_meta_desc_phase(const struct ena_eth_io_tx_meta_desc *p) 660{ 661 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT; 662} 663 664static inline void set_ena_eth_io_tx_meta_desc_phase(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 665{ 666 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_META_DESC_PHASE_MASK; 667} 668 669static inline uint32_t get_ena_eth_io_tx_meta_desc_first(const struct ena_eth_io_tx_meta_desc *p) 670{ 671 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT; 672} 673 674static inline void set_ena_eth_io_tx_meta_desc_first(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 675{ 676 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_META_DESC_FIRST_MASK; 677} 678 679static inline uint32_t get_ena_eth_io_tx_meta_desc_last(const struct ena_eth_io_tx_meta_desc *p) 680{ 681 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_LAST_MASK) >> ENA_ETH_IO_TX_META_DESC_LAST_SHIFT; 682} 683 684static inline void set_ena_eth_io_tx_meta_desc_last(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 685{ 686 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_META_DESC_LAST_MASK; 687} 688 689static inline uint32_t get_ena_eth_io_tx_meta_desc_comp_req(const struct ena_eth_io_tx_meta_desc *p) 690{ 691 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT; 692} 693 694static inline void set_ena_eth_io_tx_meta_desc_comp_req(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 695{ 696 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK; 697} 698 699static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_hi(const struct ena_eth_io_tx_meta_desc *p) 700{ 701 return p->word1 & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK; 702} 703 704static inline void set_ena_eth_io_tx_meta_desc_req_id_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 705{ 706 p->word1 |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK; 707} 708 709static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_len(const struct ena_eth_io_tx_meta_desc *p) 710{ 711 return p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK; 712} 713 714static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_len(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 715{ 716 p->word2 |= val & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK; 717} 718 719static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_off(const struct ena_eth_io_tx_meta_desc *p) 720{ 721 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK) >> ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT; 722} 723 724static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_off(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 725{ 726 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK; 727} 728 729static inline uint32_t get_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(const struct ena_eth_io_tx_meta_desc *p) 730{ 731 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK) >> ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT; 732} 733 734static inline void set_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 735{ 736 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK; 737} 738 739static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_lo(const struct ena_eth_io_tx_meta_desc *p) 740{ 741 return (p->word2 & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT; 742} 743 744static inline void set_ena_eth_io_tx_meta_desc_mss_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 745{ 746 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK; 747} 748 749static inline uint8_t get_ena_eth_io_tx_cdesc_phase(const struct ena_eth_io_tx_cdesc *p) 750{ 751 return p->flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK; 752} 753 754static inline void set_ena_eth_io_tx_cdesc_phase(struct ena_eth_io_tx_cdesc *p, uint8_t val) 755{ 756 p->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK; 757} 758 759static inline uint8_t get_ena_eth_io_rx_desc_phase(const struct ena_eth_io_rx_desc *p) 760{ 761 return p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK; 762} 763 764static inline void set_ena_eth_io_rx_desc_phase(struct ena_eth_io_rx_desc *p, uint8_t val) 765{ 766 p->ctrl |= val & ENA_ETH_IO_RX_DESC_PHASE_MASK; 767} 768 769static inline uint8_t get_ena_eth_io_rx_desc_first(const struct ena_eth_io_rx_desc *p) 770{ 771 return (p->ctrl & ENA_ETH_IO_RX_DESC_FIRST_MASK) >> ENA_ETH_IO_RX_DESC_FIRST_SHIFT; 772} 773 774static inline void set_ena_eth_io_rx_desc_first(struct ena_eth_io_rx_desc *p, uint8_t val) 775{ 776 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_FIRST_SHIFT) & ENA_ETH_IO_RX_DESC_FIRST_MASK; 777} 778 779static inline uint8_t get_ena_eth_io_rx_desc_last(const struct ena_eth_io_rx_desc *p) 780{ 781 return (p->ctrl & ENA_ETH_IO_RX_DESC_LAST_MASK) >> ENA_ETH_IO_RX_DESC_LAST_SHIFT; 782} 783 784static inline void set_ena_eth_io_rx_desc_last(struct ena_eth_io_rx_desc *p, uint8_t val) 785{ 786 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_LAST_SHIFT) & ENA_ETH_IO_RX_DESC_LAST_MASK; 787} 788 789static inline uint8_t get_ena_eth_io_rx_desc_comp_req(const struct ena_eth_io_rx_desc *p) 790{ 791 return (p->ctrl & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT; 792} 793 794static inline void set_ena_eth_io_rx_desc_comp_req(struct ena_eth_io_rx_desc *p, uint8_t val) 795{ 796 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK; 797} 798 799static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_proto_idx(const struct ena_eth_io_rx_cdesc_base *p) 800{ 801 return p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; 802} 803 804static inline void set_ena_eth_io_rx_cdesc_base_l3_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 805{ 806 p->status |= val & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; 807} 808 809static inline uint32_t get_ena_eth_io_rx_cdesc_base_src_vlan_cnt(const struct ena_eth_io_rx_cdesc_base *p) 810{ 811 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT; 812} 813 814static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 815{ 816 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK; 817} 818 819static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(const struct ena_eth_io_rx_cdesc_base *p) 820{ 821 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT; 822} 823 824static inline void set_ena_eth_io_rx_cdesc_base_l4_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 825{ 826 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK; 827} 828 829static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum_err(const struct ena_eth_io_rx_cdesc_base *p) 830{ 831 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT; 832} 833 834static inline void set_ena_eth_io_rx_cdesc_base_l3_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 835{ 836 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK; 837} 838 839static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_err(const struct ena_eth_io_rx_cdesc_base *p) 840{ 841 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT; 842} 843 844static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 845{ 846 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK; 847} 848 849static inline uint32_t get_ena_eth_io_rx_cdesc_base_ipv4_frag(const struct ena_eth_io_rx_cdesc_base *p) 850{ 851 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT; 852} 853 854static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 855{ 856 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK; 857} 858 859static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(const struct ena_eth_io_rx_cdesc_base *p) 860{ 861 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT; 862} 863 864static inline void set_ena_eth_io_rx_cdesc_base_phase(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 865{ 866 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK; 867} 868 869static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum2(const struct ena_eth_io_rx_cdesc_base *p) 870{ 871 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT; 872} 873 874static inline void set_ena_eth_io_rx_cdesc_base_l3_csum2(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 875{ 876 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK; 877} 878 879static inline uint32_t get_ena_eth_io_rx_cdesc_base_first(const struct ena_eth_io_rx_cdesc_base *p) 880{ 881 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT; 882} 883 884static inline void set_ena_eth_io_rx_cdesc_base_first(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 885{ 886 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK; 887} 888 889static inline uint32_t get_ena_eth_io_rx_cdesc_base_last(const struct ena_eth_io_rx_cdesc_base *p) 890{ 891 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT; 892} 893 894static inline void set_ena_eth_io_rx_cdesc_base_last(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 895{ 896 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK; 897} 898 899static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(const struct ena_eth_io_rx_cdesc_base *p) 900{ 901 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT; 902} 903 904static inline void set_ena_eth_io_rx_cdesc_base_buffer(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 905{ 906 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK; 907} 908 909static inline uint32_t get_ena_eth_io_intr_reg_rx_intr_delay(const struct ena_eth_io_intr_reg *p) 910{ 911 return p->intr_control & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; 912} 913 914static inline void set_ena_eth_io_intr_reg_rx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val) 915{ 916 p->intr_control |= val & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; 917} 918 919static inline uint32_t get_ena_eth_io_intr_reg_tx_intr_delay(const struct ena_eth_io_intr_reg *p) 920{ 921 return (p->intr_control & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK) >> ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT; 922} 923 924static inline void set_ena_eth_io_intr_reg_tx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val) 925{ 926 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK; 927} 928 929static inline uint32_t get_ena_eth_io_intr_reg_intr_unmask(const struct ena_eth_io_intr_reg *p) 930{ 931 return (p->intr_control & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK) >> ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT; 932} 933 934static inline void set_ena_eth_io_intr_reg_intr_unmask(struct ena_eth_io_intr_reg *p, uint32_t val) 935{ 936 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT) & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK; 937} 938 939static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_numa(const struct ena_eth_io_numa_node_cfg_reg *p) 940{ 941 return p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK; 942} 943 944static inline void set_ena_eth_io_numa_node_cfg_reg_numa(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val) 945{ 946 p->numa_cfg |= val & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK; 947} 948 949static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_enabled(const struct ena_eth_io_numa_node_cfg_reg *p) 950{ 951 return (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK) >> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT; 952} 953 954static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val) 955{ 956 p->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT) & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK; 957} 958 959#endif /* !defined(ENA_DEFS_LINUX_MAINLINE) */ 960#endif /*_ENA_ETH_IO_H_ */ 961