1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD$"); 30 31#include <sys/param.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/module.h> 35#include <sys/mutex.h> 36#include <sys/rman.h> 37#include <machine/bus.h> 38 39#include <dev/ofw/ofw_bus.h> 40#include <dev/ofw/ofw_bus_subr.h> 41 42#include <dev/iicbus/iiconf.h> 43#include <dev/iicbus/iicbus.h> 44 45#include <dev/extres/clk/clk.h> 46 47#include "iicbus_if.h" 48 49 50#define RK_I2C_CON 0x00 51#define RK_I2C_CON_EN (1 << 0) 52#define RK_I2C_CON_MODE_SHIFT 1 53#define RK_I2C_CON_MODE_TX 0 54#define RK_I2C_CON_MODE_RRX 1 55#define RK_I2C_CON_MODE_RX 2 56#define RK_I2C_CON_MODE_RTX 3 57#define RK_I2C_CON_MODE_MASK 0x6 58#define RK_I2C_CON_START (1 << 3) 59#define RK_I2C_CON_STOP (1 << 4) 60#define RK_I2C_CON_LASTACK (1 << 5) 61#define RK_I2C_CON_NAKSTOP (1 << 6) 62#define RK_I2C_CON_CTRL_MASK 0xFF 63 64#define RK_I2C_CLKDIV 0x04 65#define RK_I2C_CLKDIVL_MASK 0xFFFF 66#define RK_I2C_CLKDIVL_SHIFT 0 67#define RK_I2C_CLKDIVH_MASK 0xFFFF0000 68#define RK_I2C_CLKDIVH_SHIFT 16 69#define RK_I2C_CLKDIV_MUL 8 70 71#define RK_I2C_MRXADDR 0x08 72#define RK_I2C_MRXADDR_SADDR_MASK 0xFFFFFF 73#define RK_I2C_MRXADDR_VALID(x) (1 << (24 + x)) 74 75#define RK_I2C_MRXRADDR 0x0C 76#define RK_I2C_MRXRADDR_SRADDR_MASK 0xFFFFFF 77#define RK_I2C_MRXRADDR_VALID(x) (1 << (24 + x)) 78 79#define RK_I2C_MTXCNT 0x10 80#define RK_I2C_MTXCNT_MASK 0x3F 81 82#define RK_I2C_MRXCNT 0x14 83#define RK_I2C_MRXCNT_MASK 0x3F 84 85#define RK_I2C_IEN 0x18 86#define RK_I2C_IEN_BTFIEN (1 << 0) 87#define RK_I2C_IEN_BRFIEN (1 << 1) 88#define RK_I2C_IEN_MBTFIEN (1 << 2) 89#define RK_I2C_IEN_MBRFIEN (1 << 3) 90#define RK_I2C_IEN_STARTIEN (1 << 4) 91#define RK_I2C_IEN_STOPIEN (1 << 5) 92#define RK_I2C_IEN_NAKRCVIEN (1 << 6) 93#define RK_I2C_IEN_ALL (RK_I2C_IEN_MBTFIEN | RK_I2C_IEN_MBRFIEN | \ 94 RK_I2C_IEN_STARTIEN | RK_I2C_IEN_STOPIEN | RK_I2C_IEN_NAKRCVIEN) 95 96#define RK_I2C_IPD 0x1C 97#define RK_I2C_IPD_BTFIPD (1 << 0) 98#define RK_I2C_IPD_BRFIPD (1 << 1) 99#define RK_I2C_IPD_MBTFIPD (1 << 2) 100#define RK_I2C_IPD_MBRFIPD (1 << 3) 101#define RK_I2C_IPD_STARTIPD (1 << 4) 102#define RK_I2C_IPD_STOPIPD (1 << 5) 103#define RK_I2C_IPD_NAKRCVIPD (1 << 6) 104#define RK_I2C_IPD_ALL (RK_I2C_IPD_MBTFIPD | RK_I2C_IPD_MBRFIPD | \ 105 RK_I2C_IPD_STARTIPD | RK_I2C_IPD_STOPIPD | RK_I2C_IPD_NAKRCVIPD) 106 107#define RK_I2C_FNCT 0x20 108#define RK_I2C_FNCT_MASK 0x3F 109 110#define RK_I2C_TXDATA_BASE 0x100 111 112#define RK_I2C_RXDATA_BASE 0x200 113 114enum rk_i2c_state { 115 STATE_IDLE = 0, 116 STATE_START, 117 STATE_READ, 118 STATE_WRITE, 119 STATE_STOP 120}; 121 122struct rk_i2c_softc { 123 device_t dev; 124 struct resource *res[2]; 125 struct mtx mtx; 126 clk_t sclk; 127 clk_t pclk; 128 int busy; 129 void * intrhand; 130 uint32_t intr; 131 uint32_t ipd; 132 struct iic_msg *msg; 133 size_t cnt; 134 int msg_len; 135 bool transfer_done; 136 bool nak_recv; 137 bool tx_slave_addr; 138 uint8_t mode; 139 uint8_t state; 140 141 device_t iicbus; 142}; 143 144static struct ofw_compat_data compat_data[] = { 145 {"rockchip,rk3288-i2c", 1}, 146 {"rockchip,rk3328-i2c", 1}, 147 {"rockchip,rk3399-i2c", 1}, 148 {NULL, 0} 149}; 150 151static struct resource_spec rk_i2c_spec[] = { 152 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 153 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 154 { -1, 0 } 155}; 156 157static int rk_i2c_probe(device_t dev); 158static int rk_i2c_attach(device_t dev); 159static int rk_i2c_detach(device_t dev); 160 161#define RK_I2C_LOCK(sc) mtx_lock(&(sc)->mtx) 162#define RK_I2C_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 163#define RK_I2C_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 164#define RK_I2C_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) 165#define RK_I2C_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 166 167static uint32_t 168rk_i2c_get_clkdiv(struct rk_i2c_softc *sc, uint32_t speed) 169{ 170 uint64_t sclk_freq; 171 uint32_t clkdiv; 172 int err; 173 174 err = clk_get_freq(sc->sclk, &sclk_freq); 175 if (err != 0) 176 return (err); 177 178 clkdiv = (sclk_freq / speed / RK_I2C_CLKDIV_MUL / 2) - 1; 179 clkdiv &= RK_I2C_CLKDIVL_MASK; 180 181 clkdiv = clkdiv << RK_I2C_CLKDIVH_SHIFT | clkdiv; 182 183 return (clkdiv); 184} 185 186static int 187rk_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 188{ 189 struct rk_i2c_softc *sc; 190 uint32_t clkdiv; 191 u_int busfreq; 192 193 sc = device_get_softc(dev); 194 195 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); 196 197 clkdiv = rk_i2c_get_clkdiv(sc, busfreq); 198 199 RK_I2C_LOCK(sc); 200 201 /* Set the clock divider */ 202 RK_I2C_WRITE(sc, RK_I2C_CLKDIV, clkdiv); 203 204 /* Disable the module */ 205 RK_I2C_WRITE(sc, RK_I2C_CON, 0); 206 207 RK_I2C_UNLOCK(sc); 208 209 return (0); 210} 211 212static uint8_t 213rk_i2c_fill_tx(struct rk_i2c_softc *sc) 214{ 215 uint32_t buf32; 216 uint8_t buf; 217 int i, j, len; 218 219 if (sc->msg == NULL || sc->msg->len == sc->cnt) 220 return (0); 221 222 len = sc->msg->len - sc->cnt; 223 if (len > 8) 224 len = 8; 225 226 for (i = 0; i < len; i++) { 227 buf32 = 0; 228 for (j = 0; j < 4 ; j++) { 229 if (sc->cnt == sc->msg->len) 230 break; 231 232 /* Fill the addr if needed */ 233 if (sc->cnt == 0 && sc->tx_slave_addr) { 234 buf = sc->msg->slave; 235 sc->tx_slave_addr = false; 236 } else { 237 buf = sc->msg->buf[sc->cnt]; 238 sc->cnt++; 239 } 240 buf32 |= buf << (j * 8); 241 242 } 243 RK_I2C_WRITE(sc, RK_I2C_TXDATA_BASE + 4 * i, buf32); 244 245 if (sc->cnt == sc->msg->len) 246 break; 247 } 248 249 return (uint8_t)len; 250} 251 252static void 253rk_i2c_drain_rx(struct rk_i2c_softc *sc) 254{ 255 uint32_t buf32 = 0; 256 uint8_t buf8; 257 int len; 258 int i; 259 260 if (sc->msg == NULL) { 261 device_printf(sc->dev, "No current iic msg\n"); 262 return; 263 } 264 265 len = sc->msg->len - sc->cnt; 266 if (len > 32) 267 len = 32; 268 269 for (i = 0; i < len; i++) { 270 if (i % 4 == 0) 271 buf32 = RK_I2C_READ(sc, RK_I2C_RXDATA_BASE + (i / 4) * 4); 272 273 buf8 = (buf32 >> ((i % 4) * 8)) & 0xFF; 274 sc->msg->buf[sc->cnt++] = buf8; 275 } 276} 277 278static void 279rk_i2c_send_stop(struct rk_i2c_softc *sc) 280{ 281 uint32_t reg; 282 283 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STOPIEN); 284 285 sc->state = STATE_STOP; 286 287 reg = RK_I2C_READ(sc, RK_I2C_CON); 288 reg |= RK_I2C_CON_STOP; 289 RK_I2C_WRITE(sc, RK_I2C_CON, reg); 290} 291 292static void 293rk_i2c_intr_locked(struct rk_i2c_softc *sc) 294{ 295 uint32_t reg; 296 297 sc->ipd = RK_I2C_READ(sc, RK_I2C_IPD); 298 299 /* Something to handle? */ 300 if ((sc->ipd & RK_I2C_IPD_ALL) == 0) 301 return; 302 303 RK_I2C_WRITE(sc, RK_I2C_IPD, sc->ipd); 304 sc->ipd &= RK_I2C_IPD_ALL; 305 306 if (sc->ipd & RK_I2C_IPD_NAKRCVIPD) { 307 /* NACK received */ 308 sc->ipd &= ~RK_I2C_IPD_NAKRCVIPD; 309 sc->nak_recv = 1; 310 /* XXXX last byte !!!, signal error !!! */ 311 sc->transfer_done = 1; 312 sc->state = STATE_IDLE; 313 goto err; 314 } 315 316 switch (sc->state) { 317 case STATE_START: 318 /* Disable start bit */ 319 reg = RK_I2C_READ(sc, RK_I2C_CON); 320 reg &= ~RK_I2C_CON_START; 321 RK_I2C_WRITE(sc, RK_I2C_CON, reg); 322 323 if (sc->mode == RK_I2C_CON_MODE_RRX || 324 sc->mode == RK_I2C_CON_MODE_RX) { 325 sc->state = STATE_READ; 326 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN | 327 RK_I2C_IEN_NAKRCVIEN); 328 329 reg = RK_I2C_READ(sc, RK_I2C_CON); 330 reg |= RK_I2C_CON_LASTACK; 331 RK_I2C_WRITE(sc, RK_I2C_CON, reg); 332 333 RK_I2C_WRITE(sc, RK_I2C_MRXCNT, sc->msg->len); 334 } else { 335 sc->state = STATE_WRITE; 336 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN | 337 RK_I2C_IEN_NAKRCVIEN); 338 339 sc->msg->len += 1; 340 rk_i2c_fill_tx(sc); 341 RK_I2C_WRITE(sc, RK_I2C_MTXCNT, sc->msg->len); 342 } 343 break; 344 case STATE_READ: 345 rk_i2c_drain_rx(sc); 346 347 if (sc->cnt == sc->msg->len) 348 rk_i2c_send_stop(sc); 349 350 break; 351 case STATE_WRITE: 352 if (sc->cnt == sc->msg->len && 353 !(sc->msg->flags & IIC_M_NOSTOP)) { 354 rk_i2c_send_stop(sc); 355 break; 356 } 357 /* passthru */ 358 case STATE_STOP: 359 /* Disable stop bit */ 360 reg = RK_I2C_READ(sc, RK_I2C_CON); 361 reg &= ~RK_I2C_CON_STOP; 362 RK_I2C_WRITE(sc, RK_I2C_CON, reg); 363 364 sc->transfer_done = 1; 365 sc->state = STATE_IDLE; 366 break; 367 case STATE_IDLE: 368 break; 369 } 370 371err: 372 wakeup(sc); 373} 374 375static void 376rk_i2c_intr(void *arg) 377{ 378 struct rk_i2c_softc *sc; 379 380 sc = (struct rk_i2c_softc *)arg; 381 382 RK_I2C_LOCK(sc); 383 rk_i2c_intr_locked(sc); 384 RK_I2C_UNLOCK(sc); 385} 386 387static void 388rk_i2c_start_xfer(struct rk_i2c_softc *sc, struct iic_msg *msg, boolean_t last) 389{ 390 uint32_t reg; 391 uint8_t len; 392 393 sc->transfer_done = false; 394 sc->nak_recv = false; 395 sc->tx_slave_addr = false; 396 sc->cnt = 0; 397 sc->state = STATE_IDLE; 398 sc->msg = msg; 399 sc->msg_len = sc->msg->len; 400 401 reg = RK_I2C_READ(sc, RK_I2C_CON) & ~RK_I2C_CON_CTRL_MASK; 402 if (!(sc->msg->flags & IIC_M_NOSTART)) { 403 /* Stadard message */ 404 if (sc->mode == RK_I2C_CON_MODE_TX) { 405 sc->msg_len++; /* Take slave address in account. */ 406 sc->tx_slave_addr = true; 407 } 408 sc->state = STATE_START; 409 reg |= RK_I2C_CON_START; 410 411 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STARTIEN); 412 } else { 413 /* Continuation message */ 414 if (sc->mode == RK_I2C_CON_MODE_RX) { 415 sc->state = STATE_READ; 416 if (last) 417 reg |= RK_I2C_CON_LASTACK; 418 419 RK_I2C_WRITE(sc, RK_I2C_MRXCNT, sc->msg->len); 420 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN | 421 RK_I2C_IEN_NAKRCVIEN); 422 } else { 423 sc->state = STATE_WRITE; 424 len = rk_i2c_fill_tx(sc); 425 426 RK_I2C_WRITE(sc, RK_I2C_MTXCNT, len); 427 428 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN | 429 RK_I2C_IEN_NAKRCVIEN); 430 } 431 } 432 reg |= sc->mode << RK_I2C_CON_MODE_SHIFT; 433 reg |= RK_I2C_CON_EN; 434 RK_I2C_WRITE(sc, RK_I2C_CON, reg); 435} 436 437static int 438rk_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 439{ 440 struct rk_i2c_softc *sc; 441 uint32_t reg; 442 bool last_msg; 443 int i, j, timeout, err; 444 445 sc = device_get_softc(dev); 446 447 RK_I2C_LOCK(sc); 448 449 while (sc->busy) 450 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0); 451 sc->busy = 1; 452 453 /* Disable the module and interrupts */ 454 RK_I2C_WRITE(sc, RK_I2C_CON, 0); 455 RK_I2C_WRITE(sc, RK_I2C_IEN, 0); 456 457 /* Clean stale interrupts */ 458 RK_I2C_WRITE(sc, RK_I2C_IPD, RK_I2C_IPD_ALL); 459 460 err = 0; 461 for (i = 0; i < nmsgs; i++) { 462 /* Validate parameters. */ 463 if (msgs == NULL || msgs[i].buf == NULL || 464 msgs[i].len == 0) { 465 err = EINVAL; 466 break; 467 } 468 /* 469 * If next message have NOSTART flag, then they both 470 * should be same type (read/write) and same address. 471 */ 472 if (i < nmsgs - 1) { 473 if ((msgs[i + 1].flags & IIC_M_NOSTART) && 474 ((msgs[i].flags & IIC_M_RD) != 475 (msgs[i + 1].flags & IIC_M_RD) || 476 (msgs[i].slave != msgs[i + 1].slave))) { 477 err = EINVAL; 478 break; 479 } 480 } 481 /* 482 * Detect simple register read case. 483 * The first message should be IIC_M_WR | IIC_M_NOSTOP, 484 * next pure IIC_M_RD (no other flags allowed). Both 485 * messages should have same slave address. 486 */ 487 488 if (nmsgs - i >= 2 && msgs[i].len < 4 && 489 msgs[i].flags == (IIC_M_WR | IIC_M_NOSTOP) && 490 msgs[i + 1].flags == IIC_M_RD && 491 (msgs[i].slave & ~LSB) == (msgs[i + 1].slave & ~LSB)) { 492 sc->mode = RK_I2C_CON_MODE_RRX; 493 494 /* Write slave address */ 495 reg = msgs[i].slave & ~LSB; 496 reg |= RK_I2C_MRXADDR_VALID(0); 497 RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg); 498 499 /* Write slave register address */ 500 reg = 0; 501 for (j = 0; j < msgs[i].len ; j++) { 502 reg |= (msgs[i].buf[j] & 0xff) << (j * 8); 503 reg |= RK_I2C_MRXADDR_VALID(j); 504 } 505 RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, reg); 506 507 i++; 508 } else { 509 if (msgs[i].flags & IIC_M_RD) { 510 if (msgs[i].flags & IIC_M_NOSTART) { 511 sc->mode = RK_I2C_CON_MODE_RX; 512 } else { 513 sc->mode = RK_I2C_CON_MODE_RRX; 514 reg = msgs[i].slave & LSB; 515 reg |= RK_I2C_MRXADDR_VALID(0); 516 RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg); 517 RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, 0); 518 } 519 } else { 520 sc->mode = RK_I2C_CON_MODE_TX; 521 } 522 } 523 /* last message ? */ 524 last_msg = (i > nmsgs - 1) || 525 !(msgs[i + 1].flags & IIC_M_NOSTART); 526 rk_i2c_start_xfer(sc, msgs + i, last_msg); 527 528 if (cold) { 529 for(timeout = 10000; timeout > 0; timeout--) { 530 rk_i2c_intr_locked(sc); 531 if (sc->transfer_done != 0) 532 break; 533 DELAY(1000); 534 } 535 if (timeout <= 0) 536 err = ETIMEDOUT; 537 } else { 538 while (err == 0 && sc->transfer_done != 1) { 539 err = msleep(sc, &sc->mtx, PZERO, "rk_i2c", 540 10 * hz); 541 } 542 } 543 } 544 545 /* Disable the module and interrupts */ 546 RK_I2C_WRITE(sc, RK_I2C_CON, 0); 547 RK_I2C_WRITE(sc, RK_I2C_IEN, 0); 548 549 sc->busy = 0; 550 551 RK_I2C_UNLOCK(sc); 552 return (err); 553} 554 555static int 556rk_i2c_probe(device_t dev) 557{ 558 559 if (!ofw_bus_status_okay(dev)) 560 return (ENXIO); 561 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 562 return (ENXIO); 563 564 device_set_desc(dev, "RockChip I2C"); 565 return (BUS_PROBE_DEFAULT); 566} 567 568static int 569rk_i2c_attach(device_t dev) 570{ 571 struct rk_i2c_softc *sc; 572 int error; 573 574 sc = device_get_softc(dev); 575 sc->dev = dev; 576 577 mtx_init(&sc->mtx, device_get_nameunit(dev), "rk_i2c", MTX_DEF); 578 579 if (bus_alloc_resources(dev, rk_i2c_spec, sc->res) != 0) { 580 device_printf(dev, "cannot allocate resources for device\n"); 581 error = ENXIO; 582 goto fail; 583 } 584 585 if (bus_setup_intr(dev, sc->res[1], 586 INTR_TYPE_MISC | INTR_MPSAFE, NULL, rk_i2c_intr, sc, 587 &sc->intrhand)) { 588 bus_release_resources(dev, rk_i2c_spec, sc->res); 589 device_printf(dev, "cannot setup interrupt handler\n"); 590 return (ENXIO); 591 } 592 593 clk_set_assigned(dev, ofw_bus_get_node(dev)); 594 595 /* Activate the module clocks. */ 596 error = clk_get_by_ofw_name(dev, 0, "i2c", &sc->sclk); 597 if (error != 0) { 598 device_printf(dev, "cannot get i2c clock\n"); 599 goto fail; 600 } 601 error = clk_enable(sc->sclk); 602 if (error != 0) { 603 device_printf(dev, "cannot enable i2c clock\n"); 604 goto fail; 605 } 606 /* pclk clock is optional. */ 607 error = clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk); 608 if (error != 0 && error != ENOENT) { 609 device_printf(dev, "cannot get pclk clock\n"); 610 goto fail; 611 } 612 if (sc->pclk != NULL) { 613 error = clk_enable(sc->pclk); 614 if (error != 0) { 615 device_printf(dev, "cannot enable pclk clock\n"); 616 goto fail; 617 } 618 } 619 620 sc->iicbus = device_add_child(dev, "iicbus", -1); 621 if (sc->iicbus == NULL) { 622 device_printf(dev, "cannot add iicbus child device\n"); 623 error = ENXIO; 624 goto fail; 625 } 626 627 bus_generic_attach(dev); 628 629 return (0); 630 631fail: 632 if (rk_i2c_detach(dev) != 0) 633 device_printf(dev, "Failed to detach\n"); 634 return (error); 635} 636 637static int 638rk_i2c_detach(device_t dev) 639{ 640 struct rk_i2c_softc *sc; 641 int error; 642 643 sc = device_get_softc(dev); 644 645 if ((error = bus_generic_detach(dev)) != 0) 646 return (error); 647 648 if (sc->iicbus != NULL) 649 if ((error = device_delete_child(dev, sc->iicbus)) != 0) 650 return (error); 651 652 if (sc->sclk != NULL) 653 clk_release(sc->sclk); 654 if (sc->pclk != NULL) 655 clk_release(sc->pclk); 656 657 if (sc->intrhand != NULL) 658 bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand); 659 660 bus_release_resources(dev, rk_i2c_spec, sc->res); 661 662 mtx_destroy(&sc->mtx); 663 664 return (0); 665} 666 667static phandle_t 668rk_i2c_get_node(device_t bus, device_t dev) 669{ 670 671 return ofw_bus_get_node(bus); 672} 673 674static device_method_t rk_i2c_methods[] = { 675 DEVMETHOD(device_probe, rk_i2c_probe), 676 DEVMETHOD(device_attach, rk_i2c_attach), 677 DEVMETHOD(device_detach, rk_i2c_detach), 678 679 /* OFW methods */ 680 DEVMETHOD(ofw_bus_get_node, rk_i2c_get_node), 681 682 DEVMETHOD(iicbus_callback, iicbus_null_callback), 683 DEVMETHOD(iicbus_reset, rk_i2c_reset), 684 DEVMETHOD(iicbus_transfer, rk_i2c_transfer), 685 686 DEVMETHOD_END 687}; 688 689static driver_t rk_i2c_driver = { 690 "rk_i2c", 691 rk_i2c_methods, 692 sizeof(struct rk_i2c_softc), 693}; 694 695static devclass_t rk_i2c_devclass; 696 697EARLY_DRIVER_MODULE(rk_i2c, simplebus, rk_i2c_driver, rk_i2c_devclass, 0, 0, 698 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 699EARLY_DRIVER_MODULE(ofw_iicbus, rk_i2c, ofw_iicbus_driver, ofw_iicbus_devclass, 700 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 701MODULE_DEPEND(rk_i2c, iicbus, 1, 1, 1); 702MODULE_VERSION(rk_i2c, 1); 703