1/*- 2 * Copyright (C) 2007 3 * Oleksandr Tymoshenko <gonzo@freebsd.org>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWFV IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE FV DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 23 * IN ANY WAY OUT OF THE USE OF THIS SOFTWFV, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30#ifndef __IF_FVREG_H__ 31#define __IF_FVREG_H__ 32 33struct fv_desc { 34 uint32_t fv_stat; 35 uint32_t fv_devcs; 36 uint32_t fv_addr; 37 uint32_t fv_link; 38}; 39 40#define FV_DMASIZE(len) ((len) & ((1 << 11)-1)) 41#define FV_PKTSIZE(len) ((len & 0xffff0000) >> 16) 42 43#define FV_RX_RING_CNT 128 44#define FV_TX_RING_CNT 128 45#define FV_TX_RING_SIZE sizeof(struct fv_desc) * FV_TX_RING_CNT 46#define FV_RX_RING_SIZE sizeof(struct fv_desc) * FV_RX_RING_CNT 47#define FV_RING_ALIGN sizeof(struct fv_desc) 48#define FV_RX_ALIGN sizeof(uint32_t) 49#define FV_MAXFRAGS 8 50#define FV_TX_INTR_THRESH 8 51 52#define FV_TX_RING_ADDR(sc, i) \ 53 ((sc)->fv_rdata.fv_tx_ring_paddr + sizeof(struct fv_desc) * (i)) 54#define FV_RX_RING_ADDR(sc, i) \ 55 ((sc)->fv_rdata.fv_rx_ring_paddr + sizeof(struct fv_desc) * (i)) 56#define FV_INC(x,y) (x) = (((x) + 1) % y) 57 58struct fv_txdesc { 59 struct mbuf *tx_m; 60 bus_dmamap_t tx_dmamap; 61}; 62 63struct fv_rxdesc { 64 struct mbuf *rx_m; 65 bus_dmamap_t rx_dmamap; 66 struct fv_desc *desc; 67 /* Use this values on error instead of allocating new mbuf */ 68 uint32_t saved_ctl, saved_ca; 69}; 70 71struct fv_chain_data { 72 bus_dma_tag_t fv_parent_tag; 73 bus_dma_tag_t fv_tx_tag; 74 struct fv_txdesc fv_txdesc[FV_TX_RING_CNT]; 75 bus_dma_tag_t fv_rx_tag; 76 struct fv_rxdesc fv_rxdesc[FV_RX_RING_CNT]; 77 bus_dma_tag_t fv_tx_ring_tag; 78 bus_dma_tag_t fv_rx_ring_tag; 79 bus_dmamap_t fv_tx_ring_map; 80 bus_dmamap_t fv_rx_ring_map; 81 bus_dmamap_t fv_rx_sparemap; 82 int fv_tx_pkts; 83 int fv_tx_prod; 84 int fv_tx_cons; 85 int fv_tx_cnt; 86 int fv_rx_cons; 87 88 bus_dma_tag_t fv_sf_tag; 89 bus_dmamap_t fv_sf_buff_map; 90 uint32_t *fv_sf_buff; 91}; 92 93struct fv_ring_data { 94 struct fv_desc *fv_rx_ring; 95 struct fv_desc *fv_tx_ring; 96 bus_addr_t fv_rx_ring_paddr; 97 bus_addr_t fv_tx_ring_paddr; 98 bus_addr_t fv_sf_paddr; 99}; 100 101struct fv_softc { 102 struct ifnet *fv_ifp; /* interface info */ 103 bus_space_handle_t fv_bhandle; /* bus space handle */ 104 bus_space_tag_t fv_btag; /* bus space tag */ 105 device_t fv_dev; 106 uint8_t fv_eaddr[ETHER_ADDR_LEN]; 107 struct resource *fv_res; 108 int fv_rid; 109 struct resource *fv_irq; 110 void *fv_intrhand; 111 u_int32_t sc_inten; /* copy of CSR_INTEN */ 112 u_int32_t sc_rxint_mask; /* mask of Rx interrupts we want */ 113 u_int32_t sc_txint_mask; /* mask of Tx interrupts we want */ 114#ifdef MII 115 device_t fv_miibus; 116#else 117 struct ifmedia fv_ifmedia; 118#endif 119#ifdef FV_MDIO 120 device_t fv_miiproxy; 121#endif 122 int fv_if_flags; 123 bus_dma_tag_t fv_parent_tag; 124 bus_dma_tag_t fv_tag; 125 struct mtx fv_mtx; 126 phandle_t fv_ofw; 127 struct callout fv_stat_callout; 128 struct task fv_link_task; 129 struct fv_chain_data fv_cdata; 130 struct fv_ring_data fv_rdata; 131 int fv_link_status; 132 int fv_detach; 133}; 134 135#define FV_LOCK(_sc) mtx_lock(&(_sc)->fv_mtx) 136#define FV_UNLOCK(_sc) mtx_unlock(&(_sc)->fv_mtx) 137#define FV_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->fv_mtx, MA_OWNED) 138 139/* 140 * register space access macros 141 */ 142#define CSR_WRITE_4(sc, reg, val) \ 143 bus_space_write_4(sc->fv_btag, sc->fv_bhandle, reg, val) 144 145#define CSR_READ_4(sc, reg) \ 146 bus_space_read_4(sc->fv_btag, sc->fv_bhandle, reg) 147 148 149/* $NetBSD: aereg.h,v 1.2 2008/04/28 20:23:28 martin Exp $ */ 150 151/*- 152 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 153 * All rights reserved. 154 * 155 * This code is derived from software contributed to The NetBSD Foundation 156 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 157 * NASA Ames Research Center. 158 * 159 * Redistribution and use in source and binary forms, with or without 160 * modification, are permitted provided that the following conditions 161 * are met: 162 * 1. Redistributions of source code must retain the above copyright 163 * notice, this list of conditions and the following disclaimer. 164 * 2. Redistributions in binary form must reproduce the above copyright 165 * notice, this list of conditions and the following disclaimer in the 166 * documentation and/or other materials provided with the distribution. 167 * 168 * THIS SOFTWFV IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 169 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 170 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 171 * PURPOSE FV DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 172 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 173 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 174 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 175 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 176 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 177 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWFV, EVEN IF ADVISED OF THE 178 * POSSIBILITY OF SUCH DAMAGE. 179 */ 180 181/* 182 * Descriptor Status bits common to transmit and receive. 183 */ 184#define ADSTAT_OWN 0x80000000 /* Tulip owns descriptor */ 185#define ADSTAT_ES 0x00008000 /* Error Summary */ 186 187/* 188 * Descriptor Status bits for Receive Descriptor. 189 */ 190#define ADSTAT_Rx_FF 0x40000000 /* Filtering Fail */ 191#define ADSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */ 192#define ADSTAT_Rx_DE 0x00004000 /* Descriptor Error */ 193#define ADSTAT_Rx_LE 0x00001000 /* Length Error */ 194#define ADSTAT_Rx_RF 0x00000800 /* Runt Frame */ 195#define ADSTAT_Rx_MF 0x00000400 /* Multicast Frame */ 196#define ADSTAT_Rx_FS 0x00000200 /* First Descriptor */ 197#define ADSTAT_Rx_LS 0x00000100 /* Last Descriptor */ 198#define ADSTAT_Rx_TL 0x00000080 /* Frame Too Long */ 199#define ADSTAT_Rx_CS 0x00000040 /* Collision Seen */ 200#define ADSTAT_Rx_RT 0x00000020 /* Frame Type */ 201#define ADSTAT_Rx_RW 0x00000010 /* Receive Watchdog */ 202#define ADSTAT_Rx_RE 0x00000008 /* Report on MII Error */ 203#define ADSTAT_Rx_DB 0x00000004 /* Dribbling Bit */ 204#define ADSTAT_Rx_CE 0x00000002 /* CRC Error */ 205#define ADSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */ 206 207#define ADSTAT_Rx_LENGTH(x) (((x) & ADSTAT_Rx_FL) >> 16) 208 209/* 210 * Descriptor Status bits for Transmit Descriptor. 211 */ 212#define ADSTAT_Tx_ES 0x00008000 /* Error Summary */ 213#define ADSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */ 214#define ADSTAT_Tx_LO 0x00000800 /* Loss of Carrier */ 215#define ADSTAT_Tx_NC 0x00000400 /* No Carrier */ 216#define ADSTAT_Tx_LC 0x00000200 /* Late Collision */ 217#define ADSTAT_Tx_EC 0x00000100 /* Excessive Collisions */ 218#define ADSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */ 219#define ADSTAT_Tx_CC 0x00000078 /* Collision Count */ 220#define ADSTAT_Tx_ED 0x00000004 /* Excessive Deferral */ 221#define ADSTAT_Tx_UF 0x00000002 /* Underflow Error */ 222#define ADSTAT_Tx_DE 0x00000001 /* Deferred */ 223 224#define ADSTAT_Tx_COLLISIONS(x) (((x) & ADSTAT_Tx_CC) >> 3) 225 226/* 227 * Descriptor Control bits common to transmit and receive. 228 */ 229#define ADCTL_SIZE1 0x000007ff /* Size of buffer 1 */ 230#define ADCTL_SIZE1_SHIFT 0 231 232#define ADCTL_SIZE2 0x003ff800 /* Size of buffer 2 */ 233#define ADCTL_SIZE2_SHIFT 11 234 235#define ADCTL_ER 0x02000000 /* End of Ring */ 236#define ADCTL_CH 0x01000000 /* Second Address Chained */ 237 238/* 239 * Descriptor Control bits for Transmit Descriptor. 240 */ 241#define ADCTL_Tx_IC 0x80000000 /* Interrupt on Completion */ 242#define ADCTL_Tx_LS 0x40000000 /* Last Segment */ 243#define ADCTL_Tx_FS 0x20000000 /* First Segment */ 244#define ADCTL_Tx_SETUP 0x08000000 /* Setup frame */ 245#define ADCTL_Tx_AC 0x04000000 /* Add CRC Disable */ 246#define ADCTL_Tx_DPD 0x00800000 /* Disabled Padding */ 247 248/* 249 * Control registers. 250 */ 251 252/* tese are registers only found on this part */ 253#ifdef NOTUSE 254#define CSR_MACCTL 0x0000 /* mac control */ 255#define CSR_MACHI 0x0004 256#define CSR_MACLO 0x0008 257#define CSR_HTHI 0x000C /* multicast table high */ 258#define CSR_HTLO 0x0010 /* multicast table low */ 259#define CSR_MIIADDR 0x0014 /* mii address */ 260#define CSR_MIIDATA 0x0018 /* mii data */ 261#define CSR_FLOWC 0x001C /* flow control */ 262#define CSR_VL1 0x0020 /* vlan 1 tag */ 263#endif 264 265/* these are more or less normal Tulip registers */ 266#define CSR_BUSMODE (0x08*0) /* bus mode */ 267#define CSR_TXPOLL (0x08*1) /* tx poll demand */ 268#define CSR_RXPOLL (0x08*2) /* rx poll demand */ 269#define CSR_RXLIST (0x08*3) /* rx base descriptor address */ 270#define CSR_TXLIST (0x08*4) /* tx base descriptor address */ 271#define CSR_STATUS (0x08*5) /* (interrupt) status */ 272#define CSR_OPMODE (0x08*6) /* operation mode */ 273#define CSR_INTEN (0x08*7) /* interrupt enable */ 274#define CSR_MISSED (0x08*8) /* missed frame counter */ 275 276#ifdef NOTUSE 277#define CSR_HTBA 0x1050 /* host tx buffer address (ro) */ 278#define CSR_HRBA 0x1054 /* host rx buffer address (ro) */ 279#endif 280 281#define CSR_MIIMNG (0x08*9) /* MII Management Register */ 282#define CSR_FULLDUP (0x08*11) /* Full Duplex Register */ 283 284/* 21143 like register */ 285#define FULLDUP_CS 0x80000000 /* Cycle Size */ 286#define FULLDUP_TT_SHIFT 27 /* Transmit Timer */ 287#define FULLDUP_NTP_SHIFT 24 /* Number of Transmit Packets */ 288#define FULLDUP_RT_SHIFT 20 /* Receive Timer */ 289#define FULLDUP_NRP_SHIFT 17 /* Number of Receive Packets */ 290#define FULLDUP_CON_MODE 0x00010000 /* Continuous Mode */ 291#define FULLDUP_TIM_SHIFT 0 /* Timer Value */ 292 293/* CSR_MACCTL - Mac Control */ 294#define MACCTL_RE 0x00000004 /* rx enable */ 295#define MACCTL_TE 0x00000008 /* tx enable */ 296#define MACCTL_DC 0x00000020 /* deferral check */ 297#define MACCTL_PSTR 0x00000100 /* automatic pad strip */ 298#define MACCTL_DTRY 0x00000400 /* disable retry */ 299#define MACCTL_DBF 0x00000800 /* disable broadcast frames */ 300#define MACCTL_LCC 0x00001000 /* late collision control */ 301#define MACCTL_HASH 0x00002000 /* hash filtering enable */ 302#define MACCTL_HO 0x00008000 /* disable perfect filtering */ 303#define MACCTL_PB 0x00010000 /* pass bad frames */ 304#define MACCTL_IF 0x00020000 /* inverse filtering */ 305#define MACCTL_PR 0x00040000 /* promiscuous mode */ 306#define MACCTL_PM 0x00080000 /* pass all multicast */ 307#define MACCTL_FDX 0x00100000 /* full duplex mode */ 308#define MACCTL_LOOP 0x00600000 /* loopback mask */ 309#define MACCTL_LOOP_INT 0x00200000 /* internal loopback */ 310#define MACCTL_LOOP_EXT 0x00400000 /* external loopback */ 311#define MACCTL_LOOP_NONE 0x00000000 312#define MACCTL_DRO 0x00800000 /* disable receive own */ 313#define MACCTL_PS 0x08000000 /* port select, 0 = mii */ 314#define MACCTL_HBD 0x10000000 /* heartbeat disable */ 315#define MACCTL_BLE 0x40000000 /* mac big endian */ 316#define MACCTL_RA 0x80000000 /* receive all packets */ 317 318/* CSR_MIIADDR - MII Addess */ 319#define MIIADDR_BUSY 0x00000001 /* mii busy */ 320#define MIIADDR_WRITE 0x00000002 /* mii write */ 321#define MIIADDR_REG_MASK 0x000007C0 /* mii register */ 322#define MIIADDR_REG_SHIFT 6 323#define MIIADDR_PHY_MASK 0x0000F800 /* mii phy */ 324#define MIIADDR_PHY_SHIFT 11 325 326#define MIIADDR_GETREG(x) (((x) & MIIADDR_REG) >> 6) 327#define MIIADDR_PUTREG(x) (((x) << 6) & MIIADR_REG) 328#define MIIADDR_GETPHY(x) (((x) & MIIADDR_PHY) >> 11) 329#define MIIADDR_PUTPHY(x) (((x) << 6) & MIIADR_PHY) 330 331/* CSR_FLOWC - Flow Control */ 332#define FLOWC_FCB 0x00000001 /* flow control busy */ 333#define FLOWC_FCE 0x00000002 /* flow control enable */ 334#define FLOWC_PCF 0x00000004 /* pass control frames */ 335#define FLOWC_PT 0xffff0000 /* pause time */ 336 337/* CSR_BUSMODE - Bus Mode */ 338#define BUSMODE_SWR 0x00000001 /* software reset */ 339#define BUSMODE_BAR 0x00000002 /* bus arbitration */ 340#define BUSMODE_DSL 0x0000007c /* descriptor skip length */ 341#define BUSMODE_BLE 0x00000080 /* data buf endian */ 342 /* programmable burst length */ 343#define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */ 344#define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */ 345#define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */ 346#define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */ 347#define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */ 348#define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */ 349#define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */ 350#define BUSMODE_TAP_SHIFT 17 /* Transmit Automatic Polling */ 351#define BUSMODE_DBO 0x00100000 /* descriptor endian */ 352#define BUSMODE_ALIGN_16B 0x01000000 /* force oddhw rx buf align */ 353 354/* CSR_TXPOLL - Transmit Poll Demand */ 355#define TXPOLL_TPD 0x00000001 /* transmit poll demand */ 356 357 358/* CSR_RXPOLL - Receive Poll Demand */ 359#define RXPOLL_RPD 0x00000001 /* receive poll demand */ 360 361/* CSR_STATUS - Status */ 362#define STATUS_TI 0x00000001 /* transmit interrupt */ 363#define STATUS_TPS 0x00000002 /* transmit process stopped */ 364#define STATUS_TU 0x00000004 /* transmit buffer unavail */ 365#define STATUS_TJT 0x00000008 /* transmit jabber timeout */ 366#define STATUS_UNF 0x00000020 /* transmit underflow */ 367#define STATUS_RI 0x00000040 /* receive interrupt */ 368#define STATUS_RU 0x00000080 /* receive buffer unavail */ 369#define STATUS_RPS 0x00000100 /* receive process stopped */ 370#define STATUS_ETI 0x00000400 /* early transmit interrupt */ 371#define STATUS_SE 0x00002000 /* system error */ 372#define STATUS_ER 0x00004000 /* early receive (21041) */ 373#define STATUS_AIS 0x00008000 /* abnormal intr summary */ 374#define STATUS_NIS 0x00010000 /* normal interrupt summary */ 375#define STATUS_RS 0x000e0000 /* receive process state */ 376#define STATUS_RS_STOPPED 0x00000000 /* Stopped */ 377#define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive 378 descriptor */ 379#define STATUS_RS_CHECK 0x00040000 /* Running - check for end 380 of receive */ 381#define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */ 382#define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */ 383#define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive 384 descriptor */ 385#define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current 386 frame from FIFO */ 387#define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current 388 frame from FIFO into 389 buffer */ 390#define STATUS_TS 0x00700000 /* transmit process state */ 391#define STATUS_TS_STOPPED 0x00000000 /* Stopped */ 392#define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit 393 descriptor */ 394#define STATUS_TS_WAIT 0x00200000 /* Running - wait for end 395 of transmission */ 396#define STATUS_TS_READING 0x00300000 /* Running - read buffer from 397 memory and queue into 398 FIFO */ 399#define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */ 400#define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit 401 descriptor */ 402#define STATUS_TX_ABORT 0x00800000 /* Transmit bus abort */ 403#define STATUS_RX_ABORT 0x01000000 /* Transmit bus abort */ 404 405/* CSR_OPMODE - Operation Mode */ 406#define OPMODE_SR 0x00000002 /* start receive */ 407#define OPMODE_OSF 0x00000004 /* operate on second frame */ 408#define OPMODE_PR 0x00000040 /* promiscuous mode */ 409#define OPMODE_PM 0x00000080 /* pass all multicast */ 410#define OPMODE_FDX 0x00000200 /* full duplex mode */ 411#define OPMODE_ST 0x00002000 /* start transmitter */ 412#define OPMODE_TR 0x0000c000 /* threshold control */ 413#define OPMODE_TR_32 0x00000000 /* 32 words */ 414#define OPMODE_TR_64 0x00004000 /* 64 words */ 415#define OPMODE_TR_128 0x00008000 /* 128 words */ 416#define OPMODE_TR_256 0x0000c000 /* 256 words */ 417#define OPMODE_SF 0x00200000 /* store and forward mode */ 418#define OPMODE_SPEED 0x80000000 /* speed 100M:1 10M:0 */ 419 420/* CSR_INTEN - Interrupt Enable */ 421 /* See bits for CSR_STATUS -- Status */ 422 423 424/* CSR_MISSED - Missed Frames */ 425#define MISSED_MFC 0xffff0000 /* missed packet count */ 426#define MISSED_FOC 0x0000ffff /* fifo overflow counter */ 427 428#define MISSED_GETMFC(x) ((x) & MISSED_MFC) 429#define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 16) 430 431/* setup frame code refer dc code */ 432 433#define FV_SFRAME_LEN 192 434#define FV_MIN_FRAMELEN 60 435 436/* 437 * MII Definitions for the 21041 and 21140/21140A/21142 438 * copy from if_devar.h 439 */ 440#define MII_PREAMBLE (~0) 441#define MII_TEST 0xAAAAAAAA 442#define MII_RDCMD 0x06 443#define MII_WRCMD 0x05 444#define MII_DIN 0x00080000 445#define MII_RD 0x00040000 446#define MII_WR 0x00000000 447#define MII_DOUT 0x00020000 448#define MII_CLK 0x00010000 449#define MII_CLKON MII_CLK 450#define MII_CLKOFF MII_CLK 451 452#endif /* __IF_FVREG_H__ */ 453