1/*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30 31/* 32 * UART driver for Tegra SoCs. 33 */ 34#include "opt_platform.h" 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/conf.h> 40#include <sys/kernel.h> 41#include <sys/module.h> 42#include <sys/sysctl.h> 43#include <machine/bus.h> 44 45#include <dev/extres/clk/clk.h> 46#include <dev/extres/hwreset/hwreset.h> 47#include <dev/ofw/ofw_bus.h> 48#include <dev/ofw/ofw_bus_subr.h> 49#include <dev/uart/uart.h> 50#include <dev/uart/uart_cpu.h> 51#include <dev/uart/uart_cpu_fdt.h> 52#include <dev/uart/uart_bus.h> 53#include <dev/uart/uart_dev_ns8250.h> 54#include <dev/ic/ns16550.h> 55 56#include "uart_if.h" 57 58/* 59 * High-level UART interface. 60 */ 61struct tegra_softc { 62 struct ns8250_softc ns8250_base; 63 clk_t clk; 64 hwreset_t reset; 65}; 66 67/* 68 * UART class interface. 69 */ 70static int 71tegra_uart_attach(struct uart_softc *sc) 72{ 73 int rv; 74 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 75 struct uart_bas *bas = &sc->sc_bas; 76 77 rv = ns8250_bus_attach(sc); 78 if (rv != 0) 79 return (rv); 80 81 ns8250->ier_rxbits = 0x1d; 82 ns8250->ier_mask = 0xc0; 83 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 84 ns8250->ier |= ns8250->ier_rxbits; 85 uart_setreg(bas, REG_IER, ns8250->ier); 86 uart_barrier(bas); 87 return (0); 88} 89 90static void 91tegra_uart_grab(struct uart_softc *sc) 92{ 93 struct uart_bas *bas = &sc->sc_bas; 94 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 95 u_char ier; 96 97 /* 98 * turn off all interrupts to enter polling mode. Leave the 99 * saved mask alone. We'll restore whatever it was in ungrab. 100 * All pending interrupt signals are reset when IER is set to 0. 101 */ 102 uart_lock(sc->sc_hwmtx); 103 ier = uart_getreg(bas, REG_IER); 104 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 105 106 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0) 107 ; 108 109 uart_setreg(bas, REG_FCR, 0); 110 uart_barrier(bas); 111 uart_unlock(sc->sc_hwmtx); 112} 113 114static void 115tegra_uart_ungrab(struct uart_softc *sc) 116{ 117 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 118 struct uart_bas *bas = &sc->sc_bas; 119 120 /* 121 * Restore previous interrupt mask 122 */ 123 uart_lock(sc->sc_hwmtx); 124 uart_setreg(bas, REG_FCR, ns8250->fcr); 125 uart_setreg(bas, REG_IER, ns8250->ier); 126 uart_barrier(bas); 127 uart_unlock(sc->sc_hwmtx); 128} 129 130static kobj_method_t tegra_methods[] = { 131 KOBJMETHOD(uart_probe, ns8250_bus_probe), 132 KOBJMETHOD(uart_attach, tegra_uart_attach), 133 KOBJMETHOD(uart_detach, ns8250_bus_detach), 134 KOBJMETHOD(uart_flush, ns8250_bus_flush), 135 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 136 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 137 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 138 KOBJMETHOD(uart_param, ns8250_bus_param), 139 KOBJMETHOD(uart_receive, ns8250_bus_receive), 140 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 141 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 142 KOBJMETHOD(uart_grab, tegra_uart_grab), 143 KOBJMETHOD(uart_ungrab, tegra_uart_ungrab), 144 KOBJMETHOD_END 145}; 146 147static struct uart_class tegra_uart_class = { 148 "tegra class", 149 tegra_methods, 150 sizeof(struct tegra_softc), 151 .uc_ops = &uart_ns8250_ops, 152 .uc_range = 8, 153 .uc_rclk = 0, 154}; 155 156/* Compatible devices. */ 157static struct ofw_compat_data compat_data[] = { 158 {"nvidia,tegra124-uart", (uintptr_t)&tegra_uart_class}, 159 {NULL, (uintptr_t)NULL}, 160}; 161 162UART_FDT_CLASS(compat_data); 163 164/* 165 * UART Driver interface. 166 */ 167static int 168uart_fdt_get_shift1(phandle_t node) 169{ 170 pcell_t shift; 171 172 if ((OF_getencprop(node, "reg-shift", &shift, sizeof(shift))) <= 0) 173 shift = 2; 174 return ((int)shift); 175} 176 177static int 178tegra_uart_probe(device_t dev) 179{ 180 struct tegra_softc *sc; 181 phandle_t node; 182 uint64_t freq; 183 int shift; 184 int rv; 185 const struct ofw_compat_data *cd; 186 187 sc = device_get_softc(dev); 188 if (!ofw_bus_status_okay(dev)) 189 return (ENXIO); 190 cd = ofw_bus_search_compatible(dev, compat_data); 191 if (cd->ocd_data == 0) 192 return (ENXIO); 193 sc->ns8250_base.base.sc_class = (struct uart_class *)cd->ocd_data; 194 195 rv = hwreset_get_by_ofw_name(dev, 0, "serial", &sc->reset); 196 if (rv != 0) { 197 device_printf(dev, "Cannot get 'serial' reset\n"); 198 return (ENXIO); 199 } 200 rv = hwreset_deassert(sc->reset); 201 if (rv != 0) { 202 device_printf(dev, "Cannot unreset 'serial' reset\n"); 203 return (ENXIO); 204 } 205 206 node = ofw_bus_get_node(dev); 207 shift = uart_fdt_get_shift1(node); 208 rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk); 209 if (rv != 0) { 210 device_printf(dev, "Cannot get UART clock: %d\n", rv); 211 return (ENXIO); 212 } 213 rv = clk_enable(sc->clk); 214 if (rv != 0) { 215 device_printf(dev, "Cannot enable UART clock: %d\n", rv); 216 return (ENXIO); 217 } 218 rv = clk_get_freq(sc->clk, &freq); 219 if (rv != 0) { 220 device_printf(dev, "Cannot enable UART clock: %d\n", rv); 221 return (ENXIO); 222 } 223 return (uart_bus_probe(dev, shift, 0, (int)freq, 0, 0, 0)); 224} 225 226static int 227tegra_uart_detach(device_t dev) 228{ 229 struct tegra_softc *sc; 230 231 sc = device_get_softc(dev); 232 if (sc->clk != NULL) { 233 clk_release(sc->clk); 234 } 235 236 return (uart_bus_detach(dev)); 237} 238 239static device_method_t tegra_uart_bus_methods[] = { 240 /* Device interface */ 241 DEVMETHOD(device_probe, tegra_uart_probe), 242 DEVMETHOD(device_attach, uart_bus_attach), 243 DEVMETHOD(device_detach, tegra_uart_detach), 244 { 0, 0 } 245}; 246 247static driver_t tegra_uart_driver = { 248 uart_driver_name, 249 tegra_uart_bus_methods, 250 sizeof(struct tegra_softc), 251}; 252 253DRIVER_MODULE(tegra_uart, simplebus, tegra_uart_driver, uart_devclass, 254 0, 0); 255