1/*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30/* 31 * Tegra GPIO driver. 32 */ 33#include "opt_platform.h" 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#include <sys/gpio.h> 38#include <sys/kernel.h> 39#include <sys/proc.h> 40#include <sys/rman.h> 41#include <sys/lock.h> 42#include <sys/module.h> 43#include <sys/mutex.h> 44 45#include <machine/bus.h> 46#include <machine/intr.h> 47#include <machine/resource.h> 48 49#include <dev/gpio/gpiobusvar.h> 50#include <dev/ofw/openfirm.h> 51#include <dev/ofw/ofw_bus.h> 52#include <dev/ofw/ofw_bus_subr.h> 53 54#include "pic_if.h" 55 56#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx) 57#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 58#define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->mtx, \ 59 device_get_nameunit(_sc->dev), "tegra_gpio", MTX_DEF) 60#define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx); 61#define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED); 62#define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED); 63 64#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) 65#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) 66 67#define GPIO_BANK_OFFS 0x100 /* Bank offset */ 68#define GPIO_NUM_BANKS 8 /* Total number per bank */ 69#define GPIO_REGS_IN_BANK 4 /* Total registers in bank */ 70#define GPIO_PINS_IN_REG 8 /* Total pin in register */ 71 72#define GPIO_BANKNUM(n) ((n) / (GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG)) 73#define GPIO_PORTNUM(n) (((n) / GPIO_PINS_IN_REG) % GPIO_REGS_IN_BANK) 74#define GPIO_BIT(n) ((n) % GPIO_PINS_IN_REG) 75 76#define GPIO_REGNUM(n) (GPIO_BANKNUM(n) * GPIO_BANK_OFFS + \ 77 GPIO_PORTNUM(n) * 4) 78 79#define NGPIO ((GPIO_NUM_BANKS * GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG) - 8) 80 81/* Register offsets */ 82#define GPIO_CNF 0x00 83#define GPIO_OE 0x10 84#define GPIO_OUT 0x20 85#define GPIO_IN 0x30 86#define GPIO_INT_STA 0x40 87#define GPIO_INT_ENB 0x50 88#define GPIO_INT_LVL 0x60 89#define GPIO_INT_LVL_DELTA (1 << 16) 90#define GPIO_INT_LVL_EDGE (1 << 8) 91#define GPIO_INT_LVL_HIGH (1 << 0) 92#define GPIO_INT_LVL_MASK (GPIO_INT_LVL_DELTA | \ 93 GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH) 94#define GPIO_INT_CLR 0x70 95#define GPIO_MSK_CNF 0x80 96#define GPIO_MSK_OE 0x90 97#define GPIO_MSK_OUT 0xA0 98#define GPIO_MSK_INT_STA 0xC0 99#define GPIO_MSK_INT_ENB 0xD0 100#define GPIO_MSK_INT_LVL 0xE0 101 102char *tegra_gpio_port_names[] = { 103 "A", "B", "C", "D", /* Bank 0 */ 104 "E", "F", "G", "H", /* Bank 1 */ 105 "I", "J", "K", "L", /* Bank 2 */ 106 "M", "N", "O", "P", /* Bank 3 */ 107 "Q", "R", "S", "T", /* Bank 4 */ 108 "U", "V", "W", "X", /* Bank 5 */ 109 "Y", "Z", "AA", "BB", /* Bank 6 */ 110 "CC", "DD", "EE" /* Bank 7 */ 111}; 112 113struct tegra_gpio_irqsrc { 114 struct intr_irqsrc isrc; 115 u_int irq; 116 uint32_t cfgreg; 117}; 118 119struct tegra_gpio_softc; 120struct tegra_gpio_irq_cookie { 121 struct tegra_gpio_softc *sc; 122 int bank_num; 123}; 124 125struct tegra_gpio_softc { 126 device_t dev; 127 device_t busdev; 128 struct mtx mtx; 129 struct resource *mem_res; 130 struct resource *irq_res[GPIO_NUM_BANKS]; 131 void *irq_ih[GPIO_NUM_BANKS]; 132 struct tegra_gpio_irq_cookie irq_cookies[GPIO_NUM_BANKS]; 133 int gpio_npins; 134 struct gpio_pin gpio_pins[NGPIO]; 135 struct tegra_gpio_irqsrc *isrcs; 136}; 137 138static struct ofw_compat_data compat_data[] = { 139 {"nvidia,tegra124-gpio", 1}, 140 {NULL, 0} 141}; 142 143/* -------------------------------------------------------------------------- 144 * 145 * GPIO 146 * 147 */ 148static inline void 149gpio_write_masked(struct tegra_gpio_softc *sc, bus_size_t reg, 150 struct gpio_pin *pin, uint32_t val) 151{ 152 uint32_t tmp; 153 int bit; 154 155 bit = GPIO_BIT(pin->gp_pin); 156 tmp = 0x100 << bit; /* mask */ 157 tmp |= (val & 1) << bit; /* value */ 158 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin), tmp); 159} 160 161static inline uint32_t 162gpio_read(struct tegra_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin) 163{ 164 int bit; 165 uint32_t val; 166 167 bit = GPIO_BIT(pin->gp_pin); 168 val = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin)); 169 return (val >> bit) & 1; 170} 171 172static void 173tegra_gpio_pin_configure(struct tegra_gpio_softc *sc, struct gpio_pin *pin, 174 unsigned int flags) 175{ 176 177 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0) 178 return; 179 180 /* Manage input/output */ 181 pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 182 if (flags & GPIO_PIN_OUTPUT) { 183 pin->gp_flags |= GPIO_PIN_OUTPUT; 184 gpio_write_masked(sc, GPIO_MSK_OE, pin, 1); 185 } else { 186 pin->gp_flags |= GPIO_PIN_INPUT; 187 gpio_write_masked(sc, GPIO_MSK_OE, pin, 0); 188 } 189} 190 191static device_t 192tegra_gpio_get_bus(device_t dev) 193{ 194 struct tegra_gpio_softc *sc; 195 196 sc = device_get_softc(dev); 197 return (sc->busdev); 198} 199 200static int 201tegra_gpio_pin_max(device_t dev, int *maxpin) 202{ 203 204 *maxpin = NGPIO - 1; 205 return (0); 206} 207 208static int 209tegra_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 210{ 211 struct tegra_gpio_softc *sc; 212 213 sc = device_get_softc(dev); 214 if (pin >= sc->gpio_npins) 215 return (EINVAL); 216 217 GPIO_LOCK(sc); 218 *caps = sc->gpio_pins[pin].gp_caps; 219 GPIO_UNLOCK(sc); 220 221 return (0); 222} 223 224static int 225tegra_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 226{ 227 struct tegra_gpio_softc *sc; 228 int cnf; 229 230 sc = device_get_softc(dev); 231 if (pin >= sc->gpio_npins) 232 return (EINVAL); 233 234 GPIO_LOCK(sc); 235 cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]); 236 if (cnf == 0) { 237 GPIO_UNLOCK(sc); 238 return (ENXIO); 239 } 240 *flags = sc->gpio_pins[pin].gp_flags; 241 GPIO_UNLOCK(sc); 242 243 return (0); 244} 245 246static int 247tegra_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 248{ 249 struct tegra_gpio_softc *sc; 250 251 sc = device_get_softc(dev); 252 if (pin >= sc->gpio_npins) 253 return (EINVAL); 254 255 GPIO_LOCK(sc); 256 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME); 257 GPIO_UNLOCK(sc); 258 259 return (0); 260} 261 262static int 263tegra_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 264{ 265 struct tegra_gpio_softc *sc; 266 int cnf; 267 268 sc = device_get_softc(dev); 269 if (pin >= sc->gpio_npins) 270 return (EINVAL); 271 272 GPIO_LOCK(sc); 273 cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]); 274 if (cnf == 0) { 275 /* XXX - allow this for while .... 276 GPIO_UNLOCK(sc); 277 return (ENXIO); 278 */ 279 gpio_write_masked(sc, GPIO_MSK_CNF, &sc->gpio_pins[pin], 1); 280 } 281 tegra_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags); 282 GPIO_UNLOCK(sc); 283 284 return (0); 285} 286 287static int 288tegra_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 289{ 290 struct tegra_gpio_softc *sc; 291 292 sc = device_get_softc(dev); 293 if (pin >= sc->gpio_npins) 294 return (EINVAL); 295 GPIO_LOCK(sc); 296 gpio_write_masked(sc, GPIO_MSK_OUT, &sc->gpio_pins[pin], value); 297 GPIO_UNLOCK(sc); 298 299 return (0); 300} 301 302static int 303tegra_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 304{ 305 struct tegra_gpio_softc *sc; 306 307 sc = device_get_softc(dev); 308 if (pin >= sc->gpio_npins) 309 return (EINVAL); 310 311 GPIO_LOCK(sc); 312 *val = gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]); 313 GPIO_UNLOCK(sc); 314 315 return (0); 316} 317 318static int 319tegra_gpio_pin_toggle(device_t dev, uint32_t pin) 320{ 321 struct tegra_gpio_softc *sc; 322 323 sc = device_get_softc(dev); 324 if (pin >= sc->gpio_npins) 325 return (EINVAL); 326 327 GPIO_LOCK(sc); 328 gpio_write_masked(sc, GPIO_MSK_OE, &sc->gpio_pins[pin], 329 gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]) ^ 1); 330 GPIO_UNLOCK(sc); 331 332 return (0); 333} 334 335/* -------------------------------------------------------------------------- 336 * 337 * Interrupts 338 * 339 */ 340static inline void 341intr_write_masked(struct tegra_gpio_softc *sc, bus_addr_t reg, 342 struct tegra_gpio_irqsrc *tgi, uint32_t val) 343{ 344 uint32_t tmp; 345 int bit; 346 347 bit = GPIO_BIT(tgi->irq); 348 tmp = 0x100 << bit; /* mask */ 349 tmp |= (val & 1) << bit; /* value */ 350 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp); 351} 352 353static inline void 354intr_write_modify(struct tegra_gpio_softc *sc, bus_addr_t reg, 355 struct tegra_gpio_irqsrc *tgi, uint32_t val, uint32_t mask) 356{ 357 uint32_t tmp; 358 int bit; 359 360 bit = GPIO_BIT(tgi->irq); 361 GPIO_LOCK(sc); 362 tmp = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq)); 363 tmp &= ~(mask << bit); 364 tmp |= val << bit; 365 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp); 366 GPIO_UNLOCK(sc); 367} 368 369static inline void 370tegra_gpio_isrc_mask(struct tegra_gpio_softc *sc, 371 struct tegra_gpio_irqsrc *tgi, uint32_t val) 372{ 373 374 intr_write_masked(sc, GPIO_MSK_INT_ENB, tgi, val); 375} 376 377static inline void 378tegra_gpio_isrc_eoi(struct tegra_gpio_softc *sc, 379 struct tegra_gpio_irqsrc *tgi) 380{ 381 382 intr_write_masked(sc, GPIO_INT_CLR, tgi, 1); 383} 384 385static inline bool 386tegra_gpio_isrc_is_level(struct tegra_gpio_irqsrc *tgi) 387{ 388 389 return (tgi->cfgreg & GPIO_INT_LVL_EDGE); 390} 391 392static int 393tegra_gpio_intr(void *arg) 394{ 395 u_int irq, i, j, val, basepin; 396 struct tegra_gpio_softc *sc; 397 struct trapframe *tf; 398 struct tegra_gpio_irqsrc *tgi; 399 struct tegra_gpio_irq_cookie *cookie; 400 401 cookie = (struct tegra_gpio_irq_cookie *)arg; 402 sc = cookie->sc; 403 tf = curthread->td_intr_frame; 404 405 for (i = 0; i < GPIO_REGS_IN_BANK; i++) { 406 basepin = cookie->bank_num * GPIO_REGS_IN_BANK * 407 GPIO_PINS_IN_REG + i * GPIO_PINS_IN_REG; 408 409 val = bus_read_4(sc->mem_res, GPIO_INT_STA + 410 GPIO_REGNUM(basepin)); 411 val &= bus_read_4(sc->mem_res, GPIO_INT_ENB + 412 GPIO_REGNUM(basepin)); 413 /* Interrupt handling */ 414 for (j = 0; j < GPIO_PINS_IN_REG; j++) { 415 if ((val & (1 << j)) == 0) 416 continue; 417 irq = basepin + j; 418 tgi = &sc->isrcs[irq]; 419 if (!tegra_gpio_isrc_is_level(tgi)) 420 tegra_gpio_isrc_eoi(sc, tgi); 421 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) { 422 tegra_gpio_isrc_mask(sc, tgi, 0); 423 if (tegra_gpio_isrc_is_level(tgi)) 424 tegra_gpio_isrc_eoi(sc, tgi); 425 device_printf(sc->dev, 426 "Stray irq %u disabled\n", irq); 427 } 428 429 } 430 } 431 432 return (FILTER_HANDLED); 433} 434 435static int 436tegra_gpio_pic_attach(struct tegra_gpio_softc *sc) 437{ 438 int error; 439 uint32_t irq; 440 const char *name; 441 442 sc->isrcs = malloc(sizeof(*sc->isrcs) * sc->gpio_npins, M_DEVBUF, 443 M_WAITOK | M_ZERO); 444 445 name = device_get_nameunit(sc->dev); 446 for (irq = 0; irq < sc->gpio_npins; irq++) { 447 sc->isrcs[irq].irq = irq; 448 sc->isrcs[irq].cfgreg = 0; 449 error = intr_isrc_register(&sc->isrcs[irq].isrc, 450 sc->dev, 0, "%s,%u", name, irq); 451 if (error != 0) 452 return (error); /* XXX deregister ISRCs */ 453 } 454 if (intr_pic_register(sc->dev, 455 OF_xref_from_node(ofw_bus_get_node(sc->dev))) == NULL) 456 return (ENXIO); 457 458 return (0); 459} 460 461static int 462tegra_gpio_pic_detach(struct tegra_gpio_softc *sc) 463{ 464 465 /* 466 * There has not been established any procedure yet 467 * how to detach PIC from living system correctly. 468 */ 469 device_printf(sc->dev, "%s: not implemented yet\n", __func__); 470 return (EBUSY); 471} 472 473 474static void 475tegra_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 476{ 477 struct tegra_gpio_softc *sc; 478 struct tegra_gpio_irqsrc *tgi; 479 480 sc = device_get_softc(dev); 481 tgi = (struct tegra_gpio_irqsrc *)isrc; 482 tegra_gpio_isrc_mask(sc, tgi, 0); 483} 484 485static void 486tegra_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 487{ 488 struct tegra_gpio_softc *sc; 489 struct tegra_gpio_irqsrc *tgi; 490 491 sc = device_get_softc(dev); 492 tgi = (struct tegra_gpio_irqsrc *)isrc; 493 tegra_gpio_isrc_mask(sc, tgi, 1); 494} 495 496static int 497tegra_gpio_pic_map_fdt(struct tegra_gpio_softc *sc, u_int ncells, 498 pcell_t *cells, u_int *irqp, uint32_t *regp) 499{ 500 uint32_t reg; 501 502 /* 503 * The first cell is the interrupt number. 504 * The second cell is used to specify flags: 505 * bits[3:0] trigger type and level flags: 506 * 1 = low-to-high edge triggered. 507 * 2 = high-to-low edge triggered. 508 * 4 = active high level-sensitive. 509 * 8 = active low level-sensitive. 510 */ 511 if (ncells != 2 || cells[0] >= sc->gpio_npins) 512 return (EINVAL); 513 514 /* 515 * All interrupt types could be set for an interrupt at one moment. 516 * At least, the combination of 'low-to-high' and 'high-to-low' edge 517 * triggered interrupt types can make a sense. 518 */ 519 if (cells[1] == 1) 520 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH; 521 else if (cells[1] == 2) 522 reg = GPIO_INT_LVL_EDGE; 523 else if (cells[1] == 3) 524 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA; 525 else if (cells[1] == 4) 526 reg = GPIO_INT_LVL_HIGH; 527 else if (cells[1] == 8) 528 reg = 0; 529 else 530 return (EINVAL); 531 532 *irqp = cells[0]; 533 if (regp != NULL) 534 *regp = reg; 535 return (0); 536} 537 538 539static int 540tegra_gpio_pic_map_gpio(struct tegra_gpio_softc *sc, u_int gpio_pin_num, 541 u_int gpio_pin_flags, u_int intr_mode, u_int *irqp, uint32_t *regp) 542{ 543 544 uint32_t reg; 545 546 if (gpio_pin_num >= sc->gpio_npins) 547 return (EINVAL); 548 switch (intr_mode) { 549 case GPIO_INTR_CONFORM: 550 case GPIO_INTR_LEVEL_LOW: 551 reg = 0; 552 break; 553 case GPIO_INTR_LEVEL_HIGH: 554 reg = GPIO_INT_LVL_HIGH; 555 break; 556 case GPIO_INTR_EDGE_RISING: 557 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH; 558 break; 559 case GPIO_INTR_EDGE_FALLING: 560 reg = GPIO_INT_LVL_EDGE; 561 break; 562 case GPIO_INTR_EDGE_BOTH: 563 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA; 564 break; 565 default: 566 return (EINVAL); 567 } 568 *irqp = gpio_pin_num; 569 if (regp != NULL) 570 *regp = reg; 571 return (0); 572} 573 574static int 575tegra_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 576 struct intr_irqsrc **isrcp) 577{ 578 int rv; 579 u_int irq; 580 struct tegra_gpio_softc *sc; 581 582 sc = device_get_softc(dev); 583 584 if (data->type == INTR_MAP_DATA_FDT) { 585 struct intr_map_data_fdt *daf; 586 587 daf = (struct intr_map_data_fdt *)data; 588 rv = tegra_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq, 589 NULL); 590 } else if (data->type == INTR_MAP_DATA_GPIO) { 591 struct intr_map_data_gpio *dag; 592 593 dag = (struct intr_map_data_gpio *)data; 594 rv = tegra_gpio_pic_map_gpio(sc, dag->gpio_pin_num, 595 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, NULL); 596 } else 597 return (ENOTSUP); 598 599 if (rv == 0) 600 *isrcp = &sc->isrcs[irq].isrc; 601 return (rv); 602} 603 604static void 605tegra_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 606{ 607 struct tegra_gpio_softc *sc; 608 struct tegra_gpio_irqsrc *tgi; 609 610 sc = device_get_softc(dev); 611 tgi = (struct tegra_gpio_irqsrc *)isrc; 612 if (tegra_gpio_isrc_is_level(tgi)) 613 tegra_gpio_isrc_eoi(sc, tgi); 614} 615 616static void 617tegra_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 618{ 619 struct tegra_gpio_softc *sc; 620 struct tegra_gpio_irqsrc *tgi; 621 622 sc = device_get_softc(dev); 623 tgi = (struct tegra_gpio_irqsrc *)isrc; 624 tegra_gpio_isrc_mask(sc, tgi, 1); 625} 626 627static void 628tegra_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 629{ 630 struct tegra_gpio_softc *sc; 631 struct tegra_gpio_irqsrc *tgi; 632 633 sc = device_get_softc(dev); 634 tgi = (struct tegra_gpio_irqsrc *)isrc; 635 636 tegra_gpio_isrc_mask(sc, tgi, 0); 637 if (tegra_gpio_isrc_is_level(tgi)) 638 tegra_gpio_isrc_eoi(sc, tgi); 639} 640 641static int 642tegra_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 643 struct resource *res, struct intr_map_data *data) 644{ 645 u_int irq; 646 uint32_t cfgreg; 647 int rv; 648 struct tegra_gpio_softc *sc; 649 struct tegra_gpio_irqsrc *tgi; 650 651 sc = device_get_softc(dev); 652 tgi = (struct tegra_gpio_irqsrc *)isrc; 653 654 if (data == NULL) 655 return (ENOTSUP); 656 657 /* Get and check config for an interrupt. */ 658 if (data->type == INTR_MAP_DATA_FDT) { 659 struct intr_map_data_fdt *daf; 660 661 daf = (struct intr_map_data_fdt *)data; 662 rv = tegra_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq, 663 &cfgreg); 664 } else if (data->type == INTR_MAP_DATA_GPIO) { 665 struct intr_map_data_gpio *dag; 666 667 dag = (struct intr_map_data_gpio *)data; 668 rv = tegra_gpio_pic_map_gpio(sc, dag->gpio_pin_num, 669 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, &cfgreg); 670 } else 671 return (ENOTSUP); 672 if (rv != 0) 673 return (EINVAL); 674 675 /* 676 * If this is a setup for another handler, 677 * only check that its configuration match. 678 */ 679 if (isrc->isrc_handlers != 0) 680 return (tgi->cfgreg == cfgreg ? 0 : EINVAL); 681 682 tgi->cfgreg = cfgreg; 683 intr_write_modify(sc, GPIO_INT_LVL, tgi, cfgreg, GPIO_INT_LVL_MASK); 684 tegra_gpio_pic_enable_intr(dev, isrc); 685 686 return (0); 687} 688 689static int 690tegra_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 691 struct resource *res, struct intr_map_data *data) 692{ 693 struct tegra_gpio_softc *sc; 694 struct tegra_gpio_irqsrc *tgi; 695 696 sc = device_get_softc(dev); 697 tgi = (struct tegra_gpio_irqsrc *)isrc; 698 699 if (isrc->isrc_handlers == 0) 700 tegra_gpio_isrc_mask(sc, tgi, 0); 701 return (0); 702} 703 704static int 705tegra_gpio_probe(device_t dev) 706{ 707 708 if (!ofw_bus_status_okay(dev)) 709 return (ENXIO); 710 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 711 device_set_desc(dev, "Tegra GPIO Controller"); 712 return (BUS_PROBE_DEFAULT); 713 } 714 715 return (ENXIO); 716} 717 718/* -------------------------------------------------------------------------- 719 * 720 * Bus 721 * 722 */ 723static int 724tegra_gpio_detach(device_t dev) 725{ 726 struct tegra_gpio_softc *sc; 727 int i; 728 729 sc = device_get_softc(dev); 730 731 KASSERT(mtx_initialized(&sc->mtx), ("gpio mutex not initialized")); 732 733 for (i = 0; i < GPIO_NUM_BANKS; i++) { 734 if (sc->irq_ih[i] != NULL) 735 bus_teardown_intr(dev, sc->irq_res[i], sc->irq_ih[i]); 736 } 737 738 if (sc->isrcs != NULL) 739 tegra_gpio_pic_detach(sc); 740 741 gpiobus_detach_bus(dev); 742 743 for (i = 0; i < GPIO_NUM_BANKS; i++) { 744 if (sc->irq_res[i] != NULL) 745 bus_release_resource(dev, SYS_RES_IRQ, 0, 746 sc->irq_res[i]); 747 } 748 if (sc->mem_res != NULL) 749 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 750 GPIO_LOCK_DESTROY(sc); 751 752 return(0); 753} 754 755static int 756tegra_gpio_attach(device_t dev) 757{ 758 struct tegra_gpio_softc *sc; 759 int i, rid; 760 761 sc = device_get_softc(dev); 762 sc->dev = dev; 763 GPIO_LOCK_INIT(sc); 764 765 /* Allocate bus_space resources. */ 766 rid = 0; 767 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 768 RF_ACTIVE); 769 if (sc->mem_res == NULL) { 770 device_printf(dev, "Cannot allocate memory resources\n"); 771 tegra_gpio_detach(dev); 772 return (ENXIO); 773 } 774 775 sc->gpio_npins = NGPIO; 776 for (i = 0; i < sc->gpio_npins; i++) { 777 sc->gpio_pins[i].gp_pin = i; 778 sc->gpio_pins[i].gp_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 779 GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | 780 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | 781 GPIO_INTR_EDGE_BOTH; 782 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, "gpio_%s.%d", 783 tegra_gpio_port_names[ i / GPIO_PINS_IN_REG], 784 i % GPIO_PINS_IN_REG); 785 sc->gpio_pins[i].gp_flags = 786 gpio_read(sc, GPIO_OE, &sc->gpio_pins[i]) != 0 ? 787 GPIO_PIN_OUTPUT : GPIO_PIN_INPUT; 788 } 789 790 /* Init interrupt related registes. */ 791 for (i = 0; i < sc->gpio_npins; i += GPIO_PINS_IN_REG) { 792 bus_write_4(sc->mem_res, GPIO_INT_ENB + GPIO_REGNUM(i), 0); 793 bus_write_4(sc->mem_res, GPIO_INT_STA + GPIO_REGNUM(i), 0xFF); 794 bus_write_4(sc->mem_res, GPIO_INT_CLR + GPIO_REGNUM(i), 0xFF); 795 } 796 797 /* Allocate interrupts. */ 798 for (i = 0; i < GPIO_NUM_BANKS; i++) { 799 sc->irq_cookies[i].sc = sc; 800 sc->irq_cookies[i].bank_num = i; 801 rid = i; 802 sc->irq_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ, 803 &rid, RF_ACTIVE); 804 if (sc->irq_res[i] == NULL) { 805 device_printf(dev, "Cannot allocate IRQ resources\n"); 806 tegra_gpio_detach(dev); 807 return (ENXIO); 808 } 809 if ((bus_setup_intr(dev, sc->irq_res[i], 810 INTR_TYPE_MISC | INTR_MPSAFE, tegra_gpio_intr, NULL, 811 &sc->irq_cookies[i], &sc->irq_ih[i]))) { 812 device_printf(dev, 813 "WARNING: unable to register interrupt handler\n"); 814 tegra_gpio_detach(dev); 815 return (ENXIO); 816 } 817 } 818 819 if (tegra_gpio_pic_attach(sc) != 0) { 820 device_printf(dev, "WARNING: unable to attach PIC\n"); 821 tegra_gpio_detach(dev); 822 return (ENXIO); 823 } 824 825 sc->busdev = gpiobus_attach_bus(dev); 826 if (sc->busdev == NULL) { 827 tegra_gpio_detach(dev); 828 return (ENXIO); 829 } 830 831 return (bus_generic_attach(dev)); 832} 833 834static int 835tegra_map_gpios(device_t dev, phandle_t pdev, phandle_t gparent, 836 int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags) 837{ 838 839 if (gcells != 2) 840 return (ERANGE); 841 *pin = gpios[0]; 842 *flags= gpios[1]; 843 return (0); 844} 845 846static phandle_t 847tegra_gpio_get_node(device_t bus, device_t dev) 848{ 849 850 /* We only have one child, the GPIO bus, which needs our own node. */ 851 return (ofw_bus_get_node(bus)); 852} 853 854static device_method_t tegra_gpio_methods[] = { 855 DEVMETHOD(device_probe, tegra_gpio_probe), 856 DEVMETHOD(device_attach, tegra_gpio_attach), 857 DEVMETHOD(device_detach, tegra_gpio_detach), 858 859 /* Interrupt controller interface */ 860 DEVMETHOD(pic_disable_intr, tegra_gpio_pic_disable_intr), 861 DEVMETHOD(pic_enable_intr, tegra_gpio_pic_enable_intr), 862 DEVMETHOD(pic_map_intr, tegra_gpio_pic_map_intr), 863 DEVMETHOD(pic_setup_intr, tegra_gpio_pic_setup_intr), 864 DEVMETHOD(pic_teardown_intr, tegra_gpio_pic_teardown_intr), 865 DEVMETHOD(pic_post_filter, tegra_gpio_pic_post_filter), 866 DEVMETHOD(pic_post_ithread, tegra_gpio_pic_post_ithread), 867 DEVMETHOD(pic_pre_ithread, tegra_gpio_pic_pre_ithread), 868 869 /* GPIO protocol */ 870 DEVMETHOD(gpio_get_bus, tegra_gpio_get_bus), 871 DEVMETHOD(gpio_pin_max, tegra_gpio_pin_max), 872 DEVMETHOD(gpio_pin_getname, tegra_gpio_pin_getname), 873 DEVMETHOD(gpio_pin_getflags, tegra_gpio_pin_getflags), 874 DEVMETHOD(gpio_pin_getcaps, tegra_gpio_pin_getcaps), 875 DEVMETHOD(gpio_pin_setflags, tegra_gpio_pin_setflags), 876 DEVMETHOD(gpio_pin_get, tegra_gpio_pin_get), 877 DEVMETHOD(gpio_pin_set, tegra_gpio_pin_set), 878 DEVMETHOD(gpio_pin_toggle, tegra_gpio_pin_toggle), 879 DEVMETHOD(gpio_map_gpios, tegra_map_gpios), 880 881 /* ofw_bus interface */ 882 DEVMETHOD(ofw_bus_get_node, tegra_gpio_get_node), 883 884 DEVMETHOD_END 885}; 886 887static devclass_t tegra_gpio_devclass; 888static DEFINE_CLASS_0(gpio, tegra_gpio_driver, tegra_gpio_methods, 889 sizeof(struct tegra_gpio_softc)); 890EARLY_DRIVER_MODULE(tegra_gpio, simplebus, tegra_gpio_driver, 891 tegra_gpio_devclass, NULL, NULL, 70); 892