1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Olivier Houchard. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 28/* 29 * $FreeBSD$ 30 */ 31 32#ifndef PL310_H_ 33#define PL310_H_ 34 35/** 36 * PL310 - L2 Cache Controller register offsets. 37 * 38 */ 39#define PL310_CACHE_ID 0x000 40#define CACHE_ID_RELEASE_SHIFT 0 41#define CACHE_ID_RELEASE_MASK 0x3f 42#define CACHE_ID_RELEASE_r0p0 0x00 43#define CACHE_ID_RELEASE_r1p0 0x02 44#define CACHE_ID_RELEASE_r2p0 0x04 45#define CACHE_ID_RELEASE_r3p0 0x05 46#define CACHE_ID_RELEASE_r3p1 0x06 47#define CACHE_ID_RELEASE_r3p2 0x08 48#define CACHE_ID_RELEASE_r3p3 0x09 49#define CACHE_ID_PARTNUM_SHIFT 6 50#define CACHE_ID_PARTNUM_MASK 0xf 51#define CACHE_ID_PARTNUM_VALUE 0x3 52#define PL310_CACHE_TYPE 0x004 53#define PL310_CTRL 0x100 54#define CTRL_ENABLED 0x01 55#define CTRL_DISABLED 0x00 56#define PL310_AUX_CTRL 0x104 57#define AUX_CTRL_MASK 0xc0000fff 58#define AUX_CTRL_ASSOCIATIVITY_SHIFT 16 59#define AUX_CTRL_WAY_SIZE_SHIFT 17 60#define AUX_CTRL_WAY_SIZE_MASK (0x7 << 17) 61#define AUX_CTRL_SHARE_OVERRIDE (1 << 22) 62#define AUX_CTRL_NS_LOCKDOWN (1 << 26) 63#define AUX_CTRL_NS_INT_CTRL (1 << 27) 64#define AUX_CTRL_DATA_PREFETCH (1 << 28) 65#define AUX_CTRL_INSTR_PREFETCH (1 << 29) 66#define AUX_CTRL_EARLY_BRESP (1 << 30) 67#define PL310_TAG_RAM_CTRL 0x108 68#define PL310_DATA_RAM_CTRL 0x10C 69#define RAM_CTRL_WRITE_SHIFT 8 70#define RAM_CTRL_WRITE_MASK (0x7 << 8) 71#define RAM_CTRL_READ_SHIFT 4 72#define RAM_CTRL_READ_MASK (0x7 << 4) 73#define RAM_CTRL_SETUP_SHIFT 0 74#define RAM_CTRL_SETUP_MASK (0x7 << 0) 75#define PL310_EVENT_COUNTER_CTRL 0x200 76#define EVENT_COUNTER_CTRL_ENABLED (1 << 0) 77#define EVENT_COUNTER_CTRL_C0_RESET (1 << 1) 78#define EVENT_COUNTER_CTRL_C1_RESET (1 << 2) 79#define PL310_EVENT_COUNTER1_CONF 0x204 80#define PL310_EVENT_COUNTER0_CONF 0x208 81#define EVENT_COUNTER_CONF_NOINTR 0 82#define EVENT_COUNTER_CONF_INCR 1 83#define EVENT_COUNTER_CONF_OVFW 2 84#define EVENT_COUNTER_CONF_NOEV (0 << 2) 85#define EVENT_COUNTER_CONF_CO (1 << 2) 86#define EVENT_COUNTER_CONF_DRHIT (2 << 2) 87#define EVENT_COUNTER_CONF_DRREQ (3 << 2) 88#define EVENT_COUNTER_CONF_DWHIT (4 << 2) 89#define EVENT_COUNTER_CONF_DWREQ (5 << 2) 90#define EVENT_COUNTER_CONF_DWTREQ (6 << 2) 91#define EVENT_COUNTER_CONF_DIRHIT (7 << 2) 92#define EVENT_COUNTER_CONF_DIRREQ (8 << 2) 93#define EVENT_COUNTER_CONF_WA (9 << 2) 94#define PL310_EVENT_COUNTER1_VAL 0x20C 95#define PL310_EVENT_COUNTER0_VAL 0x210 96#define PL310_INTR_MASK 0x214 97#define PL310_MASKED_INTR_STAT 0x218 98#define PL310_RAW_INTR_STAT 0x21C 99#define PL310_INTR_CLEAR 0x220 100#define INTR_MASK_ALL ((1 << 9) - 1) 101#define INTR_MASK_ECNTR (1 << 0) 102#define INTR_MASK_PARRT (1 << 1) 103#define INTR_MASK_PARRD (1 << 2) 104#define INTR_MASK_ERRWT (1 << 3) 105#define INTR_MASK_ERRWD (1 << 4) 106#define INTR_MASK_ERRRT (1 << 5) 107#define INTR_MASK_ERRRD (1 << 6) 108#define INTR_MASK_SLVERR (1 << 7) 109#define INTR_MASK_DECERR (1 << 8) 110#define PL310_CACHE_SYNC 0x730 111#define PL310_INV_LINE_PA 0x770 112#define PL310_INV_WAY 0x77C 113#define PL310_CLEAN_LINE_PA 0x7B0 114#define PL310_CLEAN_LINE_IDX 0x7B8 115#define PL310_CLEAN_WAY 0x7BC 116#define PL310_CLEAN_INV_LINE_PA 0x7F0 117#define PL310_CLEAN_INV_LINE_IDX 0x7F8 118#define PL310_CLEAN_INV_WAY 0x7FC 119#define PL310_LOCKDOWN_D_WAY(x) (0x900 + ((x) * 8)) 120#define PL310_LOCKDOWN_I_WAY(x) (0x904 + ((x) * 8)) 121#define PL310_LOCKDOWN_LINE_ENABLE 0x950 122#define PL310_UNLOCK_ALL_LINES_WAY 0x954 123#define PL310_ADDR_FILTER_STAR 0xC00 124#define PL310_ADDR_FILTER_END 0xC04 125#define PL310_DEBUG_CTRL 0xF40 126#define DEBUG_CTRL_DISABLE_LINEFILL (1 << 0) 127#define DEBUG_CTRL_DISABLE_WRITEBACK (1 << 1) 128#define DEBUG_CTRL_SPNIDEN (1 << 2) 129#define PL310_PREFETCH_CTRL 0xF60 130#define PREFETCH_CTRL_OFFSET_MASK (0x1f) 131#define PREFETCH_CTRL_NOTSAMEID (1 << 21) 132#define PREFETCH_CTRL_INCR_DL (1 << 23) 133#define PREFETCH_CTRL_PREFETCH_DROP (1 << 24) 134#define PREFETCH_CTRL_DL_ON_WRAP (1 << 27) 135#define PREFETCH_CTRL_DATA_PREFETCH (1 << 28) 136#define PREFETCH_CTRL_INSTR_PREFETCH (1 << 29) 137#define PREFETCH_CTRL_DL (1 << 30) 138#define PL310_POWER_CTRL 0xF80 139#define POWER_CTRL_ENABLE_GATING (1 << 1) 140#define POWER_CTRL_ENABLE_STANDBY (1 << 0) 141 142struct intr_config_hook; 143 144struct pl310_softc { 145 device_t sc_dev; 146 struct resource *sc_mem_res; 147 struct resource *sc_irq_res; 148 void* sc_irq_h; 149 int sc_enabled; 150 struct mtx sc_mtx; 151 u_int sc_rtl_revision; 152 struct intr_config_hook *sc_ich; 153 boolean_t sc_io_coherent; 154}; 155 156/** 157 * pl310_read4 - read a 32-bit value from the PL310 registers 158 * pl310_write4 - write a 32-bit value from the PL310 registers 159 * @off: byte offset within the register set to read from 160 * @val: the value to write into the register 161 * 162 * 163 * LOCKING: 164 * None 165 * 166 * RETURNS: 167 * nothing in case of write function, if read function returns the value read. 168 */ 169static __inline uint32_t 170pl310_read4(struct pl310_softc *sc, bus_size_t off) 171{ 172 173 return bus_read_4(sc->sc_mem_res, off); 174} 175 176static __inline void 177pl310_write4(struct pl310_softc *sc, bus_size_t off, uint32_t val) 178{ 179 180 bus_write_4(sc->sc_mem_res, off, val); 181} 182 183void pl310_set_ram_latency(struct pl310_softc *sc, uint32_t which_reg, 184 uint32_t read, uint32_t write, uint32_t setup); 185 186#ifndef PLATFORM 187void platform_pl310_init(struct pl310_softc *); 188void platform_pl310_write_ctrl(struct pl310_softc *, uint32_t); 189void platform_pl310_write_debug(struct pl310_softc *, uint32_t); 190#endif 191 192#endif /* PL310_H_ */ 193