1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 5 * All rights reserved. 6 * 7 * Based on OMAP3 INTC code by Ben Gray 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD$"); 34 35#include "opt_platform.h" 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/bus.h> 40#include <sys/kernel.h> 41#include <sys/ktr.h> 42#include <sys/module.h> 43#include <sys/proc.h> 44#include <sys/rman.h> 45#include <machine/bus.h> 46#include <machine/intr.h> 47 48#include <dev/ofw/openfirm.h> 49#include <dev/ofw/ofw_bus.h> 50#include <dev/ofw/ofw_bus_subr.h> 51 52#include "pic_if.h" 53 54#define INTC_PENDING_BASIC 0x00 55#define INTC_PENDING_BANK1 0x04 56#define INTC_PENDING_BANK2 0x08 57#define INTC_FIQ_CONTROL 0x0C 58#define INTC_ENABLE_BANK1 0x10 59#define INTC_ENABLE_BANK2 0x14 60#define INTC_ENABLE_BASIC 0x18 61#define INTC_DISABLE_BANK1 0x1C 62#define INTC_DISABLE_BANK2 0x20 63#define INTC_DISABLE_BASIC 0x24 64 65#define INTC_PENDING_BASIC_ARM 0x0000FF 66#define INTC_PENDING_BASIC_GPU1_PEND 0x000100 67#define INTC_PENDING_BASIC_GPU2_PEND 0x000200 68#define INTC_PENDING_BASIC_GPU1_7 0x000400 69#define INTC_PENDING_BASIC_GPU1_9 0x000800 70#define INTC_PENDING_BASIC_GPU1_10 0x001000 71#define INTC_PENDING_BASIC_GPU1_18 0x002000 72#define INTC_PENDING_BASIC_GPU1_19 0x004000 73#define INTC_PENDING_BASIC_GPU2_21 0x008000 74#define INTC_PENDING_BASIC_GPU2_22 0x010000 75#define INTC_PENDING_BASIC_GPU2_23 0x020000 76#define INTC_PENDING_BASIC_GPU2_24 0x040000 77#define INTC_PENDING_BASIC_GPU2_25 0x080000 78#define INTC_PENDING_BASIC_GPU2_30 0x100000 79#define INTC_PENDING_BASIC_MASK 0x1FFFFF 80 81#define INTC_PENDING_BASIC_GPU1_MASK (INTC_PENDING_BASIC_GPU1_7 | \ 82 INTC_PENDING_BASIC_GPU1_9 | \ 83 INTC_PENDING_BASIC_GPU1_10 | \ 84 INTC_PENDING_BASIC_GPU1_18 | \ 85 INTC_PENDING_BASIC_GPU1_19) 86 87#define INTC_PENDING_BASIC_GPU2_MASK (INTC_PENDING_BASIC_GPU2_21 | \ 88 INTC_PENDING_BASIC_GPU2_22 | \ 89 INTC_PENDING_BASIC_GPU2_23 | \ 90 INTC_PENDING_BASIC_GPU2_24 | \ 91 INTC_PENDING_BASIC_GPU2_25 | \ 92 INTC_PENDING_BASIC_GPU2_30) 93 94#define INTC_PENDING_BANK1_MASK (~((1 << 7) | (1 << 9) | (1 << 10) | \ 95 (1 << 18) | (1 << 19))) 96#define INTC_PENDING_BANK2_MASK (~((1 << 21) | (1 << 22) | (1 << 23) | \ 97 (1 << 24) | (1 << 25) | (1 << 30))) 98 99#define BANK1_START 8 100#define BANK1_END (BANK1_START + 32 - 1) 101#define BANK2_START (BANK1_START + 32) 102#define BANK2_END (BANK2_START + 32 - 1) 103 104#define IS_IRQ_BASIC(n) (((n) >= 0) && ((n) < BANK1_START)) 105#define IS_IRQ_BANK1(n) (((n) >= BANK1_START) && ((n) <= BANK1_END)) 106#define IS_IRQ_BANK2(n) (((n) >= BANK2_START) && ((n) <= BANK2_END)) 107#define IRQ_BANK1(n) ((n) - BANK1_START) 108#define IRQ_BANK2(n) ((n) - BANK2_START) 109 110#ifdef DEBUG 111#define dprintf(fmt, args...) printf(fmt, ##args) 112#else 113#define dprintf(fmt, args...) 114#endif 115 116#define BCM_INTC_NIRQS 72 /* 8 + 32 + 32 */ 117 118struct bcm_intc_irqsrc { 119 struct intr_irqsrc bii_isrc; 120 u_int bii_irq; 121 uint16_t bii_disable_reg; 122 uint16_t bii_enable_reg; 123 uint32_t bii_mask; 124}; 125 126struct bcm_intc_softc { 127 device_t sc_dev; 128 struct resource * intc_res; 129 bus_space_tag_t intc_bst; 130 bus_space_handle_t intc_bsh; 131 struct resource * intc_irq_res; 132 void * intc_irq_hdl; 133 struct bcm_intc_irqsrc intc_isrcs[BCM_INTC_NIRQS]; 134}; 135 136static struct ofw_compat_data compat_data[] = { 137 {"broadcom,bcm2835-armctrl-ic", 1}, 138 {"brcm,bcm2835-armctrl-ic", 1}, 139 {"brcm,bcm2836-armctrl-ic", 1}, 140 {NULL, 0} 141}; 142 143static struct bcm_intc_softc *bcm_intc_sc = NULL; 144 145#define intc_read_4(_sc, reg) \ 146 bus_space_read_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg)) 147#define intc_write_4(_sc, reg, val) \ 148 bus_space_write_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg), (val)) 149 150static inline void 151bcm_intc_isrc_mask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii) 152{ 153 154 intc_write_4(sc, bii->bii_disable_reg, bii->bii_mask); 155} 156 157static inline void 158bcm_intc_isrc_unmask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii) 159{ 160 161 intc_write_4(sc, bii->bii_enable_reg, bii->bii_mask); 162} 163 164static inline int 165bcm2835_intc_active_intr(struct bcm_intc_softc *sc) 166{ 167 uint32_t pending, pending_gpu; 168 169 pending = intc_read_4(sc, INTC_PENDING_BASIC) & INTC_PENDING_BASIC_MASK; 170 if (pending == 0) 171 return (-1); 172 if (pending & INTC_PENDING_BASIC_ARM) 173 return (ffs(pending) - 1); 174 if (pending & INTC_PENDING_BASIC_GPU1_MASK) { 175 if (pending & INTC_PENDING_BASIC_GPU1_7) 176 return (BANK1_START + 7); 177 if (pending & INTC_PENDING_BASIC_GPU1_9) 178 return (BANK1_START + 9); 179 if (pending & INTC_PENDING_BASIC_GPU1_10) 180 return (BANK1_START + 10); 181 if (pending & INTC_PENDING_BASIC_GPU1_18) 182 return (BANK1_START + 18); 183 if (pending & INTC_PENDING_BASIC_GPU1_19) 184 return (BANK1_START + 19); 185 } 186 if (pending & INTC_PENDING_BASIC_GPU2_MASK) { 187 if (pending & INTC_PENDING_BASIC_GPU2_21) 188 return (BANK2_START + 21); 189 if (pending & INTC_PENDING_BASIC_GPU2_22) 190 return (BANK2_START + 22); 191 if (pending & INTC_PENDING_BASIC_GPU2_23) 192 return (BANK2_START + 23); 193 if (pending & INTC_PENDING_BASIC_GPU2_24) 194 return (BANK2_START + 24); 195 if (pending & INTC_PENDING_BASIC_GPU2_25) 196 return (BANK2_START + 25); 197 if (pending & INTC_PENDING_BASIC_GPU2_30) 198 return (BANK2_START + 30); 199 } 200 if (pending & INTC_PENDING_BASIC_GPU1_PEND) { 201 pending_gpu = intc_read_4(sc, INTC_PENDING_BANK1); 202 pending_gpu &= INTC_PENDING_BANK1_MASK; 203 if (pending_gpu != 0) 204 return (BANK1_START + ffs(pending_gpu) - 1); 205 } 206 if (pending & INTC_PENDING_BASIC_GPU2_PEND) { 207 pending_gpu = intc_read_4(sc, INTC_PENDING_BANK2); 208 pending_gpu &= INTC_PENDING_BANK2_MASK; 209 if (pending_gpu != 0) 210 return (BANK2_START + ffs(pending_gpu) - 1); 211 } 212 return (-1); /* It shouldn't end here, but it's hardware. */ 213} 214 215static int 216bcm2835_intc_intr(void *arg) 217{ 218 int irq, num; 219 struct bcm_intc_softc *sc = arg; 220 221 for (num = 0; ; num++) { 222 irq = bcm2835_intc_active_intr(sc); 223 if (irq == -1) 224 break; 225 if (intr_isrc_dispatch(&sc->intc_isrcs[irq].bii_isrc, 226 curthread->td_intr_frame) != 0) { 227 bcm_intc_isrc_mask(sc, &sc->intc_isrcs[irq]); 228 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 229 irq); 230 } 231 arm_irq_memory_barrier(0); /* XXX */ 232 } 233 if (num == 0 && bootverbose) 234 device_printf(sc->sc_dev, "Spurious interrupt detected\n"); 235 236 return (FILTER_HANDLED); 237} 238 239static void 240bcm_intc_enable_intr(device_t dev, struct intr_irqsrc *isrc) 241{ 242 struct bcm_intc_irqsrc *bii = (struct bcm_intc_irqsrc *)isrc; 243 244 arm_irq_memory_barrier(bii->bii_irq); 245 bcm_intc_isrc_unmask(device_get_softc(dev), bii); 246} 247 248static void 249bcm_intc_disable_intr(device_t dev, struct intr_irqsrc *isrc) 250{ 251 252 bcm_intc_isrc_mask(device_get_softc(dev), 253 (struct bcm_intc_irqsrc *)isrc); 254} 255 256static int 257bcm_intc_map_intr(device_t dev, struct intr_map_data *data, 258 struct intr_irqsrc **isrcp) 259{ 260 u_int irq; 261 struct intr_map_data_fdt *daf; 262 struct bcm_intc_softc *sc; 263 bool valid; 264 265 if (data->type != INTR_MAP_DATA_FDT) 266 return (ENOTSUP); 267 268 daf = (struct intr_map_data_fdt *)data; 269 if (daf->ncells == 1) 270 irq = daf->cells[0]; 271 else if (daf->ncells == 2) { 272 valid = true; 273 switch (daf->cells[0]) { 274 case 0: 275 irq = daf->cells[1]; 276 if (irq >= BANK1_START) 277 valid = false; 278 break; 279 case 1: 280 irq = daf->cells[1] + BANK1_START; 281 if (irq > BANK1_END) 282 valid = false; 283 break; 284 case 2: 285 irq = daf->cells[1] + BANK2_START; 286 if (irq > BANK2_END) 287 valid = false; 288 break; 289 default: 290 valid = false; 291 break; 292 } 293 294 if (!valid) { 295 device_printf(dev, 296 "invalid IRQ config: bank=%d, irq=%d\n", 297 daf->cells[0], daf->cells[1]); 298 return (EINVAL); 299 } 300 } 301 else 302 return (EINVAL); 303 304 if (irq >= BCM_INTC_NIRQS) 305 return (EINVAL); 306 307 sc = device_get_softc(dev); 308 *isrcp = &sc->intc_isrcs[irq].bii_isrc; 309 return (0); 310} 311 312static void 313bcm_intc_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 314{ 315 316 bcm_intc_disable_intr(dev, isrc); 317} 318 319static void 320bcm_intc_post_ithread(device_t dev, struct intr_irqsrc *isrc) 321{ 322 323 bcm_intc_enable_intr(dev, isrc); 324} 325 326static void 327bcm_intc_post_filter(device_t dev, struct intr_irqsrc *isrc) 328{ 329} 330 331static int 332bcm_intc_pic_register(struct bcm_intc_softc *sc, intptr_t xref) 333{ 334 struct bcm_intc_irqsrc *bii; 335 int error; 336 uint32_t irq; 337 const char *name; 338 339 name = device_get_nameunit(sc->sc_dev); 340 for (irq = 0; irq < BCM_INTC_NIRQS; irq++) { 341 bii = &sc->intc_isrcs[irq]; 342 bii->bii_irq = irq; 343 if (IS_IRQ_BASIC(irq)) { 344 bii->bii_disable_reg = INTC_DISABLE_BASIC; 345 bii->bii_enable_reg = INTC_ENABLE_BASIC; 346 bii->bii_mask = 1 << irq; 347 } else if (IS_IRQ_BANK1(irq)) { 348 bii->bii_disable_reg = INTC_DISABLE_BANK1; 349 bii->bii_enable_reg = INTC_ENABLE_BANK1; 350 bii->bii_mask = 1 << IRQ_BANK1(irq); 351 } else if (IS_IRQ_BANK2(irq)) { 352 bii->bii_disable_reg = INTC_DISABLE_BANK2; 353 bii->bii_enable_reg = INTC_ENABLE_BANK2; 354 bii->bii_mask = 1 << IRQ_BANK2(irq); 355 } else 356 return (ENXIO); 357 358 error = intr_isrc_register(&bii->bii_isrc, sc->sc_dev, 0, 359 "%s,%u", name, irq); 360 if (error != 0) 361 return (error); 362 } 363 if (intr_pic_register(sc->sc_dev, xref) == NULL) 364 return (ENXIO); 365 366 return (0); 367} 368 369static int 370bcm_intc_probe(device_t dev) 371{ 372 373 if (!ofw_bus_status_okay(dev)) 374 return (ENXIO); 375 376 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 377 return (ENXIO); 378 379 device_set_desc(dev, "BCM2835 Interrupt Controller"); 380 return (BUS_PROBE_DEFAULT); 381} 382 383static int 384bcm_intc_attach(device_t dev) 385{ 386 struct bcm_intc_softc *sc = device_get_softc(dev); 387 int rid = 0; 388 intptr_t xref; 389 sc->sc_dev = dev; 390 391 if (bcm_intc_sc) 392 return (ENXIO); 393 394 sc->intc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 395 if (sc->intc_res == NULL) { 396 device_printf(dev, "could not allocate memory resource\n"); 397 return (ENXIO); 398 } 399 400 xref = OF_xref_from_node(ofw_bus_get_node(dev)); 401 if (bcm_intc_pic_register(sc, xref) != 0) { 402 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->intc_res); 403 device_printf(dev, "could not register PIC\n"); 404 return (ENXIO); 405 } 406 407 rid = 0; 408 sc->intc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 409 RF_ACTIVE); 410 if (sc->intc_irq_res == NULL) { 411 if (intr_pic_claim_root(dev, xref, bcm2835_intc_intr, sc, 0) != 0) { 412 /* XXX clean up */ 413 device_printf(dev, "could not set PIC as a root\n"); 414 return (ENXIO); 415 } 416 } else { 417 if (bus_setup_intr(dev, sc->intc_irq_res, INTR_TYPE_CLK, 418 bcm2835_intc_intr, NULL, sc, &sc->intc_irq_hdl)) { 419 /* XXX clean up */ 420 device_printf(dev, "could not setup irq handler\n"); 421 return (ENXIO); 422 } 423 } 424 sc->intc_bst = rman_get_bustag(sc->intc_res); 425 sc->intc_bsh = rman_get_bushandle(sc->intc_res); 426 427 bcm_intc_sc = sc; 428 429 return (0); 430} 431 432static device_method_t bcm_intc_methods[] = { 433 DEVMETHOD(device_probe, bcm_intc_probe), 434 DEVMETHOD(device_attach, bcm_intc_attach), 435 436 DEVMETHOD(pic_disable_intr, bcm_intc_disable_intr), 437 DEVMETHOD(pic_enable_intr, bcm_intc_enable_intr), 438 DEVMETHOD(pic_map_intr, bcm_intc_map_intr), 439 DEVMETHOD(pic_post_filter, bcm_intc_post_filter), 440 DEVMETHOD(pic_post_ithread, bcm_intc_post_ithread), 441 DEVMETHOD(pic_pre_ithread, bcm_intc_pre_ithread), 442 443 { 0, 0 } 444}; 445 446static driver_t bcm_intc_driver = { 447 "intc", 448 bcm_intc_methods, 449 sizeof(struct bcm_intc_softc), 450}; 451 452static devclass_t bcm_intc_devclass; 453 454EARLY_DRIVER_MODULE(intc, simplebus, bcm_intc_driver, bcm_intc_devclass, 455 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 456