1/*-
2 * Copyright 2013-2015 John Wehle <john@feith.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 */
27
28/*
29 * Amlogic aml8726 timer driver.
30 *
31 * 16 bit Timer A is used for the event timer / hard clock.
32 * 32 bit Timer E is used for the timecounter / DELAY.
33 *
34 * The current implementation doesn't use Timers B-D.  Another approach is
35 * to split the timers between the cores implementing per cpu event timers.
36 *
37 * The timers all share the MUX register which requires a mutex to serialize
38 * access.  The mutex is also used to avoid potential problems between the
39 * interrupt handler and timer_start / timer_stop.
40 */
41
42#include <sys/cdefs.h>
43__FBSDID("$FreeBSD$");
44
45#include <sys/param.h>
46#include <sys/systm.h>
47#include <sys/bus.h>
48#include <sys/kernel.h>
49#include <sys/module.h>
50#include <sys/malloc.h>
51#include <sys/rman.h>
52#include <sys/timetc.h>
53#include <sys/timeet.h>
54
55#include <machine/bus.h>
56#include <machine/cpu.h>
57
58#include <dev/ofw/ofw_bus.h>
59#include <dev/ofw/ofw_bus_subr.h>
60
61struct aml8726_timer_softc {
62	device_t		dev;
63	struct resource	*	res[2];
64	struct mtx		mtx;
65	void *			ih_cookie;
66	struct eventtimer	et;
67	uint32_t		first_ticks;
68	uint32_t		period_ticks;
69	struct timecounter	tc;
70};
71
72static struct resource_spec aml8726_timer_spec[] = {
73	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
74	{ SYS_RES_IRQ,		0,	RF_ACTIVE },	/* INT_TIMER_A */
75	{ -1, 0 }
76};
77
78/*
79 * devclass_get_device / device_get_softc could be used
80 * to dynamically locate this, however the timers are a
81 * required device which can't be unloaded so there's
82 * no need for the overhead.
83 */
84static struct aml8726_timer_softc *aml8726_timer_sc = NULL;
85
86#define	AML_TIMER_LOCK(sc)		mtx_lock_spin(&(sc)->mtx)
87#define	AML_TIMER_UNLOCK(sc)		mtx_unlock_spin(&(sc)->mtx)
88#define	AML_TIMER_LOCK_INIT(sc)		\
89    mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev),	\
90    "timer", MTX_SPIN)
91#define	AML_TIMER_LOCK_DESTROY(sc)	mtx_destroy(&(sc)->mtx);
92
93#define	AML_TIMER_MUX_REG		0
94#define	AML_TIMER_INPUT_1us		0
95#define	AML_TIMER_INPUT_10us		1
96#define	AML_TIMER_INPUT_100us		2
97#define	AML_TIMER_INPUT_1ms		3
98#define	AML_TIMER_INPUT_MASK		3
99#define	AML_TIMER_A_INPUT_MASK		3
100#define	AML_TIMER_A_INPUT_SHIFT		0
101#define	AML_TIMER_B_INPUT_MASK		(3 << 2)
102#define	AML_TIMER_B_INPUT_SHIFT		2
103#define	AML_TIMER_C_INPUT_MASK		(3 << 4)
104#define	AML_TIMER_C_INPUT_SHIFT		4
105#define	AML_TIMER_D_INPUT_MASK		(3 << 6)
106#define	AML_TIMER_D_INPUT_SHIFT		6
107#define	AML_TIMER_E_INPUT_SYS		0
108#define	AML_TIMER_E_INPUT_1us		1
109#define	AML_TIMER_E_INPUT_10us		2
110#define	AML_TIMER_E_INPUT_100us		3
111#define	AML_TIMER_E_INPUT_1ms		4
112#define	AML_TIMER_E_INPUT_MASK		(7 << 8)
113#define	AML_TIMER_E_INPUT_SHIFT		8
114#define	AML_TIMER_A_PERIODIC		(1 << 12)
115#define	AML_TIMER_B_PERIODIC		(1 << 13)
116#define	AML_TIMER_C_PERIODIC		(1 << 14)
117#define	AML_TIMER_D_PERIODIC		(1 << 15)
118#define	AML_TIMER_A_EN			(1 << 16)
119#define	AML_TIMER_B_EN			(1 << 17)
120#define	AML_TIMER_C_EN			(1 << 18)
121#define	AML_TIMER_D_EN			(1 << 19)
122#define	AML_TIMER_E_EN			(1 << 20)
123#define	AML_TIMER_A_REG			4
124#define	AML_TIMER_B_REG			8
125#define	AML_TIMER_C_REG			12
126#define	AML_TIMER_D_REG			16
127#define	AML_TIMER_E_REG			20
128
129#define	CSR_WRITE_4(sc, reg, val)	bus_write_4((sc)->res[0], reg, (val))
130#define	CSR_READ_4(sc, reg)		bus_read_4((sc)->res[0], reg)
131
132static unsigned
133aml8726_get_timecount(struct timecounter *tc)
134{
135	struct aml8726_timer_softc *sc =
136	    (struct aml8726_timer_softc *)tc->tc_priv;
137
138	return CSR_READ_4(sc, AML_TIMER_E_REG);
139}
140
141static int
142aml8726_hardclock(void *arg)
143{
144	struct aml8726_timer_softc *sc = (struct aml8726_timer_softc *)arg;
145
146	AML_TIMER_LOCK(sc);
147
148	if (sc->first_ticks != 0 && sc->period_ticks != 0) {
149		sc->first_ticks = 0;
150
151		CSR_WRITE_4(sc, AML_TIMER_A_REG, sc->period_ticks);
152		CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
153		    (CSR_READ_4(sc, AML_TIMER_MUX_REG) |
154		    AML_TIMER_A_PERIODIC | AML_TIMER_A_EN));
155	}
156
157	AML_TIMER_UNLOCK(sc);
158
159	if (sc->et.et_active)
160		sc->et.et_event_cb(&sc->et, sc->et.et_arg);
161
162	return (FILTER_HANDLED);
163}
164
165static int
166aml8726_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
167{
168	struct aml8726_timer_softc *sc =
169	    (struct aml8726_timer_softc *)et->et_priv;
170	uint32_t first_ticks;
171	uint32_t period_ticks;
172	uint32_t periodic;
173	uint32_t ticks;
174
175	first_ticks = (first * et->et_frequency) / SBT_1S;
176	period_ticks = (period * et->et_frequency) / SBT_1S;
177
178	if (first_ticks != 0) {
179		ticks = first_ticks;
180		periodic = 0;
181
182	} else {
183		ticks = period_ticks;
184		periodic = AML_TIMER_A_PERIODIC;
185	}
186
187	if (ticks == 0)
188		return (EINVAL);
189
190	AML_TIMER_LOCK(sc);
191
192	sc->first_ticks = first_ticks;
193	sc->period_ticks = period_ticks;
194
195	CSR_WRITE_4(sc, AML_TIMER_A_REG, ticks);
196	CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
197	    ((CSR_READ_4(sc, AML_TIMER_MUX_REG) & ~AML_TIMER_A_PERIODIC) |
198	    AML_TIMER_A_EN | periodic));
199
200	AML_TIMER_UNLOCK(sc);
201
202	return (0);
203}
204
205static int
206aml8726_timer_stop(struct eventtimer *et)
207{
208	struct aml8726_timer_softc *sc =
209	    (struct aml8726_timer_softc *)et->et_priv;
210
211	AML_TIMER_LOCK(sc);
212
213	CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
214	    (CSR_READ_4(sc, AML_TIMER_MUX_REG) & ~AML_TIMER_A_EN));
215
216	AML_TIMER_UNLOCK(sc);
217
218	return (0);
219}
220
221static int
222aml8726_timer_probe(device_t dev)
223{
224
225	if (!ofw_bus_status_okay(dev))
226		return (ENXIO);
227
228	if (!ofw_bus_is_compatible(dev, "amlogic,meson6-timer"))
229		return (ENXIO);
230
231	device_set_desc(dev, "Amlogic aml8726 timer");
232
233	return (BUS_PROBE_DEFAULT);
234}
235
236static int
237aml8726_timer_attach(device_t dev)
238{
239	struct aml8726_timer_softc *sc = device_get_softc(dev);
240
241	/* There should be exactly one instance. */
242	if (aml8726_timer_sc != NULL)
243		return (ENXIO);
244
245	sc->dev = dev;
246
247	if (bus_alloc_resources(dev, aml8726_timer_spec, sc->res)) {
248		device_printf(dev, "can not allocate resources for device\n");
249		return (ENXIO);
250	}
251
252	/*
253	 * Disable the timers, select the input for each timer,
254	 * clear timer E, and then enable timer E.
255	 */
256	CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
257	    ((CSR_READ_4(sc, AML_TIMER_MUX_REG) &
258	    ~(AML_TIMER_A_EN | AML_TIMER_A_INPUT_MASK |
259	    AML_TIMER_E_EN | AML_TIMER_E_INPUT_MASK)) |
260	    (AML_TIMER_INPUT_1us << AML_TIMER_A_INPUT_SHIFT) |
261	    (AML_TIMER_E_INPUT_1us << AML_TIMER_E_INPUT_SHIFT)));
262
263	CSR_WRITE_4(sc, AML_TIMER_E_REG, 0);
264
265	CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
266	    (CSR_READ_4(sc, AML_TIMER_MUX_REG) | AML_TIMER_E_EN));
267
268	/*
269	 * Initialize the mutex prior to installing the interrupt handler
270	 * in case of a spurious interrupt.
271	 */
272	AML_TIMER_LOCK_INIT(sc);
273
274	if (bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK,
275	    aml8726_hardclock, NULL, sc, &sc->ih_cookie)) {
276		device_printf(dev, "could not setup interrupt handler\n");
277		bus_release_resources(dev, aml8726_timer_spec, sc->res);
278		AML_TIMER_LOCK_DESTROY(sc);
279		return (ENXIO);
280	}
281
282	aml8726_timer_sc = sc;
283
284	sc->et.et_name = "aml8726 timer A";
285	sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
286	sc->et.et_frequency = 1000000;
287	sc->et.et_quality = 1000;
288	sc->et.et_min_period = (0x00000002LLU * SBT_1S) / sc->et.et_frequency;
289	sc->et.et_max_period = (0x0000fffeLLU * SBT_1S) / sc->et.et_frequency;
290	sc->et.et_start = aml8726_timer_start;
291	sc->et.et_stop = aml8726_timer_stop;
292	sc->et.et_priv = sc;
293
294	et_register(&sc->et);
295
296	sc->tc.tc_get_timecount = aml8726_get_timecount;
297	sc->tc.tc_name = "aml8726 timer E";
298	sc->tc.tc_frequency = 1000000;
299	sc->tc.tc_counter_mask = ~0u;
300	sc->tc.tc_quality = 1000;
301	sc->tc.tc_priv = sc;
302
303	tc_init(&sc->tc);
304
305	return (0);
306}
307
308static int
309aml8726_timer_detach(device_t dev)
310{
311
312	return (EBUSY);
313}
314
315static device_method_t aml8726_timer_methods[] = {
316	/* Device interface */
317	DEVMETHOD(device_probe,		aml8726_timer_probe),
318	DEVMETHOD(device_attach,	aml8726_timer_attach),
319	DEVMETHOD(device_detach,	aml8726_timer_detach),
320
321	DEVMETHOD_END
322};
323
324static driver_t aml8726_timer_driver = {
325	"timer",
326	aml8726_timer_methods,
327	sizeof(struct aml8726_timer_softc),
328};
329
330static devclass_t aml8726_timer_devclass;
331
332EARLY_DRIVER_MODULE(timer, simplebus, aml8726_timer_driver,
333    aml8726_timer_devclass, 0, 0, BUS_PASS_TIMER);
334
335void
336DELAY(int usec)
337{
338	uint32_t counter;
339	uint32_t delta, now, previous, remaining;
340
341	/* Timer has not yet been initialized */
342	if (aml8726_timer_sc == NULL) {
343		for (; usec > 0; usec--)
344			for (counter = 200; counter > 0; counter--) {
345				/* Prevent gcc from optimizing out the loop */
346				cpufunc_nullop();
347			}
348		return;
349	}
350	TSENTER();
351
352	/*
353	 * Some of the other timers in the source tree do this calculation as:
354	 *
355	 *   usec * ((sc->tc.tc_frequency / 1000000) + 1)
356	 *
357	 * which gives a fairly pessimistic result when tc_frequency is an exact
358	 * multiple of 1000000.  Given the data type and typical values for
359	 * tc_frequency adding 999999 shouldn't overflow.
360	 */
361	remaining = usec * ((aml8726_timer_sc->tc.tc_frequency + 999999) /
362	    1000000);
363
364	/*
365	 * We add one since the first iteration may catch the counter just
366	 * as it is changing.
367	 */
368	remaining += 1;
369
370	previous = aml8726_get_timecount(&aml8726_timer_sc->tc);
371
372	for ( ; ; ) {
373		now = aml8726_get_timecount(&aml8726_timer_sc->tc);
374
375		/*
376		 * If the timer has rolled over, then we have the case:
377		 *
378		 *   if (previous > now) {
379		 *     delta = (0 - previous) + now
380		 *   }
381		 *
382		 * which is really no different then the normal case.
383		 * Both cases are simply:
384		 *
385		 *   delta = now - previous.
386		 */
387		delta = now - previous;
388
389		if (delta >= remaining)
390			break;
391
392		previous = now;
393		remaining -= delta;
394	}
395	TSEXIT();
396}
397