1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * Copyright (c) 2013 Alexander Fedorov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD$"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/kernel.h> 37#include <sys/lock.h> 38#include <sys/malloc.h> 39#include <sys/module.h> 40#include <sys/mutex.h> 41#include <sys/resource.h> 42#include <sys/rman.h> 43#include <sys/sysctl.h> 44#include <sys/queue.h> 45#include <sys/taskqueue.h> 46 47#include <machine/bus.h> 48 49#include <dev/ofw/ofw_bus.h> 50#include <dev/ofw/ofw_bus_subr.h> 51 52#include <dev/mmc/bridge.h> 53#include <dev/mmc/mmcbrvar.h> 54#include <dev/mmc/mmc_fdt_helpers.h> 55 56#include <arm/allwinner/aw_mmc.h> 57#include <dev/extres/clk/clk.h> 58#include <dev/extres/hwreset/hwreset.h> 59#include <dev/extres/regulator/regulator.h> 60 61#include "opt_mmccam.h" 62 63#ifdef MMCCAM 64#include <cam/cam.h> 65#include <cam/cam_ccb.h> 66#include <cam/cam_debug.h> 67#include <cam/cam_sim.h> 68#include <cam/cam_xpt_sim.h> 69#endif 70 71#define AW_MMC_MEMRES 0 72#define AW_MMC_IRQRES 1 73#define AW_MMC_RESSZ 2 74#define AW_MMC_DMA_SEGS (PAGE_SIZE / sizeof(struct aw_mmc_dma_desc)) 75#define AW_MMC_DMA_DESC_SIZE (sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS) 76#define AW_MMC_DMA_FTRGLEVEL 0x20070008 77 78#define AW_MMC_RESET_RETRY 1000 79 80#define CARD_ID_FREQUENCY 400000 81 82struct aw_mmc_conf { 83 uint32_t dma_xferlen; 84 bool mask_data0; 85 bool can_calibrate; 86 bool new_timing; 87}; 88 89static const struct aw_mmc_conf a10_mmc_conf = { 90 .dma_xferlen = 0x2000, 91}; 92 93static const struct aw_mmc_conf a13_mmc_conf = { 94 .dma_xferlen = 0x10000, 95}; 96 97static const struct aw_mmc_conf a64_mmc_conf = { 98 .dma_xferlen = 0x10000, 99 .mask_data0 = true, 100 .can_calibrate = true, 101 .new_timing = true, 102}; 103 104static const struct aw_mmc_conf a64_emmc_conf = { 105 .dma_xferlen = 0x2000, 106 .can_calibrate = true, 107}; 108 109static struct ofw_compat_data compat_data[] = { 110 {"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf}, 111 {"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf}, 112 {"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf}, 113 {"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf}, 114 {"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf}, 115 {NULL, 0} 116}; 117 118struct aw_mmc_softc { 119 device_t aw_dev; 120 clk_t aw_clk_ahb; 121 clk_t aw_clk_mmc; 122 hwreset_t aw_rst_ahb; 123 int aw_bus_busy; 124 int aw_resid; 125 int aw_timeout; 126 struct callout aw_timeoutc; 127 struct mmc_host aw_host; 128 struct mmc_fdt_helper mmc_helper; 129#ifdef MMCCAM 130 union ccb * ccb; 131 struct cam_devq * devq; 132 struct cam_sim * sim; 133 struct mtx sim_mtx; 134#else 135 struct mmc_request * aw_req; 136#endif 137 struct mtx aw_mtx; 138 struct resource * aw_res[AW_MMC_RESSZ]; 139 struct aw_mmc_conf * aw_mmc_conf; 140 uint32_t aw_intr; 141 uint32_t aw_intr_wait; 142 void * aw_intrhand; 143 unsigned int aw_clock; 144 device_t child; 145 146 /* Fields required for DMA access. */ 147 bus_addr_t aw_dma_desc_phys; 148 bus_dmamap_t aw_dma_map; 149 bus_dma_tag_t aw_dma_tag; 150 void * aw_dma_desc; 151 bus_dmamap_t aw_dma_buf_map; 152 bus_dma_tag_t aw_dma_buf_tag; 153 int aw_dma_map_err; 154}; 155 156static struct resource_spec aw_mmc_res_spec[] = { 157 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 158 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 159 { -1, 0, 0 } 160}; 161 162static int aw_mmc_probe(device_t); 163static int aw_mmc_attach(device_t); 164static int aw_mmc_detach(device_t); 165static int aw_mmc_setup_dma(struct aw_mmc_softc *); 166static void aw_mmc_teardown_dma(struct aw_mmc_softc *sc); 167static int aw_mmc_reset(struct aw_mmc_softc *); 168static int aw_mmc_init(struct aw_mmc_softc *); 169static void aw_mmc_intr(void *); 170static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t); 171static void aw_mmc_helper_cd_handler(device_t, bool); 172 173static void aw_mmc_print_error(uint32_t); 174static int aw_mmc_update_ios(device_t, device_t); 175static int aw_mmc_request(device_t, device_t, struct mmc_request *); 176static int aw_mmc_get_ro(device_t, device_t); 177static int aw_mmc_acquire_host(device_t, device_t); 178static int aw_mmc_release_host(device_t, device_t); 179#ifdef MMCCAM 180static void aw_mmc_cam_action(struct cam_sim *, union ccb *); 181static void aw_mmc_cam_poll(struct cam_sim *); 182static int aw_mmc_cam_settran_settings(struct aw_mmc_softc *, union ccb *); 183static int aw_mmc_cam_request(struct aw_mmc_softc *, union ccb *); 184static void aw_mmc_cam_handle_mmcio(struct cam_sim *, union ccb *); 185#endif 186 187#define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx) 188#define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx) 189#define AW_MMC_READ_4(_sc, _reg) \ 190 bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg) 191#define AW_MMC_WRITE_4(_sc, _reg, _value) \ 192 bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value) 193 194#ifdef MMCCAM 195static void 196aw_mmc_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) 197{ 198 struct aw_mmc_softc *sc; 199 200 sc = cam_sim_softc(sim); 201 202 aw_mmc_cam_request(sc, ccb); 203} 204 205static void 206aw_mmc_cam_action(struct cam_sim *sim, union ccb *ccb) 207{ 208 struct aw_mmc_softc *sc; 209 210 sc = cam_sim_softc(sim); 211 if (sc == NULL) { 212 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 213 xpt_done(ccb); 214 return; 215 } 216 217 mtx_assert(&sc->sim_mtx, MA_OWNED); 218 219 switch (ccb->ccb_h.func_code) { 220 case XPT_PATH_INQ: 221 { 222 struct ccb_pathinq *cpi; 223 224 cpi = &ccb->cpi; 225 cpi->version_num = 1; 226 cpi->hba_inquiry = 0; 227 cpi->target_sprt = 0; 228 cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN; 229 cpi->hba_eng_cnt = 0; 230 cpi->max_target = 0; 231 cpi->max_lun = 0; 232 cpi->initiator_id = 1; 233 cpi->maxio = (sc->aw_mmc_conf->dma_xferlen * 234 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 235 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 236 strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN); 237 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 238 cpi->unit_number = cam_sim_unit(sim); 239 cpi->bus_id = cam_sim_bus(sim); 240 cpi->protocol = PROTO_MMCSD; 241 cpi->protocol_version = SCSI_REV_0; 242 cpi->transport = XPORT_MMCSD; 243 cpi->transport_version = 1; 244 245 cpi->ccb_h.status = CAM_REQ_CMP; 246 break; 247 } 248 case XPT_GET_TRAN_SETTINGS: 249 { 250 struct ccb_trans_settings *cts = &ccb->cts; 251 252 if (bootverbose) 253 device_printf(sc->aw_dev, "Got XPT_GET_TRAN_SETTINGS\n"); 254 255 cts->protocol = PROTO_MMCSD; 256 cts->protocol_version = 1; 257 cts->transport = XPORT_MMCSD; 258 cts->transport_version = 1; 259 cts->xport_specific.valid = 0; 260 cts->proto_specific.mmc.host_ocr = sc->aw_host.host_ocr; 261 cts->proto_specific.mmc.host_f_min = sc->aw_host.f_min; 262 cts->proto_specific.mmc.host_f_max = sc->aw_host.f_max; 263 cts->proto_specific.mmc.host_caps = sc->aw_host.caps; 264 memcpy(&cts->proto_specific.mmc.ios, &sc->aw_host.ios, sizeof(struct mmc_ios)); 265 ccb->ccb_h.status = CAM_REQ_CMP; 266 break; 267 } 268 case XPT_SET_TRAN_SETTINGS: 269 { 270 if (bootverbose) 271 device_printf(sc->aw_dev, "Got XPT_SET_TRAN_SETTINGS\n"); 272 aw_mmc_cam_settran_settings(sc, ccb); 273 ccb->ccb_h.status = CAM_REQ_CMP; 274 break; 275 } 276 case XPT_RESET_BUS: 277 if (bootverbose) 278 device_printf(sc->aw_dev, "Got XPT_RESET_BUS, ACK it...\n"); 279 ccb->ccb_h.status = CAM_REQ_CMP; 280 break; 281 case XPT_MMC_IO: 282 /* 283 * Here is the HW-dependent part of 284 * sending the command to the underlying h/w 285 * At some point in the future an interrupt comes. 286 * Then the request will be marked as completed. 287 */ 288 ccb->ccb_h.status = CAM_REQ_INPROG; 289 290 aw_mmc_cam_handle_mmcio(sim, ccb); 291 return; 292 /* NOTREACHED */ 293 break; 294 default: 295 ccb->ccb_h.status = CAM_REQ_INVALID; 296 break; 297 } 298 xpt_done(ccb); 299 return; 300} 301 302static void 303aw_mmc_cam_poll(struct cam_sim *sim) 304{ 305 return; 306} 307 308static int 309aw_mmc_cam_settran_settings(struct aw_mmc_softc *sc, union ccb *ccb) 310{ 311 struct mmc_ios *ios; 312 struct mmc_ios *new_ios; 313 struct ccb_trans_settings_mmc *cts; 314 315 ios = &sc->aw_host.ios; 316 317 cts = &ccb->cts.proto_specific.mmc; 318 new_ios = &cts->ios; 319 320 /* Update only requested fields */ 321 if (cts->ios_valid & MMC_CLK) { 322 ios->clock = new_ios->clock; 323 device_printf(sc->aw_dev, "Clock => %d\n", ios->clock); 324 } 325 if (cts->ios_valid & MMC_VDD) { 326 ios->vdd = new_ios->vdd; 327 device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd); 328 } 329 if (cts->ios_valid & MMC_CS) { 330 ios->chip_select = new_ios->chip_select; 331 device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select); 332 } 333 if (cts->ios_valid & MMC_BW) { 334 ios->bus_width = new_ios->bus_width; 335 device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width); 336 } 337 if (cts->ios_valid & MMC_PM) { 338 ios->power_mode = new_ios->power_mode; 339 device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode); 340 } 341 if (cts->ios_valid & MMC_BT) { 342 ios->timing = new_ios->timing; 343 device_printf(sc->aw_dev, "Timing => %d\n", ios->timing); 344 } 345 if (cts->ios_valid & MMC_BM) { 346 ios->bus_mode = new_ios->bus_mode; 347 device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode); 348 } 349 350 return (aw_mmc_update_ios(sc->aw_dev, NULL)); 351} 352 353static int 354aw_mmc_cam_request(struct aw_mmc_softc *sc, union ccb *ccb) 355{ 356 struct ccb_mmcio *mmcio; 357 358 mmcio = &ccb->mmcio; 359 360 AW_MMC_LOCK(sc); 361 362#ifdef DEBUG 363 if (__predict_false(bootverbose)) { 364 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 365 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 366 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 367 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 368 } 369#endif 370 if (mmcio->cmd.data != NULL) { 371 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 372 panic("data->len = %d, data->flags = %d -- something is b0rked", 373 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 374 } 375 if (sc->ccb != NULL) { 376 device_printf(sc->aw_dev, "Controller still has an active command\n"); 377 return (EBUSY); 378 } 379 sc->ccb = ccb; 380 /* aw_mmc_request locks again */ 381 AW_MMC_UNLOCK(sc); 382 aw_mmc_request(sc->aw_dev, NULL, NULL); 383 384 return (0); 385} 386#endif /* MMCCAM */ 387 388static void 389aw_mmc_helper_cd_handler(device_t dev, bool present) 390{ 391 struct aw_mmc_softc *sc; 392 393 sc = device_get_softc(dev); 394 AW_MMC_LOCK(sc); 395 if (present) { 396 if (sc->child == NULL) { 397 if (bootverbose) 398 device_printf(sc->aw_dev, "Card inserted\n"); 399 400 sc->child = device_add_child(sc->aw_dev, "mmc", -1); 401 AW_MMC_UNLOCK(sc); 402 if (sc->child) { 403 device_set_ivars(sc->child, sc); 404 (void)device_probe_and_attach(sc->child); 405 } 406 } else 407 AW_MMC_UNLOCK(sc); 408 } else { 409 /* Card isn't present, detach if necessary */ 410 if (sc->child != NULL) { 411 if (bootverbose) 412 device_printf(sc->aw_dev, "Card removed\n"); 413 414 AW_MMC_UNLOCK(sc); 415 device_delete_child(sc->aw_dev, sc->child); 416 sc->child = NULL; 417 } else 418 AW_MMC_UNLOCK(sc); 419 } 420} 421 422static int 423aw_mmc_probe(device_t dev) 424{ 425 426 if (!ofw_bus_status_okay(dev)) 427 return (ENXIO); 428 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 429 return (ENXIO); 430 431 device_set_desc(dev, "Allwinner Integrated MMC/SD controller"); 432 433 return (BUS_PROBE_DEFAULT); 434} 435 436static int 437aw_mmc_attach(device_t dev) 438{ 439 struct aw_mmc_softc *sc; 440 struct sysctl_ctx_list *ctx; 441 struct sysctl_oid_list *tree; 442 int error; 443 444 sc = device_get_softc(dev); 445 sc->aw_dev = dev; 446 447 sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 448 449#ifndef MMCCAM 450 sc->aw_req = NULL; 451#endif 452 if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) { 453 device_printf(dev, "cannot allocate device resources\n"); 454 return (ENXIO); 455 } 456 if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES], 457 INTR_TYPE_NET | INTR_MPSAFE, NULL, aw_mmc_intr, sc, 458 &sc->aw_intrhand)) { 459 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 460 device_printf(dev, "cannot setup interrupt handler\n"); 461 return (ENXIO); 462 } 463 mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc", 464 MTX_DEF); 465 callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0); 466 467 /* De-assert reset */ 468 if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) { 469 error = hwreset_deassert(sc->aw_rst_ahb); 470 if (error != 0) { 471 device_printf(dev, "cannot de-assert reset\n"); 472 goto fail; 473 } 474 } 475 476 /* Activate the module clock. */ 477 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb); 478 if (error != 0) { 479 device_printf(dev, "cannot get ahb clock\n"); 480 goto fail; 481 } 482 error = clk_enable(sc->aw_clk_ahb); 483 if (error != 0) { 484 device_printf(dev, "cannot enable ahb clock\n"); 485 goto fail; 486 } 487 error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc); 488 if (error != 0) { 489 device_printf(dev, "cannot get mmc clock\n"); 490 goto fail; 491 } 492 error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY, 493 CLK_SET_ROUND_DOWN); 494 if (error != 0) { 495 device_printf(dev, "cannot init mmc clock\n"); 496 goto fail; 497 } 498 error = clk_enable(sc->aw_clk_mmc); 499 if (error != 0) { 500 device_printf(dev, "cannot enable mmc clock\n"); 501 goto fail; 502 } 503 504 sc->aw_timeout = 10; 505 ctx = device_get_sysctl_ctx(dev); 506 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 507 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW, 508 &sc->aw_timeout, 0, "Request timeout in seconds"); 509 510 /* Soft Reset controller. */ 511 if (aw_mmc_reset(sc) != 0) { 512 device_printf(dev, "cannot reset the controller\n"); 513 goto fail; 514 } 515 516 if (aw_mmc_setup_dma(sc) != 0) { 517 device_printf(sc->aw_dev, "Couldn't setup DMA!\n"); 518 goto fail; 519 } 520 521 /* Set some defaults for freq and supported mode */ 522 sc->aw_host.f_min = 400000; 523 sc->aw_host.f_max = 52000000; 524 sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 525 sc->aw_host.caps |= MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330; 526 mmc_fdt_parse(dev, 0, &sc->mmc_helper, &sc->aw_host); 527 mmc_fdt_gpio_setup(dev, 0, &sc->mmc_helper, aw_mmc_helper_cd_handler); 528 529#ifdef MMCCAM 530 sc->ccb = NULL; 531 if ((sc->devq = cam_simq_alloc(1)) == NULL) { 532 goto fail; 533 } 534 535 mtx_init(&sc->sim_mtx, "awmmcsim", NULL, MTX_DEF); 536 sc->sim = cam_sim_alloc(aw_mmc_cam_action, aw_mmc_cam_poll, 537 "aw_mmc_sim", sc, device_get_unit(dev), 538 &sc->sim_mtx, 1, 1, sc->devq); 539 540 if (sc->sim == NULL) { 541 cam_simq_free(sc->devq); 542 device_printf(dev, "cannot allocate CAM SIM\n"); 543 goto fail; 544 } 545 546 mtx_lock(&sc->sim_mtx); 547 if (xpt_bus_register(sc->sim, sc->aw_dev, 0) != 0) { 548 device_printf(dev, "cannot register SCSI pass-through bus\n"); 549 cam_sim_free(sc->sim, FALSE); 550 cam_simq_free(sc->devq); 551 mtx_unlock(&sc->sim_mtx); 552 goto fail; 553 } 554 555 mtx_unlock(&sc->sim_mtx); 556#endif /* MMCCAM */ 557 558 return (0); 559 560fail: 561 callout_drain(&sc->aw_timeoutc); 562 mtx_destroy(&sc->aw_mtx); 563 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 564 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 565 566#ifdef MMCCAM 567 if (sc->sim != NULL) { 568 mtx_lock(&sc->sim_mtx); 569 xpt_bus_deregister(cam_sim_path(sc->sim)); 570 cam_sim_free(sc->sim, FALSE); 571 mtx_unlock(&sc->sim_mtx); 572 } 573 574 if (sc->devq != NULL) 575 cam_simq_free(sc->devq); 576#endif 577 return (ENXIO); 578} 579 580static int 581aw_mmc_detach(device_t dev) 582{ 583 struct aw_mmc_softc *sc; 584 device_t d; 585 586 sc = device_get_softc(dev); 587 588 clk_disable(sc->aw_clk_mmc); 589 clk_disable(sc->aw_clk_ahb); 590 hwreset_assert(sc->aw_rst_ahb); 591 592 mmc_fdt_gpio_teardown(&sc->mmc_helper); 593 594 callout_drain(&sc->aw_timeoutc); 595 596 AW_MMC_LOCK(sc); 597 d = sc->child; 598 sc->child = NULL; 599 AW_MMC_UNLOCK(sc); 600 if (d != NULL) 601 device_delete_child(sc->aw_dev, d); 602 603 aw_mmc_teardown_dma(sc); 604 605 mtx_destroy(&sc->aw_mtx); 606 607 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 608 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 609 610#ifdef MMCCAM 611 if (sc->sim != NULL) { 612 mtx_lock(&sc->sim_mtx); 613 xpt_bus_deregister(cam_sim_path(sc->sim)); 614 cam_sim_free(sc->sim, FALSE); 615 mtx_unlock(&sc->sim_mtx); 616 } 617 618 if (sc->devq != NULL) 619 cam_simq_free(sc->devq); 620#endif 621 622 return (0); 623} 624 625static void 626aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 627{ 628 struct aw_mmc_softc *sc; 629 630 sc = (struct aw_mmc_softc *)arg; 631 if (err) { 632 sc->aw_dma_map_err = err; 633 return; 634 } 635 sc->aw_dma_desc_phys = segs[0].ds_addr; 636} 637 638static int 639aw_mmc_setup_dma(struct aw_mmc_softc *sc) 640{ 641 int error; 642 643 /* Allocate the DMA descriptor memory. */ 644 error = bus_dma_tag_create( 645 bus_get_dma_tag(sc->aw_dev), /* parent */ 646 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 647 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 648 BUS_SPACE_MAXADDR, /* highaddr */ 649 NULL, NULL, /* filter, filterarg*/ 650 AW_MMC_DMA_DESC_SIZE, 1, /* maxsize, nsegment */ 651 AW_MMC_DMA_DESC_SIZE, /* maxsegsize */ 652 0, /* flags */ 653 NULL, NULL, /* lock, lockarg*/ 654 &sc->aw_dma_tag); 655 if (error) 656 return (error); 657 658 error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc, 659 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 660 &sc->aw_dma_map); 661 if (error) 662 return (error); 663 664 error = bus_dmamap_load(sc->aw_dma_tag, 665 sc->aw_dma_map, 666 sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE, 667 aw_dma_desc_cb, sc, 0); 668 if (error) 669 return (error); 670 if (sc->aw_dma_map_err) 671 return (sc->aw_dma_map_err); 672 673 /* Create the DMA map for data transfers. */ 674 error = bus_dma_tag_create( 675 bus_get_dma_tag(sc->aw_dev), /* parent */ 676 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 677 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 678 BUS_SPACE_MAXADDR, /* highaddr */ 679 NULL, NULL, /* filter, filterarg*/ 680 sc->aw_mmc_conf->dma_xferlen * 681 AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS, /* maxsize, nsegments */ 682 sc->aw_mmc_conf->dma_xferlen, /* maxsegsize */ 683 BUS_DMA_ALLOCNOW, /* flags */ 684 NULL, NULL, /* lock, lockarg*/ 685 &sc->aw_dma_buf_tag); 686 if (error) 687 return (error); 688 error = bus_dmamap_create(sc->aw_dma_buf_tag, 0, 689 &sc->aw_dma_buf_map); 690 if (error) 691 return (error); 692 693 return (0); 694} 695 696static void 697aw_mmc_teardown_dma(struct aw_mmc_softc *sc) 698{ 699 700 bus_dmamap_unload(sc->aw_dma_tag, sc->aw_dma_map); 701 bus_dmamem_free(sc->aw_dma_tag, sc->aw_dma_desc, sc->aw_dma_map); 702 if (bus_dma_tag_destroy(sc->aw_dma_tag) != 0) 703 device_printf(sc->aw_dev, "Cannot destroy the dma tag\n"); 704 705 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 706 bus_dmamap_destroy(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 707 if (bus_dma_tag_destroy(sc->aw_dma_buf_tag) != 0) 708 device_printf(sc->aw_dev, "Cannot destroy the dma buf tag\n"); 709} 710 711static void 712aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 713{ 714 int i; 715 struct aw_mmc_dma_desc *dma_desc; 716 struct aw_mmc_softc *sc; 717 718 sc = (struct aw_mmc_softc *)arg; 719 sc->aw_dma_map_err = err; 720 721 if (err) 722 return; 723 724 dma_desc = sc->aw_dma_desc; 725 for (i = 0; i < nsegs; i++) { 726 if (segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen) 727 dma_desc[i].buf_size = 0; /* Size of 0 indicate max len */ 728 else 729 dma_desc[i].buf_size = segs[i].ds_len; 730 dma_desc[i].buf_addr = segs[i].ds_addr; 731 dma_desc[i].config = AW_MMC_DMA_CONFIG_CH | 732 AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC; 733 734 dma_desc[i].next = sc->aw_dma_desc_phys + 735 ((i + 1) * sizeof(struct aw_mmc_dma_desc)); 736 } 737 738 dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD; 739 dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD | 740 AW_MMC_DMA_CONFIG_ER; 741 dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC; 742 dma_desc[nsegs - 1].next = 0; 743} 744 745static int 746aw_mmc_prepare_dma(struct aw_mmc_softc *sc) 747{ 748 bus_dmasync_op_t sync_op; 749 int error; 750 struct mmc_command *cmd; 751 uint32_t val; 752 753#ifdef MMCCAM 754 cmd = &sc->ccb->mmcio.cmd; 755#else 756 cmd = sc->aw_req->cmd; 757#endif 758 if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS)) 759 return (EFBIG); 760 error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 761 cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0); 762 if (error) 763 return (error); 764 if (sc->aw_dma_map_err) 765 return (sc->aw_dma_map_err); 766 767 if (cmd->data->flags & MMC_DATA_WRITE) 768 sync_op = BUS_DMASYNC_PREWRITE; 769 else 770 sync_op = BUS_DMASYNC_PREREAD; 771 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op); 772 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE); 773 774 /* Enable DMA */ 775 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 776 val &= ~AW_MMC_GCTL_FIFO_AC_MOD; 777 val |= AW_MMC_GCTL_DMA_ENB; 778 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 779 780 /* Reset DMA */ 781 val |= AW_MMC_GCTL_DMA_RST; 782 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 783 784 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST); 785 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, 786 AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST); 787 788 /* Enable RX or TX DMA interrupt */ 789 val = AW_MMC_READ_4(sc, AW_MMC_IDIE); 790 if (cmd->data->flags & MMC_DATA_WRITE) 791 val |= AW_MMC_IDST_TX_INT; 792 else 793 val |= AW_MMC_IDST_RX_INT; 794 AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val); 795 796 /* Set DMA descritptor list address */ 797 AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys); 798 799 /* FIFO trigger level */ 800 AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL); 801 802 return (0); 803} 804 805static int 806aw_mmc_reset(struct aw_mmc_softc *sc) 807{ 808 uint32_t reg; 809 int timeout; 810 811 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 812 reg |= AW_MMC_GCTL_RESET; 813 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 814 timeout = AW_MMC_RESET_RETRY; 815 while (--timeout > 0) { 816 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0) 817 break; 818 DELAY(100); 819 } 820 if (timeout == 0) 821 return (ETIMEDOUT); 822 823 return (0); 824} 825 826static int 827aw_mmc_init(struct aw_mmc_softc *sc) 828{ 829 uint32_t reg; 830 int ret; 831 832 ret = aw_mmc_reset(sc); 833 if (ret != 0) 834 return (ret); 835 836 /* Set the timeout. */ 837 AW_MMC_WRITE_4(sc, AW_MMC_TMOR, 838 AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) | 839 AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK)); 840 841 /* Unmask interrupts. */ 842 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0); 843 844 /* Clear pending interrupts. */ 845 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 846 847 /* Debug register, undocumented */ 848 AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb); 849 850 /* Function select register */ 851 AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000); 852 853 AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff); 854 855 /* Enable interrupts and disable AHB access. */ 856 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 857 reg |= AW_MMC_GCTL_INT_ENB; 858 reg &= ~AW_MMC_GCTL_FIFO_AC_MOD; 859 reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS; 860 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 861 862 return (0); 863} 864 865static void 866aw_mmc_req_done(struct aw_mmc_softc *sc) 867{ 868 struct mmc_command *cmd; 869#ifdef MMCCAM 870 union ccb *ccb; 871#else 872 struct mmc_request *req; 873#endif 874 uint32_t val, mask; 875 int retry; 876 877#ifdef MMCCAM 878 ccb = sc->ccb; 879 cmd = &ccb->mmcio.cmd; 880#else 881 cmd = sc->aw_req->cmd; 882#endif 883#ifdef DEBUG 884 if (bootverbose) { 885 device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error); 886 } 887#endif 888 if (cmd->error != MMC_ERR_NONE) { 889 /* Reset the FIFO and DMA engines. */ 890 mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST; 891 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 892 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask); 893 894 retry = AW_MMC_RESET_RETRY; 895 while (--retry > 0) { 896 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & 897 AW_MMC_GCTL_RESET) == 0) 898 break; 899 DELAY(100); 900 } 901 if (retry == 0) 902 device_printf(sc->aw_dev, 903 "timeout resetting DMA/FIFO\n"); 904 aw_mmc_update_clock(sc, 1); 905 } 906 907 callout_stop(&sc->aw_timeoutc); 908 sc->aw_intr = 0; 909 sc->aw_resid = 0; 910 sc->aw_dma_map_err = 0; 911 sc->aw_intr_wait = 0; 912#ifdef MMCCAM 913 sc->ccb = NULL; 914 ccb->ccb_h.status = 915 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 916 xpt_done(ccb); 917#else 918 req = sc->aw_req; 919 sc->aw_req = NULL; 920 req->done(req); 921#endif 922} 923 924static void 925aw_mmc_req_ok(struct aw_mmc_softc *sc) 926{ 927 int timeout; 928 struct mmc_command *cmd; 929 uint32_t status; 930 931 timeout = 1000; 932 while (--timeout > 0) { 933 status = AW_MMC_READ_4(sc, AW_MMC_STAR); 934 if ((status & AW_MMC_STAR_CARD_BUSY) == 0) 935 break; 936 DELAY(1000); 937 } 938#ifdef MMCCAM 939 cmd = &sc->ccb->mmcio.cmd; 940#else 941 cmd = sc->aw_req->cmd; 942#endif 943 if (timeout == 0) { 944 cmd->error = MMC_ERR_FAILED; 945 aw_mmc_req_done(sc); 946 return; 947 } 948 if (cmd->flags & MMC_RSP_PRESENT) { 949 if (cmd->flags & MMC_RSP_136) { 950 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3); 951 cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2); 952 cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1); 953 cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 954 } else 955 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 956 } 957 /* All data has been transferred ? */ 958 if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len) 959 cmd->error = MMC_ERR_FAILED; 960 aw_mmc_req_done(sc); 961} 962 963 964static inline void 965set_mmc_error(struct aw_mmc_softc *sc, int error_code) 966{ 967#ifdef MMCCAM 968 sc->ccb->mmcio.cmd.error = error_code; 969#else 970 sc->aw_req->cmd->error = error_code; 971#endif 972} 973 974static void 975aw_mmc_timeout(void *arg) 976{ 977 struct aw_mmc_softc *sc; 978 979 sc = (struct aw_mmc_softc *)arg; 980#ifdef MMCCAM 981 if (sc->ccb != NULL) { 982#else 983 if (sc->aw_req != NULL) { 984#endif 985 device_printf(sc->aw_dev, "controller timeout\n"); 986 set_mmc_error(sc, MMC_ERR_TIMEOUT); 987 aw_mmc_req_done(sc); 988 } else 989 device_printf(sc->aw_dev, 990 "Spurious timeout - no active request\n"); 991} 992 993static void 994aw_mmc_print_error(uint32_t err) 995{ 996 if(err & AW_MMC_INT_RESP_ERR) 997 printf("AW_MMC_INT_RESP_ERR "); 998 if (err & AW_MMC_INT_RESP_CRC_ERR) 999 printf("AW_MMC_INT_RESP_CRC_ERR "); 1000 if (err & AW_MMC_INT_DATA_CRC_ERR) 1001 printf("AW_MMC_INT_DATA_CRC_ERR "); 1002 if (err & AW_MMC_INT_RESP_TIMEOUT) 1003 printf("AW_MMC_INT_RESP_TIMEOUT "); 1004 if (err & AW_MMC_INT_FIFO_RUN_ERR) 1005 printf("AW_MMC_INT_FIFO_RUN_ERR "); 1006 if (err & AW_MMC_INT_CMD_BUSY) 1007 printf("AW_MMC_INT_CMD_BUSY "); 1008 if (err & AW_MMC_INT_DATA_START_ERR) 1009 printf("AW_MMC_INT_DATA_START_ERR "); 1010 if (err & AW_MMC_INT_DATA_END_BIT_ERR) 1011 printf("AW_MMC_INT_DATA_END_BIT_ERR"); 1012 printf("\n"); 1013} 1014 1015static void 1016aw_mmc_intr(void *arg) 1017{ 1018 bus_dmasync_op_t sync_op; 1019 struct aw_mmc_softc *sc; 1020 struct mmc_data *data; 1021 uint32_t idst, imask, rint; 1022 1023 sc = (struct aw_mmc_softc *)arg; 1024 AW_MMC_LOCK(sc); 1025 rint = AW_MMC_READ_4(sc, AW_MMC_RISR); 1026 idst = AW_MMC_READ_4(sc, AW_MMC_IDST); 1027 imask = AW_MMC_READ_4(sc, AW_MMC_IMKR); 1028 if (idst == 0 && imask == 0 && rint == 0) { 1029 AW_MMC_UNLOCK(sc); 1030 return; 1031 } 1032#ifdef DEBUG 1033 device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n", 1034 idst, imask, rint); 1035#endif 1036#ifdef MMCCAM 1037 if (sc->ccb == NULL) { 1038#else 1039 if (sc->aw_req == NULL) { 1040#endif 1041 device_printf(sc->aw_dev, 1042 "Spurious interrupt - no active request, rint: 0x%08X\n", 1043 rint); 1044 aw_mmc_print_error(rint); 1045 goto end; 1046 } 1047 if (rint & AW_MMC_INT_ERR_BIT) { 1048 if (bootverbose) 1049 device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint); 1050 aw_mmc_print_error(rint); 1051 if (rint & AW_MMC_INT_RESP_TIMEOUT) 1052 set_mmc_error(sc, MMC_ERR_TIMEOUT); 1053 else 1054 set_mmc_error(sc, MMC_ERR_FAILED); 1055 aw_mmc_req_done(sc); 1056 goto end; 1057 } 1058 if (idst & AW_MMC_IDST_ERROR) { 1059 device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst); 1060 set_mmc_error(sc, MMC_ERR_FAILED); 1061 aw_mmc_req_done(sc); 1062 goto end; 1063 } 1064 1065 sc->aw_intr |= rint; 1066#ifdef MMCCAM 1067 data = sc->ccb->mmcio.cmd.data; 1068#else 1069 data = sc->aw_req->cmd->data; 1070#endif 1071 if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) { 1072 if (data->flags & MMC_DATA_WRITE) 1073 sync_op = BUS_DMASYNC_POSTWRITE; 1074 else 1075 sync_op = BUS_DMASYNC_POSTREAD; 1076 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 1077 sync_op); 1078 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, 1079 BUS_DMASYNC_POSTWRITE); 1080 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 1081 sc->aw_resid = data->len >> 2; 1082 } 1083 if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait) 1084 aw_mmc_req_ok(sc); 1085 1086end: 1087 AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst); 1088 AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint); 1089 AW_MMC_UNLOCK(sc); 1090} 1091 1092static int 1093aw_mmc_request(device_t bus, device_t child, struct mmc_request *req) 1094{ 1095 int blksz; 1096 struct aw_mmc_softc *sc; 1097 struct mmc_command *cmd; 1098 uint32_t cmdreg, imask; 1099 int err; 1100 1101 sc = device_get_softc(bus); 1102 1103 AW_MMC_LOCK(sc); 1104#ifdef MMCCAM 1105 KASSERT(req == NULL, ("req should be NULL in MMCCAM case!")); 1106 /* 1107 * For MMCCAM, sc->ccb has been NULL-checked and populated 1108 * by aw_mmc_cam_request() already. 1109 */ 1110 cmd = &sc->ccb->mmcio.cmd; 1111#else 1112 if (sc->aw_req) { 1113 AW_MMC_UNLOCK(sc); 1114 return (EBUSY); 1115 } 1116 sc->aw_req = req; 1117 cmd = req->cmd; 1118 1119#ifdef DEBUG 1120 if (bootverbose) 1121 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1122 cmd->opcode, cmd->arg, cmd->flags, 1123 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 1124 cmd->data != NULL ? cmd->data->flags: 0); 1125#endif 1126#endif 1127 cmdreg = AW_MMC_CMDR_LOAD; 1128 imask = AW_MMC_INT_ERR_BIT; 1129 sc->aw_intr_wait = 0; 1130 sc->aw_intr = 0; 1131 sc->aw_resid = 0; 1132 cmd->error = MMC_ERR_NONE; 1133 1134 if (cmd->opcode == MMC_GO_IDLE_STATE) 1135 cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ; 1136 1137 if (cmd->flags & MMC_RSP_PRESENT) 1138 cmdreg |= AW_MMC_CMDR_RESP_RCV; 1139 if (cmd->flags & MMC_RSP_136) 1140 cmdreg |= AW_MMC_CMDR_LONG_RESP; 1141 if (cmd->flags & MMC_RSP_CRC) 1142 cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC; 1143 1144 if (cmd->data) { 1145 cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER; 1146 1147 if (cmd->data->flags & MMC_DATA_MULTI) { 1148 cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG; 1149 imask |= AW_MMC_INT_AUTO_STOP_DONE; 1150 sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE; 1151 } else { 1152 sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER; 1153 imask |= AW_MMC_INT_DATA_OVER; 1154 } 1155 if (cmd->data->flags & MMC_DATA_WRITE) 1156 cmdreg |= AW_MMC_CMDR_DIR_WRITE; 1157 1158 blksz = min(cmd->data->len, MMC_SECTOR_SIZE); 1159 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz); 1160 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1161 } else { 1162 imask |= AW_MMC_INT_CMD_DONE; 1163 } 1164 1165 /* Enable the interrupts we are interested in */ 1166 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask); 1167 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1168 1169 /* Enable auto stop if needed */ 1170 AW_MMC_WRITE_4(sc, AW_MMC_A12A, 1171 cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff); 1172 1173 /* Write the command argument */ 1174 AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg); 1175 1176 /* 1177 * If we don't have data start the request 1178 * if we do prepare the dma request and start the request 1179 */ 1180 if (cmd->data == NULL) { 1181 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1182 } else { 1183 err = aw_mmc_prepare_dma(sc); 1184 if (err != 0) 1185 device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err); 1186 1187 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1188 } 1189 1190 callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz, 1191 aw_mmc_timeout, sc); 1192 AW_MMC_UNLOCK(sc); 1193 1194 return (0); 1195} 1196 1197static int 1198aw_mmc_read_ivar(device_t bus, device_t child, int which, 1199 uintptr_t *result) 1200{ 1201 struct aw_mmc_softc *sc; 1202 1203 sc = device_get_softc(bus); 1204 switch (which) { 1205 default: 1206 return (EINVAL); 1207 case MMCBR_IVAR_BUS_MODE: 1208 *(int *)result = sc->aw_host.ios.bus_mode; 1209 break; 1210 case MMCBR_IVAR_BUS_WIDTH: 1211 *(int *)result = sc->aw_host.ios.bus_width; 1212 break; 1213 case MMCBR_IVAR_CHIP_SELECT: 1214 *(int *)result = sc->aw_host.ios.chip_select; 1215 break; 1216 case MMCBR_IVAR_CLOCK: 1217 *(int *)result = sc->aw_host.ios.clock; 1218 break; 1219 case MMCBR_IVAR_F_MIN: 1220 *(int *)result = sc->aw_host.f_min; 1221 break; 1222 case MMCBR_IVAR_F_MAX: 1223 *(int *)result = sc->aw_host.f_max; 1224 break; 1225 case MMCBR_IVAR_HOST_OCR: 1226 *(int *)result = sc->aw_host.host_ocr; 1227 break; 1228 case MMCBR_IVAR_MODE: 1229 *(int *)result = sc->aw_host.mode; 1230 break; 1231 case MMCBR_IVAR_OCR: 1232 *(int *)result = sc->aw_host.ocr; 1233 break; 1234 case MMCBR_IVAR_POWER_MODE: 1235 *(int *)result = sc->aw_host.ios.power_mode; 1236 break; 1237 case MMCBR_IVAR_VDD: 1238 *(int *)result = sc->aw_host.ios.vdd; 1239 break; 1240 case MMCBR_IVAR_VCCQ: 1241 *(int *)result = sc->aw_host.ios.vccq; 1242 break; 1243 case MMCBR_IVAR_CAPS: 1244 *(int *)result = sc->aw_host.caps; 1245 break; 1246 case MMCBR_IVAR_TIMING: 1247 *(int *)result = sc->aw_host.ios.timing; 1248 break; 1249 case MMCBR_IVAR_MAX_DATA: 1250 *(int *)result = (sc->aw_mmc_conf->dma_xferlen * 1251 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 1252 break; 1253 case MMCBR_IVAR_RETUNE_REQ: 1254 *(int *)result = retune_req_none; 1255 break; 1256 } 1257 1258 return (0); 1259} 1260 1261static int 1262aw_mmc_write_ivar(device_t bus, device_t child, int which, 1263 uintptr_t value) 1264{ 1265 struct aw_mmc_softc *sc; 1266 1267 sc = device_get_softc(bus); 1268 switch (which) { 1269 default: 1270 return (EINVAL); 1271 case MMCBR_IVAR_BUS_MODE: 1272 sc->aw_host.ios.bus_mode = value; 1273 break; 1274 case MMCBR_IVAR_BUS_WIDTH: 1275 sc->aw_host.ios.bus_width = value; 1276 break; 1277 case MMCBR_IVAR_CHIP_SELECT: 1278 sc->aw_host.ios.chip_select = value; 1279 break; 1280 case MMCBR_IVAR_CLOCK: 1281 sc->aw_host.ios.clock = value; 1282 break; 1283 case MMCBR_IVAR_MODE: 1284 sc->aw_host.mode = value; 1285 break; 1286 case MMCBR_IVAR_OCR: 1287 sc->aw_host.ocr = value; 1288 break; 1289 case MMCBR_IVAR_POWER_MODE: 1290 sc->aw_host.ios.power_mode = value; 1291 break; 1292 case MMCBR_IVAR_VDD: 1293 sc->aw_host.ios.vdd = value; 1294 break; 1295 case MMCBR_IVAR_VCCQ: 1296 sc->aw_host.ios.vccq = value; 1297 break; 1298 case MMCBR_IVAR_TIMING: 1299 sc->aw_host.ios.timing = value; 1300 break; 1301 /* These are read-only */ 1302 case MMCBR_IVAR_CAPS: 1303 case MMCBR_IVAR_HOST_OCR: 1304 case MMCBR_IVAR_F_MIN: 1305 case MMCBR_IVAR_F_MAX: 1306 case MMCBR_IVAR_MAX_DATA: 1307 return (EINVAL); 1308 } 1309 1310 return (0); 1311} 1312 1313static int 1314aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon) 1315{ 1316 uint32_t reg; 1317 int retry; 1318 1319 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1320 reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER | 1321 AW_MMC_CKCR_MASK_DATA0); 1322 1323 if (clkon) 1324 reg |= AW_MMC_CKCR_ENB; 1325 if (sc->aw_mmc_conf->mask_data0) 1326 reg |= AW_MMC_CKCR_MASK_DATA0; 1327 1328 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1329 1330 reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK | 1331 AW_MMC_CMDR_WAIT_PRE_OVER; 1332 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg); 1333 retry = 0xfffff; 1334 1335 while (reg & AW_MMC_CMDR_LOAD && --retry > 0) { 1336 reg = AW_MMC_READ_4(sc, AW_MMC_CMDR); 1337 DELAY(10); 1338 } 1339 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1340 1341 if (reg & AW_MMC_CMDR_LOAD) { 1342 device_printf(sc->aw_dev, "timeout updating clock\n"); 1343 return (ETIMEDOUT); 1344 } 1345 1346 if (sc->aw_mmc_conf->mask_data0) { 1347 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1348 reg &= ~AW_MMC_CKCR_MASK_DATA0; 1349 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1350 } 1351 1352 return (0); 1353} 1354 1355static int 1356aw_mmc_switch_vccq(device_t bus, device_t child) 1357{ 1358 struct aw_mmc_softc *sc; 1359 int uvolt, err; 1360 1361 sc = device_get_softc(bus); 1362 1363 if (sc->mmc_helper.vqmmc_supply == NULL) 1364 return EOPNOTSUPP; 1365 1366 switch (sc->aw_host.ios.vccq) { 1367 case vccq_180: 1368 uvolt = 1800000; 1369 break; 1370 case vccq_330: 1371 uvolt = 3300000; 1372 break; 1373 default: 1374 return EINVAL; 1375 } 1376 1377 err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, uvolt, uvolt); 1378 if (err != 0) { 1379 device_printf(sc->aw_dev, 1380 "Cannot set vqmmc to %d<->%d\n", 1381 uvolt, 1382 uvolt); 1383 return (err); 1384 } 1385 1386 return (0); 1387} 1388 1389static int 1390aw_mmc_update_ios(device_t bus, device_t child) 1391{ 1392 int error; 1393 struct aw_mmc_softc *sc; 1394 struct mmc_ios *ios; 1395 unsigned int clock; 1396 uint32_t reg, div = 1; 1397 1398 sc = device_get_softc(bus); 1399 1400 ios = &sc->aw_host.ios; 1401 1402 /* Set the bus width. */ 1403 switch (ios->bus_width) { 1404 case bus_width_1: 1405 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1); 1406 break; 1407 case bus_width_4: 1408 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4); 1409 break; 1410 case bus_width_8: 1411 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8); 1412 break; 1413 } 1414 1415 switch (ios->power_mode) { 1416 case power_on: 1417 break; 1418 case power_off: 1419 if (bootverbose) 1420 device_printf(sc->aw_dev, "Powering down sd/mmc\n"); 1421 1422 if (sc->mmc_helper.vmmc_supply) 1423 regulator_disable(sc->mmc_helper.vmmc_supply); 1424 if (sc->mmc_helper.vqmmc_supply) 1425 regulator_disable(sc->mmc_helper.vqmmc_supply); 1426 1427 aw_mmc_reset(sc); 1428 break; 1429 case power_up: 1430 if (bootverbose) 1431 device_printf(sc->aw_dev, "Powering up sd/mmc\n"); 1432 1433 if (sc->mmc_helper.vmmc_supply) 1434 regulator_enable(sc->mmc_helper.vmmc_supply); 1435 if (sc->mmc_helper.vqmmc_supply) 1436 regulator_enable(sc->mmc_helper.vqmmc_supply); 1437 aw_mmc_init(sc); 1438 break; 1439 }; 1440 1441 /* Enable ddr mode if needed */ 1442 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 1443 if (ios->timing == bus_timing_uhs_ddr50 || 1444 ios->timing == bus_timing_mmc_ddr52) 1445 reg |= AW_MMC_GCTL_DDR_MOD_SEL; 1446 else 1447 reg &= ~AW_MMC_GCTL_DDR_MOD_SEL; 1448 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 1449 1450 if (ios->clock && ios->clock != sc->aw_clock) { 1451 sc->aw_clock = clock = ios->clock; 1452 1453 /* Disable clock */ 1454 error = aw_mmc_update_clock(sc, 0); 1455 if (error != 0) 1456 return (error); 1457 1458 if (ios->timing == bus_timing_mmc_ddr52 && 1459 (sc->aw_mmc_conf->new_timing || 1460 ios->bus_width == bus_width_8)) { 1461 div = 2; 1462 clock <<= 1; 1463 } 1464 1465 /* Reset the divider. */ 1466 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1467 reg &= ~AW_MMC_CKCR_DIV; 1468 reg |= div - 1; 1469 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1470 1471 /* New timing mode if needed */ 1472 if (sc->aw_mmc_conf->new_timing) { 1473 reg = AW_MMC_READ_4(sc, AW_MMC_NTSR); 1474 reg |= AW_MMC_NTSR_MODE_SELECT; 1475 AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg); 1476 } 1477 1478 /* Set the MMC clock. */ 1479 error = clk_disable(sc->aw_clk_mmc); 1480 if (error != 0 && bootverbose) 1481 device_printf(sc->aw_dev, 1482 "failed to disable mmc clock: %d\n", error); 1483 error = clk_set_freq(sc->aw_clk_mmc, clock, 1484 CLK_SET_ROUND_DOWN); 1485 if (error != 0) { 1486 device_printf(sc->aw_dev, 1487 "failed to set frequency to %u Hz: %d\n", 1488 clock, error); 1489 return (error); 1490 } 1491 error = clk_enable(sc->aw_clk_mmc); 1492 if (error != 0 && bootverbose) 1493 device_printf(sc->aw_dev, 1494 "failed to re-enable mmc clock: %d\n", error); 1495 1496 if (sc->aw_mmc_conf->can_calibrate) 1497 AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN); 1498 1499 /* Enable clock. */ 1500 error = aw_mmc_update_clock(sc, 1); 1501 if (error != 0) 1502 return (error); 1503 } 1504 1505 1506 return (0); 1507} 1508 1509static int 1510aw_mmc_get_ro(device_t bus, device_t child) 1511{ 1512 struct aw_mmc_softc *sc; 1513 1514 sc = device_get_softc(bus); 1515 1516 return (mmc_fdt_gpio_get_readonly(&sc->mmc_helper)); 1517} 1518 1519static int 1520aw_mmc_acquire_host(device_t bus, device_t child) 1521{ 1522 struct aw_mmc_softc *sc; 1523 int error; 1524 1525 sc = device_get_softc(bus); 1526 AW_MMC_LOCK(sc); 1527 while (sc->aw_bus_busy) { 1528 error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0); 1529 if (error != 0) { 1530 AW_MMC_UNLOCK(sc); 1531 return (error); 1532 } 1533 } 1534 sc->aw_bus_busy++; 1535 AW_MMC_UNLOCK(sc); 1536 1537 return (0); 1538} 1539 1540static int 1541aw_mmc_release_host(device_t bus, device_t child) 1542{ 1543 struct aw_mmc_softc *sc; 1544 1545 sc = device_get_softc(bus); 1546 AW_MMC_LOCK(sc); 1547 sc->aw_bus_busy--; 1548 wakeup(sc); 1549 AW_MMC_UNLOCK(sc); 1550 1551 return (0); 1552} 1553 1554static device_method_t aw_mmc_methods[] = { 1555 /* Device interface */ 1556 DEVMETHOD(device_probe, aw_mmc_probe), 1557 DEVMETHOD(device_attach, aw_mmc_attach), 1558 DEVMETHOD(device_detach, aw_mmc_detach), 1559 1560 /* Bus interface */ 1561 DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar), 1562 DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar), 1563 1564 /* MMC bridge interface */ 1565 DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios), 1566 DEVMETHOD(mmcbr_request, aw_mmc_request), 1567 DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro), 1568 DEVMETHOD(mmcbr_switch_vccq, aw_mmc_switch_vccq), 1569 DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host), 1570 DEVMETHOD(mmcbr_release_host, aw_mmc_release_host), 1571 1572 DEVMETHOD_END 1573}; 1574 1575static devclass_t aw_mmc_devclass; 1576 1577static driver_t aw_mmc_driver = { 1578 "aw_mmc", 1579 aw_mmc_methods, 1580 sizeof(struct aw_mmc_softc), 1581}; 1582 1583DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, aw_mmc_devclass, NULL, 1584 NULL); 1585#ifndef MMCCAM 1586MMC_DECLARE_BRIDGE(aw_mmc); 1587#endif 1588SIMPLEBUS_PNP_INFO(compat_data); 1589