1/*- 2 * Copyright (c) 2014-2016 Jared D. McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29/* 30 * Allwinner A10/A20 and H3 Audio Codec 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD$"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/rman.h> 40#include <sys/condvar.h> 41#include <sys/kernel.h> 42#include <sys/module.h> 43#include <sys/gpio.h> 44 45#include <machine/bus.h> 46 47#include <dev/sound/pcm/sound.h> 48#include <dev/sound/chip.h> 49 50#include <dev/ofw/ofw_bus.h> 51#include <dev/ofw/ofw_bus_subr.h> 52 53#include <dev/gpio/gpiobusvar.h> 54 55#include <dev/extres/clk/clk.h> 56#include <dev/extres/hwreset/hwreset.h> 57 58#include "sunxi_dma_if.h" 59#include "mixer_if.h" 60 61struct a10codec_info; 62 63struct a10codec_config { 64 /* mixer class */ 65 struct kobj_class *mixer_class; 66 67 /* toggle DAC/ADC mute */ 68 void (*mute)(struct a10codec_info *, int, int); 69 70 /* DRQ types */ 71 u_int drqtype_codec; 72 u_int drqtype_sdram; 73 74 /* register map */ 75 bus_size_t DPC, 76 DAC_FIFOC, 77 DAC_FIFOS, 78 DAC_TXDATA, 79 ADC_FIFOC, 80 ADC_FIFOS, 81 ADC_RXDATA, 82 DAC_CNT, 83 ADC_CNT; 84}; 85 86#define TX_TRIG_LEVEL 0xf 87#define RX_TRIG_LEVEL 0x7 88#define DRQ_CLR_CNT 0x3 89 90#define AC_DAC_DPC(_sc) ((_sc)->cfg->DPC) 91#define DAC_DPC_EN_DA 0x80000000 92#define AC_DAC_FIFOC(_sc) ((_sc)->cfg->DAC_FIFOC) 93#define DAC_FIFOC_FS_SHIFT 29 94#define DAC_FIFOC_FS_MASK (7U << DAC_FIFOC_FS_SHIFT) 95#define DAC_FS_48KHZ 0 96#define DAC_FS_32KHZ 1 97#define DAC_FS_24KHZ 2 98#define DAC_FS_16KHZ 3 99#define DAC_FS_12KHZ 4 100#define DAC_FS_8KHZ 5 101#define DAC_FS_192KHZ 6 102#define DAC_FS_96KHZ 7 103#define DAC_FIFOC_FIFO_MODE_SHIFT 24 104#define DAC_FIFOC_FIFO_MODE_MASK (3U << DAC_FIFOC_FIFO_MODE_SHIFT) 105#define FIFO_MODE_24_31_8 0 106#define FIFO_MODE_16_31_16 0 107#define FIFO_MODE_16_15_0 1 108#define DAC_FIFOC_DRQ_CLR_CNT_SHIFT 21 109#define DAC_FIFOC_DRQ_CLR_CNT_MASK (3U << DAC_FIFOC_DRQ_CLR_CNT_SHIFT) 110#define DAC_FIFOC_TX_TRIG_LEVEL_SHIFT 8 111#define DAC_FIFOC_TX_TRIG_LEVEL_MASK (0x7f << DAC_FIFOC_TX_TRIG_LEVEL_SHIFT) 112#define DAC_FIFOC_MONO_EN (1U << 6) 113#define DAC_FIFOC_TX_BITS (1U << 5) 114#define DAC_FIFOC_DRQ_EN (1U << 4) 115#define DAC_FIFOC_FIFO_FLUSH (1U << 0) 116#define AC_DAC_FIFOS(_sc) ((_sc)->cfg->DAC_FIFOS) 117#define AC_DAC_TXDATA(_sc) ((_sc)->cfg->DAC_TXDATA) 118#define AC_ADC_FIFOC(_sc) ((_sc)->cfg->ADC_FIFOC) 119#define ADC_FIFOC_FS_SHIFT 29 120#define ADC_FIFOC_FS_MASK (7U << ADC_FIFOC_FS_SHIFT) 121#define ADC_FS_48KHZ 0 122#define ADC_FIFOC_EN_AD (1U << 28) 123#define ADC_FIFOC_RX_FIFO_MODE (1U << 24) 124#define ADC_FIFOC_RX_TRIG_LEVEL_SHIFT 8 125#define ADC_FIFOC_RX_TRIG_LEVEL_MASK (0x1f << ADC_FIFOC_RX_TRIG_LEVEL_SHIFT) 126#define ADC_FIFOC_MONO_EN (1U << 7) 127#define ADC_FIFOC_RX_BITS (1U << 6) 128#define ADC_FIFOC_DRQ_EN (1U << 4) 129#define ADC_FIFOC_FIFO_FLUSH (1U << 1) 130#define AC_ADC_FIFOS(_sc) ((_sc)->cfg->ADC_FIFOS) 131#define AC_ADC_RXDATA(_sc) ((_sc)->cfg->ADC_RXDATA) 132#define AC_DAC_CNT(_sc) ((_sc)->cfg->DAC_CNT) 133#define AC_ADC_CNT(_sc) ((_sc)->cfg->ADC_CNT) 134 135static uint32_t a10codec_fmt[] = { 136 SND_FORMAT(AFMT_S16_LE, 1, 0), 137 SND_FORMAT(AFMT_S16_LE, 2, 0), 138 0 139}; 140 141static struct pcmchan_caps a10codec_pcaps = { 8000, 192000, a10codec_fmt, 0 }; 142static struct pcmchan_caps a10codec_rcaps = { 8000, 48000, a10codec_fmt, 0 }; 143 144struct a10codec_info; 145 146struct a10codec_chinfo { 147 struct snd_dbuf *buffer; 148 struct pcm_channel *channel; 149 struct a10codec_info *parent; 150 bus_dmamap_t dmamap; 151 void *dmaaddr; 152 bus_addr_t physaddr; 153 bus_size_t fifo; 154 device_t dmac; 155 void *dmachan; 156 157 int dir; 158 int run; 159 uint32_t pos; 160 uint32_t format; 161 uint32_t blocksize; 162 uint32_t speed; 163}; 164 165struct a10codec_info { 166 device_t dev; 167 struct resource *res[2]; 168 struct mtx *lock; 169 bus_dma_tag_t dmat; 170 unsigned dmasize; 171 void *ih; 172 173 struct a10codec_config *cfg; 174 175 struct a10codec_chinfo play; 176 struct a10codec_chinfo rec; 177}; 178 179static struct resource_spec a10codec_spec[] = { 180 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 181 { -1, 0 } 182}; 183 184#define CODEC_ANALOG_READ(sc, reg) bus_read_4((sc)->res[1], (reg)) 185#define CODEC_ANALOG_WRITE(sc, reg, val) bus_write_4((sc)->res[1], (reg), (val)) 186 187#define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) 188#define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 189 190/* 191 * A10/A20 mixer interface 192 */ 193 194#define A10_DAC_ACTL 0x10 195#define A10_DACAREN (1U << 31) 196#define A10_DACALEN (1U << 30) 197#define A10_MIXEN (1U << 29) 198#define A10_DACPAS (1U << 8) 199#define A10_PAMUTE (1U << 6) 200#define A10_PAVOL_SHIFT 0 201#define A10_PAVOL_MASK (0x3f << A10_PAVOL_SHIFT) 202#define A10_ADC_ACTL 0x28 203#define A10_ADCREN (1U << 31) 204#define A10_ADCLEN (1U << 30) 205#define A10_PREG1EN (1U << 29) 206#define A10_PREG2EN (1U << 28) 207#define A10_VMICEN (1U << 27) 208#define A10_ADCG_SHIFT 20 209#define A10_ADCG_MASK (7U << A10_ADCG_SHIFT) 210#define A10_ADCIS_SHIFT 17 211#define A10_ADCIS_MASK (7U << A10_ADCIS_SHIFT) 212#define A10_ADC_IS_LINEIN 0 213#define A10_ADC_IS_FMIN 1 214#define A10_ADC_IS_MIC1 2 215#define A10_ADC_IS_MIC2 3 216#define A10_ADC_IS_MIC1_L_MIC2_R 4 217#define A10_ADC_IS_MIC1_LR_MIC2_LR 5 218#define A10_ADC_IS_OMIX 6 219#define A10_ADC_IS_LINEIN_L_MIC1_R 7 220#define A10_LNRDF (1U << 16) 221#define A10_LNPREG_SHIFT 13 222#define A10_LNPREG_MASK (7U << A10_LNPREG_SHIFT) 223#define A10_PA_EN (1U << 4) 224#define A10_DDE (1U << 3) 225 226static int 227a10_mixer_init(struct snd_mixer *m) 228{ 229 struct a10codec_info *sc = mix_getdevinfo(m); 230 uint32_t val; 231 232 mix_setdevs(m, SOUND_MASK_VOLUME | SOUND_MASK_LINE | SOUND_MASK_RECLEV); 233 mix_setrecdevs(m, SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC); 234 235 /* Unmute input source to PA */ 236 val = CODEC_READ(sc, A10_DAC_ACTL); 237 val |= A10_PAMUTE; 238 CODEC_WRITE(sc, A10_DAC_ACTL, val); 239 240 /* Enable PA */ 241 val = CODEC_READ(sc, A10_ADC_ACTL); 242 val |= A10_PA_EN; 243 CODEC_WRITE(sc, A10_ADC_ACTL, val); 244 245 return (0); 246} 247 248static const struct a10_mixer { 249 unsigned reg; 250 unsigned mask; 251 unsigned shift; 252} a10_mixers[SOUND_MIXER_NRDEVICES] = { 253 [SOUND_MIXER_VOLUME] = { A10_DAC_ACTL, A10_PAVOL_MASK, 254 A10_PAVOL_SHIFT }, 255 [SOUND_MIXER_LINE] = { A10_ADC_ACTL, A10_LNPREG_MASK, 256 A10_LNPREG_SHIFT }, 257 [SOUND_MIXER_RECLEV] = { A10_ADC_ACTL, A10_ADCG_MASK, 258 A10_ADCG_SHIFT }, 259}; 260 261static int 262a10_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, 263 unsigned right) 264{ 265 struct a10codec_info *sc = mix_getdevinfo(m); 266 uint32_t val; 267 unsigned nvol, max; 268 269 max = a10_mixers[dev].mask >> a10_mixers[dev].shift; 270 nvol = (left * max) / 100; 271 272 val = CODEC_READ(sc, a10_mixers[dev].reg); 273 val &= ~a10_mixers[dev].mask; 274 val |= (nvol << a10_mixers[dev].shift); 275 CODEC_WRITE(sc, a10_mixers[dev].reg, val); 276 277 left = right = (left * 100) / max; 278 return (left | (right << 8)); 279} 280 281static uint32_t 282a10_mixer_setrecsrc(struct snd_mixer *m, uint32_t src) 283{ 284 struct a10codec_info *sc = mix_getdevinfo(m); 285 uint32_t val; 286 287 val = CODEC_READ(sc, A10_ADC_ACTL); 288 289 switch (src) { 290 case SOUND_MASK_LINE: /* line-in */ 291 val &= ~A10_ADCIS_MASK; 292 val |= (A10_ADC_IS_LINEIN << A10_ADCIS_SHIFT); 293 break; 294 case SOUND_MASK_MIC: /* MIC1 */ 295 val &= ~A10_ADCIS_MASK; 296 val |= (A10_ADC_IS_MIC1 << A10_ADCIS_SHIFT); 297 break; 298 case SOUND_MASK_LINE1: /* MIC2 */ 299 val &= ~A10_ADCIS_MASK; 300 val |= (A10_ADC_IS_MIC2 << A10_ADCIS_SHIFT); 301 break; 302 default: 303 break; 304 } 305 306 CODEC_WRITE(sc, A10_ADC_ACTL, val); 307 308 switch ((val & A10_ADCIS_MASK) >> A10_ADCIS_SHIFT) { 309 case A10_ADC_IS_LINEIN: 310 return (SOUND_MASK_LINE); 311 case A10_ADC_IS_MIC1: 312 return (SOUND_MASK_MIC); 313 case A10_ADC_IS_MIC2: 314 return (SOUND_MASK_LINE1); 315 default: 316 return (0); 317 } 318} 319 320static void 321a10_mute(struct a10codec_info *sc, int mute, int dir) 322{ 323 uint32_t val; 324 325 if (dir == PCMDIR_PLAY) { 326 val = CODEC_READ(sc, A10_DAC_ACTL); 327 if (mute) { 328 /* Disable DAC analog l/r channels and output mixer */ 329 val &= ~A10_DACAREN; 330 val &= ~A10_DACALEN; 331 val &= ~A10_DACPAS; 332 } else { 333 /* Enable DAC analog l/r channels and output mixer */ 334 val |= A10_DACAREN; 335 val |= A10_DACALEN; 336 val |= A10_DACPAS; 337 } 338 CODEC_WRITE(sc, A10_DAC_ACTL, val); 339 } else { 340 val = CODEC_READ(sc, A10_ADC_ACTL); 341 if (mute) { 342 /* Disable ADC analog l/r channels, MIC1 preamp, 343 * and VMIC pin voltage 344 */ 345 val &= ~A10_ADCREN; 346 val &= ~A10_ADCLEN; 347 val &= ~A10_PREG1EN; 348 val &= ~A10_VMICEN; 349 } else { 350 /* Enable ADC analog l/r channels, MIC1 preamp, 351 * and VMIC pin voltage 352 */ 353 val |= A10_ADCREN; 354 val |= A10_ADCLEN; 355 val |= A10_PREG1EN; 356 val |= A10_VMICEN; 357 } 358 CODEC_WRITE(sc, A10_ADC_ACTL, val); 359 } 360} 361 362static kobj_method_t a10_mixer_methods[] = { 363 KOBJMETHOD(mixer_init, a10_mixer_init), 364 KOBJMETHOD(mixer_set, a10_mixer_set), 365 KOBJMETHOD(mixer_setrecsrc, a10_mixer_setrecsrc), 366 KOBJMETHOD_END 367}; 368MIXER_DECLARE(a10_mixer); 369 370 371/* 372 * H3 mixer interface 373 */ 374 375#define H3_PR_CFG 0x00 376#define H3_AC_PR_RST (1 << 28) 377#define H3_AC_PR_RW (1 << 24) 378#define H3_AC_PR_ADDR_SHIFT 16 379#define H3_AC_PR_ADDR_MASK (0x1f << H3_AC_PR_ADDR_SHIFT) 380#define H3_ACDA_PR_WDAT_SHIFT 8 381#define H3_ACDA_PR_WDAT_MASK (0xff << H3_ACDA_PR_WDAT_SHIFT) 382#define H3_ACDA_PR_RDAT_SHIFT 0 383#define H3_ACDA_PR_RDAT_MASK (0xff << H3_ACDA_PR_RDAT_SHIFT) 384 385#define H3_LOMIXSC 0x01 386#define H3_LOMIXSC_LDAC (1 << 1) 387#define H3_ROMIXSC 0x02 388#define H3_ROMIXSC_RDAC (1 << 1) 389#define H3_DAC_PA_SRC 0x03 390#define H3_DACAREN (1 << 7) 391#define H3_DACALEN (1 << 6) 392#define H3_RMIXEN (1 << 5) 393#define H3_LMIXEN (1 << 4) 394#define H3_LINEIN_GCTR 0x05 395#define H3_LINEING_SHIFT 4 396#define H3_LINEING_MASK (0x7 << H3_LINEING_SHIFT) 397#define H3_MIC_GCTR 0x06 398#define H3_MIC1_GAIN_SHIFT 4 399#define H3_MIC1_GAIN_MASK (0x7 << H3_MIC1_GAIN_SHIFT) 400#define H3_MIC2_GAIN_SHIFT 0 401#define H3_MIC2_GAIN_MASK (0x7 << H3_MIC2_GAIN_SHIFT) 402#define H3_PAEN_CTR 0x07 403#define H3_LINEOUTEN (1 << 7) 404#define H3_LINEOUT_VOLC 0x09 405#define H3_LINEOUTVOL_SHIFT 3 406#define H3_LINEOUTVOL_MASK (0x1f << H3_LINEOUTVOL_SHIFT) 407#define H3_MIC2G_LINEOUT_CTR 0x0a 408#define H3_LINEOUT_LSEL (1 << 3) 409#define H3_LINEOUT_RSEL (1 << 2) 410#define H3_LADCMIXSC 0x0c 411#define H3_RADCMIXSC 0x0d 412#define H3_ADCMIXSC_MIC1 (1 << 6) 413#define H3_ADCMIXSC_MIC2 (1 << 5) 414#define H3_ADCMIXSC_LINEIN (1 << 2) 415#define H3_ADCMIXSC_OMIXER (3 << 0) 416#define H3_ADC_AP_EN 0x0f 417#define H3_ADCREN (1 << 7) 418#define H3_ADCLEN (1 << 6) 419#define H3_ADCG_SHIFT 0 420#define H3_ADCG_MASK (0x7 << H3_ADCG_SHIFT) 421 422static u_int 423h3_pr_read(struct a10codec_info *sc, u_int addr) 424{ 425 uint32_t val; 426 427 /* Read current value */ 428 val = CODEC_ANALOG_READ(sc, H3_PR_CFG); 429 430 /* De-assert reset */ 431 val |= H3_AC_PR_RST; 432 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 433 434 /* Read mode */ 435 val &= ~H3_AC_PR_RW; 436 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 437 438 /* Set address */ 439 val &= ~H3_AC_PR_ADDR_MASK; 440 val |= (addr << H3_AC_PR_ADDR_SHIFT); 441 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 442 443 /* Read data */ 444 return (CODEC_ANALOG_READ(sc , H3_PR_CFG) & H3_ACDA_PR_RDAT_MASK); 445} 446 447static void 448h3_pr_write(struct a10codec_info *sc, u_int addr, u_int data) 449{ 450 uint32_t val; 451 452 /* Read current value */ 453 val = CODEC_ANALOG_READ(sc, H3_PR_CFG); 454 455 /* De-assert reset */ 456 val |= H3_AC_PR_RST; 457 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 458 459 /* Set address */ 460 val &= ~H3_AC_PR_ADDR_MASK; 461 val |= (addr << H3_AC_PR_ADDR_SHIFT); 462 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 463 464 /* Write data */ 465 val &= ~H3_ACDA_PR_WDAT_MASK; 466 val |= (data << H3_ACDA_PR_WDAT_SHIFT); 467 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 468 469 /* Write mode */ 470 val |= H3_AC_PR_RW; 471 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 472} 473 474static void 475h3_pr_set_clear(struct a10codec_info *sc, u_int addr, u_int set, u_int clr) 476{ 477 u_int old, new; 478 479 old = h3_pr_read(sc, addr); 480 new = set | (old & ~clr); 481 h3_pr_write(sc, addr, new); 482} 483 484static int 485h3_mixer_init(struct snd_mixer *m) 486{ 487 int rid=1; 488 pcell_t reg[2]; 489 phandle_t analogref; 490 struct a10codec_info *sc = mix_getdevinfo(m); 491 492 if (OF_getencprop(ofw_bus_get_node(sc->dev), "allwinner,codec-analog-controls", 493 &analogref, sizeof(analogref)) <= 0) { 494 return (ENXIO); 495 } 496 497 if (OF_getencprop(OF_node_from_xref(analogref), "reg", 498 reg, sizeof(reg)) <= 0) { 499 return (ENXIO); 500 } 501 502 sc->res[1] = bus_alloc_resource(sc->dev, SYS_RES_MEMORY, &rid, reg[0], 503 reg[0]+reg[1], reg[1], RF_ACTIVE ); 504 505 if (sc->res[1] == NULL) { 506 return (ENXIO); 507 } 508 509 mix_setdevs(m, SOUND_MASK_PCM | SOUND_MASK_VOLUME | SOUND_MASK_RECLEV | 510 SOUND_MASK_MIC | SOUND_MASK_LINE | SOUND_MASK_LINE1); 511 mix_setrecdevs(m, SOUND_MASK_MIC | SOUND_MASK_LINE | SOUND_MASK_LINE1 | 512 SOUND_MASK_IMIX); 513 514 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 515 516 /* Right & Left LINEOUT enable */ 517 h3_pr_set_clear(sc, H3_PAEN_CTR, H3_LINEOUTEN, 0); 518 h3_pr_set_clear(sc, H3_MIC2G_LINEOUT_CTR, 519 H3_LINEOUT_LSEL | H3_LINEOUT_RSEL, 0); 520 521 return (0); 522} 523 524static const struct h3_mixer { 525 unsigned reg; 526 unsigned mask; 527 unsigned shift; 528} h3_mixers[SOUND_MIXER_NRDEVICES] = { 529 [SOUND_MIXER_VOLUME] = { H3_LINEOUT_VOLC, H3_LINEOUTVOL_MASK, 530 H3_LINEOUTVOL_SHIFT }, 531 [SOUND_MIXER_RECLEV] = { H3_ADC_AP_EN, H3_ADCG_MASK, 532 H3_ADCG_SHIFT }, 533 [SOUND_MIXER_LINE] = { H3_LINEIN_GCTR, H3_LINEING_MASK, 534 H3_LINEING_SHIFT }, 535 [SOUND_MIXER_MIC] = { H3_MIC_GCTR, H3_MIC1_GAIN_MASK, 536 H3_MIC1_GAIN_SHIFT }, 537 [SOUND_MIXER_LINE1] = { H3_MIC_GCTR, H3_MIC2_GAIN_MASK, 538 H3_MIC2_GAIN_SHIFT }, 539}; 540 541static int 542h3_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, 543 unsigned right) 544{ 545 struct a10codec_info *sc = mix_getdevinfo(m); 546 unsigned nvol, max; 547 548 max = h3_mixers[dev].mask >> h3_mixers[dev].shift; 549 nvol = (left * max) / 100; 550 551 h3_pr_set_clear(sc, h3_mixers[dev].reg, 552 nvol << h3_mixers[dev].shift, h3_mixers[dev].mask); 553 554 left = right = (left * 100) / max; 555 return (left | (right << 8)); 556} 557 558static uint32_t 559h3_mixer_setrecsrc(struct snd_mixer *m, uint32_t src) 560{ 561 struct a10codec_info *sc = mix_getdevinfo(m); 562 uint32_t val; 563 564 val = 0; 565 src &= (SOUND_MASK_LINE | SOUND_MASK_MIC | 566 SOUND_MASK_LINE1 | SOUND_MASK_IMIX); 567 568 if ((src & SOUND_MASK_LINE) != 0) /* line-in */ 569 val |= H3_ADCMIXSC_LINEIN; 570 if ((src & SOUND_MASK_MIC) != 0) /* MIC1 */ 571 val |= H3_ADCMIXSC_MIC1; 572 if ((src & SOUND_MASK_LINE1) != 0) /* MIC2 */ 573 val |= H3_ADCMIXSC_MIC2; 574 if ((src & SOUND_MASK_IMIX) != 0) /* l/r output mixer */ 575 val |= H3_ADCMIXSC_OMIXER; 576 577 h3_pr_write(sc, H3_LADCMIXSC, val); 578 h3_pr_write(sc, H3_RADCMIXSC, val); 579 580 return (src); 581} 582 583static void 584h3_mute(struct a10codec_info *sc, int mute, int dir) 585{ 586 if (dir == PCMDIR_PLAY) { 587 if (mute) { 588 /* Mute DAC l/r channels to output mixer */ 589 h3_pr_set_clear(sc, H3_LOMIXSC, 0, H3_LOMIXSC_LDAC); 590 h3_pr_set_clear(sc, H3_ROMIXSC, 0, H3_ROMIXSC_RDAC); 591 /* Disable DAC analog l/r channels and output mixer */ 592 h3_pr_set_clear(sc, H3_DAC_PA_SRC, 593 0, H3_DACAREN | H3_DACALEN | H3_RMIXEN | H3_LMIXEN); 594 } else { 595 /* Enable DAC analog l/r channels and output mixer */ 596 h3_pr_set_clear(sc, H3_DAC_PA_SRC, 597 H3_DACAREN | H3_DACALEN | H3_RMIXEN | H3_LMIXEN, 0); 598 /* Unmute DAC l/r channels to output mixer */ 599 h3_pr_set_clear(sc, H3_LOMIXSC, H3_LOMIXSC_LDAC, 0); 600 h3_pr_set_clear(sc, H3_ROMIXSC, H3_ROMIXSC_RDAC, 0); 601 } 602 } else { 603 if (mute) { 604 /* Disable ADC analog l/r channels */ 605 h3_pr_set_clear(sc, H3_ADC_AP_EN, 606 0, H3_ADCREN | H3_ADCLEN); 607 } else { 608 /* Enable ADC analog l/r channels */ 609 h3_pr_set_clear(sc, H3_ADC_AP_EN, 610 H3_ADCREN | H3_ADCLEN, 0); 611 } 612 } 613} 614 615static kobj_method_t h3_mixer_methods[] = { 616 KOBJMETHOD(mixer_init, h3_mixer_init), 617 KOBJMETHOD(mixer_set, h3_mixer_set), 618 KOBJMETHOD(mixer_setrecsrc, h3_mixer_setrecsrc), 619 KOBJMETHOD_END 620}; 621MIXER_DECLARE(h3_mixer); 622 623 624/* 625 * Channel interface 626 */ 627 628static void 629a10codec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 630{ 631 struct a10codec_chinfo *ch = arg; 632 633 if (error != 0) 634 return; 635 636 ch->physaddr = segs[0].ds_addr; 637} 638 639static void 640a10codec_transfer(struct a10codec_chinfo *ch) 641{ 642 bus_addr_t src, dst; 643 int error; 644 645 if (ch->dir == PCMDIR_PLAY) { 646 src = ch->physaddr + ch->pos; 647 dst = ch->fifo; 648 } else { 649 src = ch->fifo; 650 dst = ch->physaddr + ch->pos; 651 } 652 653 error = SUNXI_DMA_TRANSFER(ch->dmac, ch->dmachan, src, dst, 654 ch->blocksize); 655 if (error) { 656 ch->run = 0; 657 device_printf(ch->parent->dev, "DMA transfer failed: %d\n", 658 error); 659 } 660} 661 662static void 663a10codec_dmaconfig(struct a10codec_chinfo *ch) 664{ 665 struct a10codec_info *sc = ch->parent; 666 struct sunxi_dma_config conf; 667 668 memset(&conf, 0, sizeof(conf)); 669 conf.src_width = conf.dst_width = 16; 670 conf.src_burst_len = conf.dst_burst_len = 4; 671 672 if (ch->dir == PCMDIR_PLAY) { 673 conf.dst_noincr = true; 674 conf.src_drqtype = sc->cfg->drqtype_sdram; 675 conf.dst_drqtype = sc->cfg->drqtype_codec; 676 } else { 677 conf.src_noincr = true; 678 conf.src_drqtype = sc->cfg->drqtype_codec; 679 conf.dst_drqtype = sc->cfg->drqtype_sdram; 680 } 681 682 SUNXI_DMA_SET_CONFIG(ch->dmac, ch->dmachan, &conf); 683} 684 685static void 686a10codec_dmaintr(void *priv) 687{ 688 struct a10codec_chinfo *ch = priv; 689 unsigned bufsize; 690 691 bufsize = sndbuf_getsize(ch->buffer); 692 693 ch->pos += ch->blocksize; 694 if (ch->pos >= bufsize) 695 ch->pos -= bufsize; 696 697 if (ch->run) { 698 chn_intr(ch->channel); 699 a10codec_transfer(ch); 700 } 701} 702 703static unsigned 704a10codec_fs(struct a10codec_chinfo *ch) 705{ 706 switch (ch->speed) { 707 case 48000: 708 return (DAC_FS_48KHZ); 709 case 24000: 710 return (DAC_FS_24KHZ); 711 case 12000: 712 return (DAC_FS_12KHZ); 713 case 192000: 714 return (DAC_FS_192KHZ); 715 case 32000: 716 return (DAC_FS_32KHZ); 717 case 16000: 718 return (DAC_FS_16KHZ); 719 case 8000: 720 return (DAC_FS_8KHZ); 721 case 96000: 722 return (DAC_FS_96KHZ); 723 default: 724 return (DAC_FS_48KHZ); 725 } 726} 727 728static void 729a10codec_start(struct a10codec_chinfo *ch) 730{ 731 struct a10codec_info *sc = ch->parent; 732 uint32_t val; 733 734 ch->pos = 0; 735 736 if (ch->dir == PCMDIR_PLAY) { 737 /* Flush DAC FIFO */ 738 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), DAC_FIFOC_FIFO_FLUSH); 739 740 /* Clear DAC FIFO status */ 741 CODEC_WRITE(sc, AC_DAC_FIFOS(sc), 742 CODEC_READ(sc, AC_DAC_FIFOS(sc))); 743 744 /* Unmute output */ 745 sc->cfg->mute(sc, 0, ch->dir); 746 747 /* Configure DAC DMA channel */ 748 a10codec_dmaconfig(ch); 749 750 /* Configure DAC FIFO */ 751 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 752 (AFMT_CHANNEL(ch->format) == 1 ? DAC_FIFOC_MONO_EN : 0) | 753 (a10codec_fs(ch) << DAC_FIFOC_FS_SHIFT) | 754 (FIFO_MODE_16_15_0 << DAC_FIFOC_FIFO_MODE_SHIFT) | 755 (DRQ_CLR_CNT << DAC_FIFOC_DRQ_CLR_CNT_SHIFT) | 756 (TX_TRIG_LEVEL << DAC_FIFOC_TX_TRIG_LEVEL_SHIFT)); 757 758 /* Enable DAC DRQ */ 759 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 760 val |= DAC_FIFOC_DRQ_EN; 761 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val); 762 } else { 763 /* Flush ADC FIFO */ 764 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), ADC_FIFOC_FIFO_FLUSH); 765 766 /* Clear ADC FIFO status */ 767 CODEC_WRITE(sc, AC_ADC_FIFOS(sc), 768 CODEC_READ(sc, AC_ADC_FIFOS(sc))); 769 770 /* Unmute input */ 771 sc->cfg->mute(sc, 0, ch->dir); 772 773 /* Configure ADC DMA channel */ 774 a10codec_dmaconfig(ch); 775 776 /* Configure ADC FIFO */ 777 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 778 ADC_FIFOC_EN_AD | 779 ADC_FIFOC_RX_FIFO_MODE | 780 (AFMT_CHANNEL(ch->format) == 1 ? ADC_FIFOC_MONO_EN : 0) | 781 (a10codec_fs(ch) << ADC_FIFOC_FS_SHIFT) | 782 (RX_TRIG_LEVEL << ADC_FIFOC_RX_TRIG_LEVEL_SHIFT)); 783 784 /* Enable ADC DRQ */ 785 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 786 val |= ADC_FIFOC_DRQ_EN; 787 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val); 788 } 789 790 /* Start DMA transfer */ 791 a10codec_transfer(ch); 792} 793 794static void 795a10codec_stop(struct a10codec_chinfo *ch) 796{ 797 struct a10codec_info *sc = ch->parent; 798 799 /* Disable DMA channel */ 800 SUNXI_DMA_HALT(ch->dmac, ch->dmachan); 801 802 sc->cfg->mute(sc, 1, ch->dir); 803 804 if (ch->dir == PCMDIR_PLAY) { 805 /* Disable DAC DRQ */ 806 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 0); 807 } else { 808 /* Disable ADC DRQ */ 809 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 0); 810 } 811} 812 813static void * 814a10codec_chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 815 struct pcm_channel *c, int dir) 816{ 817 struct a10codec_info *sc = devinfo; 818 struct a10codec_chinfo *ch = dir == PCMDIR_PLAY ? &sc->play : &sc->rec; 819 phandle_t xref; 820 pcell_t *cells; 821 int ncells, error; 822 823 error = ofw_bus_parse_xref_list_alloc(ofw_bus_get_node(sc->dev), 824 "dmas", "#dma-cells", dir == PCMDIR_PLAY ? 1 : 0, 825 &xref, &ncells, &cells); 826 if (error != 0) { 827 device_printf(sc->dev, "cannot parse 'dmas' property\n"); 828 return (NULL); 829 } 830 OF_prop_free(cells); 831 832 ch->parent = sc; 833 ch->channel = c; 834 ch->buffer = b; 835 ch->dir = dir; 836 ch->fifo = rman_get_start(sc->res[0]) + 837 (dir == PCMDIR_REC ? AC_ADC_RXDATA(sc) : AC_DAC_TXDATA(sc)); 838 839 ch->dmac = OF_device_from_xref(xref); 840 if (ch->dmac == NULL) { 841 device_printf(sc->dev, "cannot find DMA controller\n"); 842 device_printf(sc->dev, "xref = 0x%x\n", (u_int)xref); 843 return (NULL); 844 } 845 ch->dmachan = SUNXI_DMA_ALLOC(ch->dmac, false, a10codec_dmaintr, ch); 846 if (ch->dmachan == NULL) { 847 device_printf(sc->dev, "cannot allocate DMA channel\n"); 848 return (NULL); 849 } 850 851 error = bus_dmamem_alloc(sc->dmat, &ch->dmaaddr, 852 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &ch->dmamap); 853 if (error != 0) { 854 device_printf(sc->dev, "cannot allocate channel buffer\n"); 855 return (NULL); 856 } 857 error = bus_dmamap_load(sc->dmat, ch->dmamap, ch->dmaaddr, 858 sc->dmasize, a10codec_dmamap_cb, ch, BUS_DMA_NOWAIT); 859 if (error != 0) { 860 device_printf(sc->dev, "cannot load DMA map\n"); 861 return (NULL); 862 } 863 memset(ch->dmaaddr, 0, sc->dmasize); 864 865 if (sndbuf_setup(ch->buffer, ch->dmaaddr, sc->dmasize) != 0) { 866 device_printf(sc->dev, "cannot setup sndbuf\n"); 867 return (NULL); 868 } 869 870 return (ch); 871} 872 873static int 874a10codec_chan_free(kobj_t obj, void *data) 875{ 876 struct a10codec_chinfo *ch = data; 877 struct a10codec_info *sc = ch->parent; 878 879 SUNXI_DMA_FREE(ch->dmac, ch->dmachan); 880 bus_dmamap_unload(sc->dmat, ch->dmamap); 881 bus_dmamem_free(sc->dmat, ch->dmaaddr, ch->dmamap); 882 883 return (0); 884} 885 886static int 887a10codec_chan_setformat(kobj_t obj, void *data, uint32_t format) 888{ 889 struct a10codec_chinfo *ch = data; 890 891 ch->format = format; 892 893 return (0); 894} 895 896static uint32_t 897a10codec_chan_setspeed(kobj_t obj, void *data, uint32_t speed) 898{ 899 struct a10codec_chinfo *ch = data; 900 901 /* 902 * The codec supports full duplex operation but both DAC and ADC 903 * use the same source clock (PLL2). Limit the available speeds to 904 * those supported by a 24576000 Hz input. 905 */ 906 switch (speed) { 907 case 8000: 908 case 12000: 909 case 16000: 910 case 24000: 911 case 32000: 912 case 48000: 913 ch->speed = speed; 914 break; 915 case 96000: 916 case 192000: 917 /* 96 KHz / 192 KHz mode only supported for playback */ 918 if (ch->dir == PCMDIR_PLAY) { 919 ch->speed = speed; 920 } else { 921 ch->speed = 48000; 922 } 923 break; 924 case 44100: 925 ch->speed = 48000; 926 break; 927 case 22050: 928 ch->speed = 24000; 929 break; 930 case 11025: 931 ch->speed = 12000; 932 break; 933 default: 934 ch->speed = 48000; 935 break; 936 } 937 938 return (ch->speed); 939} 940 941static uint32_t 942a10codec_chan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 943{ 944 struct a10codec_chinfo *ch = data; 945 946 ch->blocksize = blocksize & ~3; 947 948 return (ch->blocksize); 949} 950 951static int 952a10codec_chan_trigger(kobj_t obj, void *data, int go) 953{ 954 struct a10codec_chinfo *ch = data; 955 struct a10codec_info *sc = ch->parent; 956 957 if (!PCMTRIG_COMMON(go)) 958 return (0); 959 960 snd_mtxlock(sc->lock); 961 switch (go) { 962 case PCMTRIG_START: 963 ch->run = 1; 964 a10codec_stop(ch); 965 a10codec_start(ch); 966 break; 967 case PCMTRIG_STOP: 968 case PCMTRIG_ABORT: 969 ch->run = 0; 970 a10codec_stop(ch); 971 break; 972 default: 973 break; 974 } 975 snd_mtxunlock(sc->lock); 976 977 return (0); 978} 979 980static uint32_t 981a10codec_chan_getptr(kobj_t obj, void *data) 982{ 983 struct a10codec_chinfo *ch = data; 984 985 return (ch->pos); 986} 987 988static struct pcmchan_caps * 989a10codec_chan_getcaps(kobj_t obj, void *data) 990{ 991 struct a10codec_chinfo *ch = data; 992 993 if (ch->dir == PCMDIR_PLAY) { 994 return (&a10codec_pcaps); 995 } else { 996 return (&a10codec_rcaps); 997 } 998} 999 1000static kobj_method_t a10codec_chan_methods[] = { 1001 KOBJMETHOD(channel_init, a10codec_chan_init), 1002 KOBJMETHOD(channel_free, a10codec_chan_free), 1003 KOBJMETHOD(channel_setformat, a10codec_chan_setformat), 1004 KOBJMETHOD(channel_setspeed, a10codec_chan_setspeed), 1005 KOBJMETHOD(channel_setblocksize, a10codec_chan_setblocksize), 1006 KOBJMETHOD(channel_trigger, a10codec_chan_trigger), 1007 KOBJMETHOD(channel_getptr, a10codec_chan_getptr), 1008 KOBJMETHOD(channel_getcaps, a10codec_chan_getcaps), 1009 KOBJMETHOD_END 1010}; 1011CHANNEL_DECLARE(a10codec_chan); 1012 1013 1014/* 1015 * Device interface 1016 */ 1017 1018static const struct a10codec_config a10_config = { 1019 .mixer_class = &a10_mixer_class, 1020 .mute = a10_mute, 1021 .drqtype_codec = 19, 1022 .drqtype_sdram = 22, 1023 .DPC = 0x00, 1024 .DAC_FIFOC = 0x04, 1025 .DAC_FIFOS = 0x08, 1026 .DAC_TXDATA = 0x0c, 1027 .ADC_FIFOC = 0x1c, 1028 .ADC_FIFOS = 0x20, 1029 .ADC_RXDATA = 0x24, 1030 .DAC_CNT = 0x30, 1031 .ADC_CNT = 0x34, 1032}; 1033 1034static const struct a10codec_config h3_config = { 1035 .mixer_class = &h3_mixer_class, 1036 .mute = h3_mute, 1037 .drqtype_codec = 15, 1038 .drqtype_sdram = 1, 1039 .DPC = 0x00, 1040 .DAC_FIFOC = 0x04, 1041 .DAC_FIFOS = 0x08, 1042 .DAC_TXDATA = 0x20, 1043 .ADC_FIFOC = 0x10, 1044 .ADC_FIFOS = 0x14, 1045 .ADC_RXDATA = 0x18, 1046 .DAC_CNT = 0x40, 1047 .ADC_CNT = 0x44, 1048}; 1049 1050static struct ofw_compat_data compat_data[] = { 1051 { "allwinner,sun4i-a10-codec", (uintptr_t)&a10_config }, 1052 { "allwinner,sun7i-a20-codec", (uintptr_t)&a10_config }, 1053 { "allwinner,sun8i-h3-codec", (uintptr_t)&h3_config }, 1054 { NULL, 0 } 1055}; 1056 1057static int 1058a10codec_probe(device_t dev) 1059{ 1060 if (!ofw_bus_status_okay(dev)) 1061 return (ENXIO); 1062 1063 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1064 return (ENXIO); 1065 1066 device_set_desc(dev, "Allwinner Audio Codec"); 1067 return (BUS_PROBE_DEFAULT); 1068} 1069 1070static int 1071a10codec_attach(device_t dev) 1072{ 1073 struct a10codec_info *sc; 1074 char status[SND_STATUSLEN]; 1075 struct gpiobus_pin *pa_pin; 1076 phandle_t node; 1077 clk_t clk_bus, clk_codec; 1078 hwreset_t rst; 1079 uint32_t val; 1080 int error; 1081 1082 node = ofw_bus_get_node(dev); 1083 1084 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 1085 sc->cfg = (void *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1086 sc->dev = dev; 1087 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "a10codec softc"); 1088 1089 if (bus_alloc_resources(dev, a10codec_spec, sc->res)) { 1090 device_printf(dev, "cannot allocate resources for device\n"); 1091 error = ENXIO; 1092 goto fail; 1093 } 1094 1095 sc->dmasize = 131072; 1096 error = bus_dma_tag_create( 1097 bus_get_dma_tag(dev), 1098 4, sc->dmasize, /* alignment, boundary */ 1099 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1100 BUS_SPACE_MAXADDR, /* highaddr */ 1101 NULL, NULL, /* filter, filterarg */ 1102 sc->dmasize, 1, /* maxsize, nsegs */ 1103 sc->dmasize, 0, /* maxsegsize, flags */ 1104 NULL, NULL, /* lockfunc, lockarg */ 1105 &sc->dmat); 1106 if (error != 0) { 1107 device_printf(dev, "cannot create DMA tag\n"); 1108 goto fail; 1109 } 1110 1111 /* Get clocks */ 1112 if (clk_get_by_ofw_name(dev, 0, "apb", &clk_bus) != 0 && 1113 clk_get_by_ofw_name(dev, 0, "ahb", &clk_bus) != 0) { 1114 device_printf(dev, "cannot find bus clock\n"); 1115 goto fail; 1116 } 1117 if (clk_get_by_ofw_name(dev, 0, "codec", &clk_codec) != 0) { 1118 device_printf(dev, "cannot find codec clock\n"); 1119 goto fail; 1120 } 1121 1122 /* Gating bus clock for codec */ 1123 if (clk_enable(clk_bus) != 0) { 1124 device_printf(dev, "cannot enable bus clock\n"); 1125 goto fail; 1126 } 1127 /* Activate audio codec clock. According to the A10 and A20 user 1128 * manuals, Audio_pll can be either 24.576MHz or 22.5792MHz. Most 1129 * audio sampling rates require an 24.576MHz input clock with the 1130 * exception of 44.1kHz, 22.05kHz, and 11.025kHz. Unfortunately, 1131 * both capture and playback use the same clock source so to 1132 * safely support independent full duplex operation, we use a fixed 1133 * 24.576MHz clock source and don't advertise native support for 1134 * the three sampling rates that require a 22.5792MHz input. 1135 */ 1136 error = clk_set_freq(clk_codec, 24576000, CLK_SET_ROUND_DOWN); 1137 if (error != 0) { 1138 device_printf(dev, "cannot set codec clock frequency\n"); 1139 goto fail; 1140 } 1141 /* Enable audio codec clock */ 1142 error = clk_enable(clk_codec); 1143 if (error != 0) { 1144 device_printf(dev, "cannot enable codec clock\n"); 1145 goto fail; 1146 } 1147 1148 /* De-assert hwreset */ 1149 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { 1150 error = hwreset_deassert(rst); 1151 if (error != 0) { 1152 device_printf(dev, "cannot de-assert reset\n"); 1153 goto fail; 1154 } 1155 } 1156 1157 /* Enable DAC */ 1158 val = CODEC_READ(sc, AC_DAC_DPC(sc)); 1159 val |= DAC_DPC_EN_DA; 1160 CODEC_WRITE(sc, AC_DAC_DPC(sc), val); 1161 1162 if (mixer_init(dev, sc->cfg->mixer_class, sc)) { 1163 device_printf(dev, "mixer_init failed\n"); 1164 goto fail; 1165 } 1166 1167 /* Unmute PA */ 1168 if (gpio_pin_get_by_ofw_property(dev, node, "allwinner,pa-gpios", 1169 &pa_pin) == 0) { 1170 error = gpio_pin_set_active(pa_pin, 1); 1171 if (error != 0) 1172 device_printf(dev, "failed to unmute PA\n"); 1173 } 1174 1175 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 1176 1177 if (pcm_register(dev, sc, 1, 1)) { 1178 device_printf(dev, "pcm_register failed\n"); 1179 goto fail; 1180 } 1181 1182 pcm_addchan(dev, PCMDIR_PLAY, &a10codec_chan_class, sc); 1183 pcm_addchan(dev, PCMDIR_REC, &a10codec_chan_class, sc); 1184 1185 snprintf(status, SND_STATUSLEN, "at %s", ofw_bus_get_name(dev)); 1186 pcm_setstatus(dev, status); 1187 1188 return (0); 1189 1190fail: 1191 bus_release_resources(dev, a10codec_spec, sc->res); 1192 snd_mtxfree(sc->lock); 1193 free(sc, M_DEVBUF); 1194 1195 return (ENXIO); 1196} 1197 1198static device_method_t a10codec_pcm_methods[] = { 1199 /* Device interface */ 1200 DEVMETHOD(device_probe, a10codec_probe), 1201 DEVMETHOD(device_attach, a10codec_attach), 1202 1203 DEVMETHOD_END 1204}; 1205 1206static driver_t a10codec_pcm_driver = { 1207 "pcm", 1208 a10codec_pcm_methods, 1209 PCM_SOFTC_SIZE, 1210}; 1211 1212DRIVER_MODULE(a10codec, simplebus, a10codec_pcm_driver, pcm_devclass, 0, 0); 1213MODULE_DEPEND(a10codec, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1214MODULE_VERSION(a10codec, 1); 1215