1//===-- VEISelDAGToDAG.cpp - A dag to dag inst selector for VE ------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines an instruction selector for the VE target. 10// 11//===----------------------------------------------------------------------===// 12 13#include "VETargetMachine.h" 14#include "llvm/CodeGen/MachineRegisterInfo.h" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "llvm/IR/Intrinsics.h" 17#include "llvm/Support/Debug.h" 18#include "llvm/Support/ErrorHandling.h" 19#include "llvm/Support/raw_ostream.h" 20using namespace llvm; 21 22//===----------------------------------------------------------------------===// 23// Instruction Selector Implementation 24//===----------------------------------------------------------------------===// 25 26//===--------------------------------------------------------------------===// 27/// VEDAGToDAGISel - VE specific code to select VE machine 28/// instructions for SelectionDAG operations. 29/// 30namespace { 31class VEDAGToDAGISel : public SelectionDAGISel { 32 /// Subtarget - Keep a pointer to the VE Subtarget around so that we can 33 /// make the right decision when generating code for different targets. 34 const VESubtarget *Subtarget; 35 36public: 37 explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(tm) {} 38 39 bool runOnMachineFunction(MachineFunction &MF) override { 40 Subtarget = &MF.getSubtarget<VESubtarget>(); 41 return SelectionDAGISel::runOnMachineFunction(MF); 42 } 43 44 void Select(SDNode *N) override; 45 46 StringRef getPassName() const override { 47 return "VE DAG->DAG Pattern Instruction Selection"; 48 } 49 50 // Include the pieces autogenerated from the target description. 51#include "VEGenDAGISel.inc" 52}; 53} // end anonymous namespace 54 55void VEDAGToDAGISel::Select(SDNode *N) { 56 SDLoc dl(N); 57 if (N->isMachineOpcode()) { 58 N->setNodeId(-1); 59 return; // Already selected. 60 } 61 62 SelectCode(N); 63} 64 65/// createVEISelDag - This pass converts a legalized DAG into a 66/// VE-specific DAG, ready for instruction scheduling. 67/// 68FunctionPass *llvm::createVEISelDag(VETargetMachine &TM) { 69 return new VEDAGToDAGISel(TM); 70} 71