1//===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "SystemZTargetMachine.h"
10#include "MCTargetDesc/SystemZMCTargetDesc.h"
11#include "SystemZ.h"
12#include "SystemZMachineScheduler.h"
13#include "SystemZTargetTransformInfo.h"
14#include "TargetInfo/SystemZTargetInfo.h"
15#include "llvm/ADT/Optional.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/Analysis/TargetTransformInfo.h"
20#include "llvm/CodeGen/Passes.h"
21#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
22#include "llvm/CodeGen/TargetPassConfig.h"
23#include "llvm/IR/DataLayout.h"
24#include "llvm/Support/CodeGen.h"
25#include "llvm/Support/TargetRegistry.h"
26#include "llvm/Target/TargetLoweringObjectFile.h"
27#include "llvm/Transforms/Scalar.h"
28#include <string>
29
30using namespace llvm;
31
32extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget() {
33  // Register the target.
34  RegisterTargetMachine<SystemZTargetMachine> X(getTheSystemZTarget());
35}
36
37// Determine whether we use the vector ABI.
38static bool UsesVectorABI(StringRef CPU, StringRef FS) {
39  // We use the vector ABI whenever the vector facility is avaiable.
40  // This is the case by default if CPU is z13 or later, and can be
41  // overridden via "[+-]vector" feature string elements.
42  bool VectorABI = true;
43  if (CPU.empty() || CPU == "generic" ||
44      CPU == "z10" || CPU == "z196" || CPU == "zEC12")
45    VectorABI = false;
46
47  SmallVector<StringRef, 3> Features;
48  FS.split(Features, ',', -1, false /* KeepEmpty */);
49  for (auto &Feature : Features) {
50    if (Feature == "vector" || Feature == "+vector")
51      VectorABI = true;
52    if (Feature == "-vector")
53      VectorABI = false;
54  }
55
56  return VectorABI;
57}
58
59static std::string computeDataLayout(const Triple &TT, StringRef CPU,
60                                     StringRef FS) {
61  bool VectorABI = UsesVectorABI(CPU, FS);
62  std::string Ret;
63
64  // Big endian.
65  Ret += "E";
66
67  // Data mangling.
68  Ret += DataLayout::getManglingComponent(TT);
69
70  // Make sure that global data has at least 16 bits of alignment by
71  // default, so that we can refer to it using LARL.  We don't have any
72  // special requirements for stack variables though.
73  Ret += "-i1:8:16-i8:8:16";
74
75  // 64-bit integers are naturally aligned.
76  Ret += "-i64:64";
77
78  // 128-bit floats are aligned only to 64 bits.
79  Ret += "-f128:64";
80
81  // When using the vector ABI, 128-bit vectors are also aligned to 64 bits.
82  if (VectorABI)
83    Ret += "-v128:64";
84
85  // We prefer 16 bits of aligned for all globals; see above.
86  Ret += "-a:8:16";
87
88  // Integer registers are 32 or 64 bits.
89  Ret += "-n32:64";
90
91  return Ret;
92}
93
94static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
95  // Static code is suitable for use in a dynamic executable; there is no
96  // separate DynamicNoPIC model.
97  if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
98    return Reloc::Static;
99  return *RM;
100}
101
102// For SystemZ we define the models as follows:
103//
104// Small:  BRASL can call any function and will use a stub if necessary.
105//         Locally-binding symbols will always be in range of LARL.
106//
107// Medium: BRASL can call any function and will use a stub if necessary.
108//         GOT slots and locally-defined text will always be in range
109//         of LARL, but other symbols might not be.
110//
111// Large:  Equivalent to Medium for now.
112//
113// Kernel: Equivalent to Medium for now.
114//
115// This means that any PIC module smaller than 4GB meets the
116// requirements of Small, so Small seems like the best default there.
117//
118// All symbols bind locally in a non-PIC module, so the choice is less
119// obvious.  There are two cases:
120//
121// - When creating an executable, PLTs and copy relocations allow
122//   us to treat external symbols as part of the executable.
123//   Any executable smaller than 4GB meets the requirements of Small,
124//   so that seems like the best default.
125//
126// - When creating JIT code, stubs will be in range of BRASL if the
127//   image is less than 4GB in size.  GOT entries will likewise be
128//   in range of LARL.  However, the JIT environment has no equivalent
129//   of copy relocs, so locally-binding data symbols might not be in
130//   the range of LARL.  We need the Medium model in that case.
131static CodeModel::Model
132getEffectiveSystemZCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM,
133                             bool JIT) {
134  if (CM) {
135    if (*CM == CodeModel::Tiny)
136      report_fatal_error("Target does not support the tiny CodeModel", false);
137    if (*CM == CodeModel::Kernel)
138      report_fatal_error("Target does not support the kernel CodeModel", false);
139    return *CM;
140  }
141  if (JIT)
142    return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
143  return CodeModel::Small;
144}
145
146SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
147                                           StringRef CPU, StringRef FS,
148                                           const TargetOptions &Options,
149                                           Optional<Reloc::Model> RM,
150                                           Optional<CodeModel::Model> CM,
151                                           CodeGenOpt::Level OL, bool JIT)
152    : LLVMTargetMachine(
153          T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
154          getEffectiveRelocModel(RM),
155          getEffectiveSystemZCodeModel(CM, getEffectiveRelocModel(RM), JIT),
156          OL),
157      TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
158      Subtarget(TT, CPU, FS, *this) {
159  initAsmInfo();
160}
161
162SystemZTargetMachine::~SystemZTargetMachine() = default;
163
164namespace {
165
166/// SystemZ Code Generator Pass Configuration Options.
167class SystemZPassConfig : public TargetPassConfig {
168public:
169  SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM)
170    : TargetPassConfig(TM, PM) {}
171
172  SystemZTargetMachine &getSystemZTargetMachine() const {
173    return getTM<SystemZTargetMachine>();
174  }
175
176  ScheduleDAGInstrs *
177  createPostMachineScheduler(MachineSchedContext *C) const override {
178    return new ScheduleDAGMI(C,
179                             std::make_unique<SystemZPostRASchedStrategy>(C),
180                             /*RemoveKillFlags=*/true);
181  }
182
183  void addIRPasses() override;
184  bool addInstSelector() override;
185  bool addILPOpts() override;
186  void addPostRewrite() override;
187  void addPostRegAlloc() override;
188  void addPreSched2() override;
189  void addPreEmitPass() override;
190};
191
192} // end anonymous namespace
193
194void SystemZPassConfig::addIRPasses() {
195  if (getOptLevel() != CodeGenOpt::None) {
196    addPass(createSystemZTDCPass());
197    addPass(createLoopDataPrefetchPass());
198  }
199
200  TargetPassConfig::addIRPasses();
201}
202
203bool SystemZPassConfig::addInstSelector() {
204  addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
205
206 if (getOptLevel() != CodeGenOpt::None)
207    addPass(createSystemZLDCleanupPass(getSystemZTargetMachine()));
208
209  return false;
210}
211
212bool SystemZPassConfig::addILPOpts() {
213  addPass(&EarlyIfConverterID);
214  return true;
215}
216
217void SystemZPassConfig::addPostRewrite() {
218  addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
219}
220
221void SystemZPassConfig::addPostRegAlloc() {
222  // PostRewrite needs to be run at -O0 also (in which case addPostRewrite()
223  // is not called).
224  if (getOptLevel() == CodeGenOpt::None)
225    addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
226}
227
228void SystemZPassConfig::addPreSched2() {
229  if (getOptLevel() != CodeGenOpt::None)
230    addPass(&IfConverterID);
231}
232
233void SystemZPassConfig::addPreEmitPass() {
234  // Do instruction shortening before compare elimination because some
235  // vector instructions will be shortened into opcodes that compare
236  // elimination recognizes.
237  if (getOptLevel() != CodeGenOpt::None)
238    addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false);
239
240  // We eliminate comparisons here rather than earlier because some
241  // transformations can change the set of available CC values and we
242  // generally want those transformations to have priority.  This is
243  // especially true in the commonest case where the result of the comparison
244  // is used by a single in-range branch instruction, since we will then
245  // be able to fuse the compare and the branch instead.
246  //
247  // For example, two-address NILF can sometimes be converted into
248  // three-address RISBLG.  NILF produces a CC value that indicates whether
249  // the low word is zero, but RISBLG does not modify CC at all.  On the
250  // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG.
251  // The CC value produced by NILL isn't useful for our purposes, but the
252  // value produced by RISBG can be used for any comparison with zero
253  // (not just equality).  So there are some transformations that lose
254  // CC values (while still being worthwhile) and others that happen to make
255  // the CC result more useful than it was originally.
256  //
257  // Another reason is that we only want to use BRANCH ON COUNT in cases
258  // where we know that the count register is not going to be spilled.
259  //
260  // Doing it so late makes it more likely that a register will be reused
261  // between the comparison and the branch, but it isn't clear whether
262  // preventing that would be a win or not.
263  if (getOptLevel() != CodeGenOpt::None)
264    addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false);
265  addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
266
267  // Do final scheduling after all other optimizations, to get an
268  // optimal input for the decoder (branch relaxation must happen
269  // after block placement).
270  if (getOptLevel() != CodeGenOpt::None)
271    addPass(&PostMachineSchedulerID);
272}
273
274TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {
275  return new SystemZPassConfig(*this, PM);
276}
277
278TargetTransformInfo
279SystemZTargetMachine::getTargetTransformInfo(const Function &F) {
280  return TargetTransformInfo(SystemZTTIImpl(this, F));
281}
282