1//===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Mips implementation of the TargetInstrInfo class.
10//
11// FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in
12// order for MipsLongBranch pass to work correctly when the code has inline
13// assembly.  The returned value doesn't have to be the asm instruction's exact
14// size in bytes; MipsLongBranch only expects it to be the correct upper bound.
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
18#define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
19
20#include "MCTargetDesc/MipsMCTargetDesc.h"
21#include "Mips.h"
22#include "MipsRegisterInfo.h"
23#include "llvm/ADT/ArrayRef.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineMemOperand.h"
27#include "llvm/CodeGen/TargetInstrInfo.h"
28#include <cstdint>
29
30#define GET_INSTRINFO_HEADER
31#include "MipsGenInstrInfo.inc"
32
33namespace llvm {
34
35class MachineInstr;
36class MachineOperand;
37class MipsSubtarget;
38class TargetRegisterClass;
39class TargetRegisterInfo;
40
41class MipsInstrInfo : public MipsGenInstrInfo {
42  virtual void anchor();
43
44protected:
45  const MipsSubtarget &Subtarget;
46  unsigned UncondBrOpc;
47
48public:
49  enum BranchType {
50    BT_None,       // Couldn't analyze branch.
51    BT_NoBranch,   // No branches found.
52    BT_Uncond,     // One unconditional branch.
53    BT_Cond,       // One conditional branch.
54    BT_CondUncond, // A conditional branch followed by an unconditional branch.
55    BT_Indirect    // One indirct branch.
56  };
57
58  explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc);
59
60  static const MipsInstrInfo *create(MipsSubtarget &STI);
61
62  /// Branch Analysis
63  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
64                     MachineBasicBlock *&FBB,
65                     SmallVectorImpl<MachineOperand> &Cond,
66                     bool AllowModify) const override;
67
68  unsigned removeBranch(MachineBasicBlock &MBB,
69                        int *BytesRemoved = nullptr) const override;
70
71  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
72                        MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
73                        const DebugLoc &DL,
74                        int *BytesAdded = nullptr) const override;
75
76  bool
77  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
78
79  BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
80                           MachineBasicBlock *&FBB,
81                           SmallVectorImpl<MachineOperand> &Cond,
82                           bool AllowModify,
83                           SmallVectorImpl<MachineInstr *> &BranchInstrs) const;
84
85  /// Determine the opcode of a non-delay slot form for a branch if one exists.
86  unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const;
87
88  /// Determine if the branch target is in range.
89  bool isBranchOffsetInRange(unsigned BranchOpc,
90                             int64_t BrOffset) const override;
91
92  /// Predicate to determine if an instruction can go in a forbidden slot.
93  bool SafeInForbiddenSlot(const MachineInstr &MI) const;
94
95  /// Predicate to determine if an instruction has a forbidden slot.
96  bool HasForbiddenSlot(const MachineInstr &MI) const;
97
98  /// Insert nop instruction when hazard condition is found
99  void insertNoop(MachineBasicBlock &MBB,
100                  MachineBasicBlock::iterator MI) const override;
101
102  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
103  /// such, whenever a client has an instance of instruction info, it should
104  /// always be able to get register info as well (through this method).
105  virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
106
107  virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
108
109  /// Return the number of bytes of code the specified instruction may be.
110  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
111
112  void storeRegToStackSlot(MachineBasicBlock &MBB,
113                           MachineBasicBlock::iterator MBBI,
114                           unsigned SrcReg, bool isKill, int FrameIndex,
115                           const TargetRegisterClass *RC,
116                           const TargetRegisterInfo *TRI) const override {
117    storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
118  }
119
120  void loadRegFromStackSlot(MachineBasicBlock &MBB,
121                            MachineBasicBlock::iterator MBBI,
122                            unsigned DestReg, int FrameIndex,
123                            const TargetRegisterClass *RC,
124                            const TargetRegisterInfo *TRI) const override {
125    loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
126  }
127
128  virtual void storeRegToStack(MachineBasicBlock &MBB,
129                               MachineBasicBlock::iterator MI,
130                               unsigned SrcReg, bool isKill, int FrameIndex,
131                               const TargetRegisterClass *RC,
132                               const TargetRegisterInfo *TRI,
133                               int64_t Offset) const = 0;
134
135  virtual void loadRegFromStack(MachineBasicBlock &MBB,
136                                MachineBasicBlock::iterator MI,
137                                unsigned DestReg, int FrameIndex,
138                                const TargetRegisterClass *RC,
139                                const TargetRegisterInfo *TRI,
140                                int64_t Offset) const = 0;
141
142  virtual void adjustStackPtr(unsigned SP, int64_t Amount,
143                              MachineBasicBlock &MBB,
144                              MachineBasicBlock::iterator I) const = 0;
145
146  /// Create an instruction which has the same operands and memory operands
147  /// as MI but has a new opcode.
148  MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
149                                         MachineBasicBlock::iterator I) const;
150
151  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
152                             unsigned &SrcOpIdx2) const override;
153
154  /// Perform target specific instruction verification.
155  bool verifyInstruction(const MachineInstr &MI,
156                         StringRef &ErrInfo) const override;
157
158  std::pair<unsigned, unsigned>
159  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
160
161  ArrayRef<std::pair<unsigned, const char *>>
162  getSerializableDirectMachineOperandTargetFlags() const override;
163
164protected:
165  bool isZeroImm(const MachineOperand &op) const;
166
167  MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
168                                   MachineMemOperand::Flags Flags) const;
169
170private:
171  virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
172
173  void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
174                     MachineBasicBlock *&BB,
175                     SmallVectorImpl<MachineOperand> &Cond) const;
176
177  void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
178                   const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
179};
180
181/// Create MipsInstrInfo objects.
182const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI);
183const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI);
184
185} // end namespace llvm
186
187#endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
188