1/*- 2 * Copyright (c) 2008 Nathan Whitehorn 3 * All rights reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: releng/11.0/sys/powerpc/powermac/dbdma.c 259671 2013-12-21 00:07:56Z jhibbits $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/malloc.h> 34#include <sys/module.h> 35#include <sys/endian.h> 36#include <sys/bus.h> 37#include <machine/bus.h> 38#include <machine/dbdma.h> 39#include <sys/rman.h> 40 41#include "dbdmavar.h" 42 43static MALLOC_DEFINE(M_DBDMA, "dbdma", "DBDMA Command List"); 44 45static uint32_t dbdma_read_reg(dbdma_channel_t *, u_int); 46static void dbdma_write_reg(dbdma_channel_t *, u_int, uint32_t); 47static void dbdma_phys_callback(void *, bus_dma_segment_t *, int, int); 48 49static void 50dbdma_phys_callback(void *chan, bus_dma_segment_t *segs, int nsegs, int error) 51{ 52 dbdma_channel_t *channel = (dbdma_channel_t *)(chan); 53 54 channel->sc_slots_pa = segs[0].ds_addr; 55 dbdma_write_reg(channel, CHAN_CMDPTR, channel->sc_slots_pa); 56} 57 58int 59dbdma_allocate_channel(struct resource *dbdma_regs, u_int offset, 60 bus_dma_tag_t parent_dma, int slots, dbdma_channel_t **chan) 61{ 62 int error = 0; 63 dbdma_channel_t *channel; 64 65 channel = *chan = malloc(sizeof(struct dbdma_channel), M_DBDMA, 66 M_WAITOK | M_ZERO); 67 68 channel->sc_regs = dbdma_regs; 69 channel->sc_off = offset; 70 dbdma_stop(channel); 71 72 channel->sc_slots_pa = 0; 73 74 error = bus_dma_tag_create(parent_dma, 16, 0, BUS_SPACE_MAXADDR_32BIT, 75 BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE, 1, PAGE_SIZE, 0, NULL, 76 NULL, &(channel->sc_dmatag)); 77 78 error = bus_dmamem_alloc(channel->sc_dmatag, 79 (void **)&channel->sc_slots, BUS_DMA_WAITOK | BUS_DMA_ZERO, 80 &channel->sc_dmamap); 81 82 error = bus_dmamap_load(channel->sc_dmatag, channel->sc_dmamap, 83 channel->sc_slots, PAGE_SIZE, dbdma_phys_callback, channel, 0); 84 85 dbdma_write_reg(channel, CHAN_CMDPTR_HI, 0); 86 87 channel->sc_nslots = slots; 88 89 return (error); 90} 91 92int 93dbdma_resize_channel(dbdma_channel_t *chan, int newslots) 94{ 95 96 if (newslots > (PAGE_SIZE / sizeof(struct dbdma_command))) 97 return (-1); 98 99 chan->sc_nslots = newslots; 100 return (0); 101} 102 103int 104dbdma_free_channel(dbdma_channel_t *chan) 105{ 106 107 dbdma_stop(chan); 108 109 bus_dmamem_free(chan->sc_dmatag, chan->sc_slots, chan->sc_dmamap); 110 bus_dma_tag_destroy(chan->sc_dmatag); 111 112 free(chan, M_DBDMA); 113 114 return (0); 115} 116 117uint16_t 118dbdma_get_cmd_status(dbdma_channel_t *chan, int slot) 119{ 120 121 bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, BUS_DMASYNC_POSTREAD); 122 123 /* 124 * I really did mean to swap resCount and xferStatus here, to 125 * account for the quad-word little endian fields. 126 */ 127 return (le16toh(chan->sc_slots[slot].resCount)); 128} 129 130void 131dbdma_clear_cmd_status(dbdma_channel_t *chan, int slot) 132{ 133 /* See endian note above */ 134 chan->sc_slots[slot].resCount = 0; 135} 136 137uint16_t 138dbdma_get_residuals(dbdma_channel_t *chan, int slot) 139{ 140 141 bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, BUS_DMASYNC_POSTREAD); 142 143 return (le16toh(chan->sc_slots[slot].xferStatus)); 144} 145 146void 147dbdma_reset(dbdma_channel_t *chan) 148{ 149 150 dbdma_stop(chan); 151 dbdma_set_current_cmd(chan, 0); 152 dbdma_run(chan); 153} 154 155void 156dbdma_run(dbdma_channel_t *chan) 157{ 158 uint32_t control_reg; 159 160 control_reg = DBDMA_STATUS_RUN | DBDMA_STATUS_PAUSE | 161 DBDMA_STATUS_WAKE | DBDMA_STATUS_DEAD; 162 control_reg <<= DBDMA_REG_MASK_SHIFT; 163 164 control_reg |= DBDMA_STATUS_RUN; 165 dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg); 166} 167 168void 169dbdma_pause(dbdma_channel_t *chan) 170{ 171 uint32_t control_reg; 172 173 control_reg = DBDMA_STATUS_PAUSE; 174 control_reg <<= DBDMA_REG_MASK_SHIFT; 175 176 control_reg |= DBDMA_STATUS_PAUSE; 177 dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg); 178} 179 180void 181dbdma_wake(dbdma_channel_t *chan) 182{ 183 uint32_t control_reg; 184 185 control_reg = DBDMA_STATUS_WAKE | DBDMA_STATUS_PAUSE | 186 DBDMA_STATUS_RUN | DBDMA_STATUS_DEAD; 187 control_reg <<= DBDMA_REG_MASK_SHIFT; 188 189 control_reg |= DBDMA_STATUS_WAKE | DBDMA_STATUS_RUN; 190 dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg); 191} 192 193void 194dbdma_stop(dbdma_channel_t *chan) 195{ 196 uint32_t control_reg; 197 198 control_reg = DBDMA_STATUS_RUN; 199 control_reg <<= DBDMA_REG_MASK_SHIFT; 200 201 dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg); 202 203 while (dbdma_read_reg(chan, CHAN_STATUS_REG) & DBDMA_STATUS_ACTIVE) 204 DELAY(5); 205} 206 207void 208dbdma_set_current_cmd(dbdma_channel_t *chan, int slot) 209{ 210 uint32_t cmd; 211 212 cmd = chan->sc_slots_pa + slot * sizeof(struct dbdma_command); 213 dbdma_write_reg(chan, CHAN_CMDPTR, cmd); 214} 215 216uint16_t 217dbdma_get_chan_status(dbdma_channel_t *chan) 218{ 219 uint32_t status_reg; 220 221 status_reg = dbdma_read_reg(chan, CHAN_STATUS_REG); 222 return (status_reg & 0x0000ffff); 223} 224 225uint8_t 226dbdma_get_device_status(dbdma_channel_t *chan) 227{ 228 return (dbdma_get_chan_status(chan) & 0x00ff); 229} 230 231void 232dbdma_set_device_status(dbdma_channel_t *chan, uint8_t mask, uint8_t value) 233{ 234 uint32_t control_reg; 235 236 control_reg = mask; 237 control_reg <<= DBDMA_REG_MASK_SHIFT; 238 control_reg |= value; 239 240 dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg); 241} 242 243void 244dbdma_set_interrupt_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val) 245{ 246 uint32_t intr_select; 247 248 intr_select = mask; 249 intr_select <<= DBDMA_REG_MASK_SHIFT; 250 251 intr_select |= val; 252 dbdma_write_reg(chan, CHAN_INTR_SELECT, intr_select); 253} 254 255void 256dbdma_set_branch_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val) 257{ 258 uint32_t br_select; 259 260 br_select = mask; 261 br_select <<= DBDMA_REG_MASK_SHIFT; 262 263 br_select |= val; 264 dbdma_write_reg(chan, CHAN_BRANCH_SELECT, br_select); 265} 266 267void 268dbdma_set_wait_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val) 269{ 270 uint32_t wait_select; 271 272 wait_select = mask; 273 wait_select <<= DBDMA_REG_MASK_SHIFT; 274 wait_select |= val; 275 dbdma_write_reg(chan, CHAN_WAIT_SELECT, wait_select); 276} 277 278void 279dbdma_insert_command(dbdma_channel_t *chan, int slot, int command, int stream, 280 bus_addr_t data, size_t count, uint8_t interrupt, uint8_t branch, 281 uint8_t wait, uint32_t branch_slot) 282{ 283 struct dbdma_command cmd; 284 uint32_t *flip; 285 286 cmd.cmd = command; 287 cmd.key = stream; 288 cmd.intr = interrupt; 289 cmd.branch = branch; 290 cmd.wait = wait; 291 292 cmd.reqCount = count; 293 cmd.address = (uint32_t)(data); 294 if (command != DBDMA_STORE_QUAD && command != DBDMA_LOAD_QUAD) 295 cmd.cmdDep = chan->sc_slots_pa + 296 branch_slot * sizeof(struct dbdma_command); 297 else 298 cmd.cmdDep = branch_slot; 299 300 cmd.resCount = 0; 301 cmd.xferStatus = 0; 302 303 /* 304 * Move quadwords to little-endian. God only knows why 305 * Apple thought this was a good idea. 306 */ 307 flip = (uint32_t *)(&cmd); 308 flip[0] = htole32(flip[0]); 309 flip[1] = htole32(flip[1]); 310 flip[2] = htole32(flip[2]); 311 312 chan->sc_slots[slot] = cmd; 313} 314 315void 316dbdma_insert_stop(dbdma_channel_t *chan, int slot) 317{ 318 319 dbdma_insert_command(chan, slot, DBDMA_STOP, 0, 0, 0, DBDMA_NEVER, 320 DBDMA_NEVER, DBDMA_NEVER, 0); 321} 322 323void 324dbdma_insert_nop(dbdma_channel_t *chan, int slot) 325{ 326 327 dbdma_insert_command(chan, slot, DBDMA_NOP, 0, 0, 0, DBDMA_NEVER, 328 DBDMA_NEVER, DBDMA_NEVER, 0); 329} 330 331void 332dbdma_insert_branch(dbdma_channel_t *chan, int slot, int to_slot) 333{ 334 335 dbdma_insert_command(chan, slot, DBDMA_NOP, 0, 0, 0, DBDMA_NEVER, 336 DBDMA_ALWAYS, DBDMA_NEVER, to_slot); 337} 338 339void 340dbdma_sync_commands(dbdma_channel_t *chan, bus_dmasync_op_t op) 341{ 342 343 bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, op); 344} 345 346void 347dbdma_save_state(dbdma_channel_t *chan) 348{ 349 350 chan->sc_saved_regs[0] = dbdma_read_reg(chan, CHAN_CMDPTR); 351 chan->sc_saved_regs[1] = dbdma_read_reg(chan, CHAN_CMDPTR_HI); 352 chan->sc_saved_regs[2] = dbdma_read_reg(chan, CHAN_INTR_SELECT); 353 chan->sc_saved_regs[3] = dbdma_read_reg(chan, CHAN_BRANCH_SELECT); 354 chan->sc_saved_regs[4] = dbdma_read_reg(chan, CHAN_WAIT_SELECT); 355 356 dbdma_stop(chan); 357} 358 359void 360dbdma_restore_state(dbdma_channel_t *chan) 361{ 362 363 dbdma_wake(chan); 364 dbdma_write_reg(chan, CHAN_CMDPTR, chan->sc_saved_regs[0]); 365 dbdma_write_reg(chan, CHAN_CMDPTR_HI, chan->sc_saved_regs[1]); 366 dbdma_write_reg(chan, CHAN_INTR_SELECT, chan->sc_saved_regs[2]); 367 dbdma_write_reg(chan, CHAN_BRANCH_SELECT, chan->sc_saved_regs[3]); 368 dbdma_write_reg(chan, CHAN_WAIT_SELECT, chan->sc_saved_regs[4]); 369} 370 371static uint32_t 372dbdma_read_reg(dbdma_channel_t *chan, u_int offset) 373{ 374 375 return (bus_read_4(chan->sc_regs, chan->sc_off + offset)); 376} 377 378static void 379dbdma_write_reg(dbdma_channel_t *chan, u_int offset, uint32_t val) 380{ 381 382 bus_write_4(chan->sc_regs, chan->sc_off + offset, val); 383} 384