1/* 2 * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34#define LINUXKPI_PARAM_PREFIX mlx4_ 35 36#include <linux/page.h> 37#include <linux/mlx4/cq.h> 38#include <linux/slab.h> 39#include <linux/mlx4/qp.h> 40#include <linux/if_vlan.h> 41#include <linux/vmalloc.h> 42#include <linux/moduleparam.h> 43 44#include <netinet/in_systm.h> 45#include <netinet/in.h> 46#include <netinet/if_ether.h> 47#include <netinet/ip.h> 48#include <netinet/ip6.h> 49#include <netinet/tcp.h> 50#include <netinet/tcp_lro.h> 51#include <netinet/udp.h> 52 53#include "mlx4_en.h" 54 55enum { 56 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 57 MAX_BF = 256, 58 MIN_PKT_LEN = 17, 59}; 60 61static int inline_thold __read_mostly = MAX_INLINE; 62 63module_param_named(inline_thold, inline_thold, uint, 0444); 64MODULE_PARM_DESC(inline_thold, "threshold for using inline data"); 65 66int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 67 struct mlx4_en_tx_ring **pring, u32 size, 68 u16 stride, int node, int queue_idx) 69{ 70 struct mlx4_en_dev *mdev = priv->mdev; 71 struct mlx4_en_tx_ring *ring; 72 uint32_t x; 73 int tmp; 74 int err; 75 76 ring = kzalloc_node(sizeof(struct mlx4_en_tx_ring), GFP_KERNEL, node); 77 if (!ring) { 78 ring = kzalloc(sizeof(struct mlx4_en_tx_ring), GFP_KERNEL); 79 if (!ring) { 80 en_err(priv, "Failed allocating TX ring\n"); 81 return -ENOMEM; 82 } 83 } 84 85 /* Create DMA descriptor TAG */ 86 if ((err = -bus_dma_tag_create( 87 bus_get_dma_tag(mdev->pdev->dev.bsddev), 88 1, /* any alignment */ 89 0, /* no boundary */ 90 BUS_SPACE_MAXADDR, /* lowaddr */ 91 BUS_SPACE_MAXADDR, /* highaddr */ 92 NULL, NULL, /* filter, filterarg */ 93 MLX4_EN_TX_MAX_PAYLOAD_SIZE, /* maxsize */ 94 MLX4_EN_TX_MAX_MBUF_FRAGS, /* nsegments */ 95 MLX4_EN_TX_MAX_MBUF_SIZE, /* maxsegsize */ 96 0, /* flags */ 97 NULL, NULL, /* lockfunc, lockfuncarg */ 98 &ring->dma_tag))) 99 goto done; 100 101 ring->size = size; 102 ring->size_mask = size - 1; 103 ring->stride = stride; 104 ring->inline_thold = MAX(MIN_PKT_LEN, MIN(inline_thold, MAX_INLINE)); 105 mtx_init(&ring->tx_lock.m, "mlx4 tx", NULL, MTX_DEF); 106 mtx_init(&ring->comp_lock.m, "mlx4 comp", NULL, MTX_DEF); 107 108 /* Allocate the buf ring */ 109 ring->br = buf_ring_alloc(MLX4_EN_DEF_TX_QUEUE_SIZE, M_DEVBUF, 110 M_WAITOK, &ring->tx_lock.m); 111 if (ring->br == NULL) { 112 en_err(priv, "Failed allocating tx_info ring\n"); 113 err = -ENOMEM; 114 goto err_free_dma_tag; 115 } 116 117 tmp = size * sizeof(struct mlx4_en_tx_info); 118 ring->tx_info = kzalloc_node(tmp, GFP_KERNEL, node); 119 if (!ring->tx_info) { 120 ring->tx_info = kzalloc(tmp, GFP_KERNEL); 121 if (!ring->tx_info) { 122 err = -ENOMEM; 123 goto err_ring; 124 } 125 } 126 127 /* Create DMA descriptor MAPs */ 128 for (x = 0; x != size; x++) { 129 err = -bus_dmamap_create(ring->dma_tag, 0, 130 &ring->tx_info[x].dma_map); 131 if (err != 0) { 132 while (x--) { 133 bus_dmamap_destroy(ring->dma_tag, 134 ring->tx_info[x].dma_map); 135 } 136 goto err_info; 137 } 138 } 139 140 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", 141 ring->tx_info, tmp); 142 143 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); 144 145 /* Allocate HW buffers on provided NUMA node */ 146 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, 147 2 * PAGE_SIZE); 148 if (err) { 149 en_err(priv, "Failed allocating hwq resources\n"); 150 goto err_dma_map; 151 } 152 153 err = mlx4_en_map_buffer(&ring->wqres.buf); 154 if (err) { 155 en_err(priv, "Failed to map TX buffer\n"); 156 goto err_hwq_res; 157 } 158 159 ring->buf = ring->wqres.buf.direct.buf; 160 161 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d " 162 "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size, 163 ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map); 164 165 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, 166 MLX4_RESERVE_BF_QP); 167 if (err) { 168 en_err(priv, "failed reserving qp for TX ring\n"); 169 goto err_map; 170 } 171 172 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp); 173 if (err) { 174 en_err(priv, "Failed allocating qp %d\n", ring->qpn); 175 goto err_reserve; 176 } 177 ring->qp.event = mlx4_en_sqp_event; 178 179 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); 180 if (err) { 181 en_dbg(DRV, priv, "working without blueflame (%d)", err); 182 ring->bf.uar = &mdev->priv_uar; 183 ring->bf.uar->map = mdev->uar_map; 184 ring->bf_enabled = false; 185 } else 186 ring->bf_enabled = true; 187 ring->queue_index = queue_idx; 188 if (queue_idx < priv->num_tx_rings_p_up ) 189 CPU_SET(queue_idx, &ring->affinity_mask); 190 191 *pring = ring; 192 return 0; 193 194err_reserve: 195 mlx4_qp_release_range(mdev->dev, ring->qpn, 1); 196err_map: 197 mlx4_en_unmap_buffer(&ring->wqres.buf); 198err_hwq_res: 199 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 200err_dma_map: 201 for (x = 0; x != size; x++) 202 bus_dmamap_destroy(ring->dma_tag, ring->tx_info[x].dma_map); 203err_info: 204 vfree(ring->tx_info); 205err_ring: 206 buf_ring_free(ring->br, M_DEVBUF); 207err_free_dma_tag: 208 bus_dma_tag_destroy(ring->dma_tag); 209done: 210 kfree(ring); 211 return err; 212} 213 214void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 215 struct mlx4_en_tx_ring **pring) 216{ 217 struct mlx4_en_dev *mdev = priv->mdev; 218 struct mlx4_en_tx_ring *ring = *pring; 219 uint32_t x; 220 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); 221 222 buf_ring_free(ring->br, M_DEVBUF); 223 if (ring->bf_enabled) 224 mlx4_bf_free(mdev->dev, &ring->bf); 225 mlx4_qp_remove(mdev->dev, &ring->qp); 226 mlx4_qp_free(mdev->dev, &ring->qp); 227 mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); 228 mlx4_en_unmap_buffer(&ring->wqres.buf); 229 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 230 for (x = 0; x != ring->size; x++) 231 bus_dmamap_destroy(ring->dma_tag, ring->tx_info[x].dma_map); 232 vfree(ring->tx_info); 233 mtx_destroy(&ring->tx_lock.m); 234 mtx_destroy(&ring->comp_lock.m); 235 bus_dma_tag_destroy(ring->dma_tag); 236 kfree(ring); 237 *pring = NULL; 238} 239 240int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 241 struct mlx4_en_tx_ring *ring, 242 int cq, int user_prio) 243{ 244 struct mlx4_en_dev *mdev = priv->mdev; 245 int err; 246 247 ring->cqn = cq; 248 ring->prod = 0; 249 ring->cons = 0xffffffff; 250 ring->last_nr_txbb = 1; 251 ring->poll_cnt = 0; 252 ring->blocked = 0; 253 memset(ring->buf, 0, ring->buf_size); 254 255 ring->qp_state = MLX4_QP_STATE_RST; 256 ring->doorbell_qpn = ring->qp.qpn << 8; 257 258 mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, 259 ring->cqn, user_prio, &ring->context); 260 if (ring->bf_enabled) 261 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index); 262 263 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, 264 &ring->qp, &ring->qp_state); 265 return err; 266} 267 268void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 269 struct mlx4_en_tx_ring *ring) 270{ 271 struct mlx4_en_dev *mdev = priv->mdev; 272 273 mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, 274 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); 275} 276 277static volatile struct mlx4_wqe_data_seg * 278mlx4_en_store_inline_lso_data(volatile struct mlx4_wqe_data_seg *dseg, 279 struct mbuf *mb, int len, __be32 owner_bit) 280{ 281 uint8_t *inl = __DEVOLATILE(uint8_t *, dseg); 282 283 /* copy data into place */ 284 m_copydata(mb, 0, len, inl + 4); 285 dseg += DIV_ROUND_UP(4 + len, DS_SIZE_ALIGNMENT); 286 return (dseg); 287} 288 289static void 290mlx4_en_store_inline_lso_header(volatile struct mlx4_wqe_data_seg *dseg, 291 int len, __be32 owner_bit) 292{ 293} 294 295static void 296mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, 297 struct mlx4_en_tx_ring *ring, u32 index, u8 owner) 298{ 299 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; 300 struct mlx4_en_tx_desc *tx_desc = (struct mlx4_en_tx_desc *) 301 (ring->buf + (index * TXBB_SIZE)); 302 volatile __be32 *ptr = (__be32 *)tx_desc; 303 const __be32 stamp = cpu_to_be32(STAMP_VAL | 304 ((u32)owner << STAMP_SHIFT)); 305 u32 i; 306 307 /* Stamp the freed descriptor */ 308 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) { 309 *ptr = stamp; 310 ptr += STAMP_DWORDS; 311 } 312} 313 314static u32 315mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 316 struct mlx4_en_tx_ring *ring, u32 index) 317{ 318 struct mlx4_en_tx_info *tx_info; 319 struct mbuf *mb; 320 321 tx_info = &ring->tx_info[index]; 322 mb = tx_info->mb; 323 324 if (mb == NULL) 325 goto done; 326 327 bus_dmamap_sync(ring->dma_tag, tx_info->dma_map, 328 BUS_DMASYNC_POSTWRITE); 329 bus_dmamap_unload(ring->dma_tag, tx_info->dma_map); 330 331 m_freem(mb); 332done: 333 return (tx_info->nr_txbb); 334} 335 336int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) 337{ 338 struct mlx4_en_priv *priv = netdev_priv(dev); 339 int cnt = 0; 340 341 /* Skip last polled descriptor */ 342 ring->cons += ring->last_nr_txbb; 343 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", 344 ring->cons, ring->prod); 345 346 if ((u32) (ring->prod - ring->cons) > ring->size) { 347 en_warn(priv, "Tx consumer passed producer!\n"); 348 return 0; 349 } 350 351 while (ring->cons != ring->prod) { 352 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, 353 ring->cons & ring->size_mask); 354 ring->cons += ring->last_nr_txbb; 355 cnt++; 356 } 357 358 if (cnt) 359 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); 360 361 return cnt; 362} 363 364static bool 365mlx4_en_tx_ring_is_full(struct mlx4_en_tx_ring *ring) 366{ 367 int wqs; 368 wqs = ring->size - (ring->prod - ring->cons); 369 return (wqs < (HEADROOM + (2 * MLX4_EN_TX_WQE_MAX_WQEBBS))); 370} 371 372static int mlx4_en_process_tx_cq(struct net_device *dev, 373 struct mlx4_en_cq *cq) 374{ 375 struct mlx4_en_priv *priv = netdev_priv(dev); 376 struct mlx4_cq *mcq = &cq->mcq; 377 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring]; 378 struct mlx4_cqe *cqe; 379 u16 index; 380 u16 new_index, ring_index, stamp_index; 381 u32 txbbs_skipped = 0; 382 u32 txbbs_stamp = 0; 383 u32 cons_index = mcq->cons_index; 384 int size = cq->size; 385 u32 size_mask = ring->size_mask; 386 struct mlx4_cqe *buf = cq->buf; 387 int factor = priv->cqe_factor; 388 389 if (!priv->port_up) 390 return 0; 391 392 index = cons_index & size_mask; 393 cqe = &buf[(index << factor) + factor]; 394 ring_index = ring->cons & size_mask; 395 stamp_index = ring_index; 396 397 /* Process all completed CQEs */ 398 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, 399 cons_index & size)) { 400 /* 401 * make sure we read the CQE after we read the 402 * ownership bit 403 */ 404 rmb(); 405 406 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 407 MLX4_CQE_OPCODE_ERROR)) { 408 en_err(priv, "CQE completed in error - vendor syndrom: 0x%x syndrom: 0x%x\n", 409 ((struct mlx4_err_cqe *)cqe)-> 410 vendor_err_syndrome, 411 ((struct mlx4_err_cqe *)cqe)->syndrome); 412 } 413 414 /* Skip over last polled CQE */ 415 new_index = be16_to_cpu(cqe->wqe_index) & size_mask; 416 417 do { 418 txbbs_skipped += ring->last_nr_txbb; 419 ring_index = (ring_index + ring->last_nr_txbb) & size_mask; 420 /* free next descriptor */ 421 ring->last_nr_txbb = mlx4_en_free_tx_desc( 422 priv, ring, ring_index); 423 mlx4_en_stamp_wqe(priv, ring, stamp_index, 424 !!((ring->cons + txbbs_stamp) & 425 ring->size)); 426 stamp_index = ring_index; 427 txbbs_stamp = txbbs_skipped; 428 } while (ring_index != new_index); 429 430 ++cons_index; 431 index = cons_index & size_mask; 432 cqe = &buf[(index << factor) + factor]; 433 } 434 435 436 /* 437 * To prevent CQ overflow we first update CQ consumer and only then 438 * the ring consumer. 439 */ 440 mcq->cons_index = cons_index; 441 mlx4_cq_set_ci(mcq); 442 wmb(); 443 ring->cons += txbbs_skipped; 444 445 /* Wakeup Tx queue if it was stopped and ring is not full */ 446 if (unlikely(ring->blocked) && !mlx4_en_tx_ring_is_full(ring)) { 447 ring->blocked = 0; 448 if (atomic_fetchadd_int(&priv->blocked, -1) == 1) 449 atomic_clear_int(&dev->if_drv_flags ,IFF_DRV_OACTIVE); 450 ring->wake_queue++; 451 priv->port_stats.wake_queue++; 452 } 453 return (0); 454} 455 456void mlx4_en_tx_irq(struct mlx4_cq *mcq) 457{ 458 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); 459 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 460 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring]; 461 462 if (priv->port_up == 0 || !spin_trylock(&ring->comp_lock)) 463 return; 464 mlx4_en_process_tx_cq(cq->dev, cq); 465 mod_timer(&cq->timer, jiffies + 1); 466 spin_unlock(&ring->comp_lock); 467} 468 469void mlx4_en_poll_tx_cq(unsigned long data) 470{ 471 struct mlx4_en_cq *cq = (struct mlx4_en_cq *) data; 472 struct mlx4_en_priv *priv = netdev_priv(cq->dev); 473 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring]; 474 u32 inflight; 475 476 INC_PERF_COUNTER(priv->pstats.tx_poll); 477 478 if (priv->port_up == 0) 479 return; 480 if (!spin_trylock(&ring->comp_lock)) { 481 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); 482 return; 483 } 484 mlx4_en_process_tx_cq(cq->dev, cq); 485 inflight = (u32) (ring->prod - ring->cons - ring->last_nr_txbb); 486 487 /* If there are still packets in flight and the timer has not already 488 * been scheduled by the Tx routine then schedule it here to guarantee 489 * completion processing of these packets */ 490 if (inflight && priv->port_up) 491 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); 492 493 spin_unlock(&ring->comp_lock); 494} 495 496static inline void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind) 497{ 498 struct mlx4_en_cq *cq = priv->tx_cq[tx_ind]; 499 struct mlx4_en_tx_ring *ring = priv->tx_ring[tx_ind]; 500 501 if (priv->port_up == 0) 502 return; 503 504 /* If we don't have a pending timer, set one up to catch our recent 505 post in case the interface becomes idle */ 506 if (!timer_pending(&cq->timer)) 507 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); 508 509 /* Poll the CQ every mlx4_en_TX_MODER_POLL packets */ 510 if ((++ring->poll_cnt & (MLX4_EN_TX_POLL_MODER - 1)) == 0) 511 if (spin_trylock(&ring->comp_lock)) { 512 mlx4_en_process_tx_cq(priv->dev, cq); 513 spin_unlock(&ring->comp_lock); 514 } 515} 516 517static u16 518mlx4_en_get_inline_hdr_size(struct mlx4_en_tx_ring *ring, struct mbuf *mb) 519{ 520 u16 retval; 521 522 /* only copy from first fragment, if possible */ 523 retval = MIN(ring->inline_thold, mb->m_len); 524 525 /* check for too little data */ 526 if (unlikely(retval < MIN_PKT_LEN)) 527 retval = MIN(ring->inline_thold, mb->m_pkthdr.len); 528 return (retval); 529} 530 531static int 532mlx4_en_get_header_size(struct mbuf *mb) 533{ 534 struct ether_vlan_header *eh; 535 struct tcphdr *th; 536 struct ip *ip; 537 int ip_hlen, tcp_hlen; 538 struct ip6_hdr *ip6; 539 uint16_t eth_type; 540 int eth_hdr_len; 541 542 eh = mtod(mb, struct ether_vlan_header *); 543 if (mb->m_len < ETHER_HDR_LEN) 544 return (0); 545 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 546 eth_type = ntohs(eh->evl_proto); 547 eth_hdr_len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 548 } else { 549 eth_type = ntohs(eh->evl_encap_proto); 550 eth_hdr_len = ETHER_HDR_LEN; 551 } 552 if (mb->m_len < eth_hdr_len) 553 return (0); 554 switch (eth_type) { 555 case ETHERTYPE_IP: 556 ip = (struct ip *)(mb->m_data + eth_hdr_len); 557 if (mb->m_len < eth_hdr_len + sizeof(*ip)) 558 return (0); 559 if (ip->ip_p != IPPROTO_TCP) 560 return (0); 561 ip_hlen = ip->ip_hl << 2; 562 eth_hdr_len += ip_hlen; 563 break; 564 case ETHERTYPE_IPV6: 565 ip6 = (struct ip6_hdr *)(mb->m_data + eth_hdr_len); 566 if (mb->m_len < eth_hdr_len + sizeof(*ip6)) 567 return (0); 568 if (ip6->ip6_nxt != IPPROTO_TCP) 569 return (0); 570 eth_hdr_len += sizeof(*ip6); 571 break; 572 default: 573 return (0); 574 } 575 if (mb->m_len < eth_hdr_len + sizeof(*th)) 576 return (0); 577 th = (struct tcphdr *)(mb->m_data + eth_hdr_len); 578 tcp_hlen = th->th_off << 2; 579 eth_hdr_len += tcp_hlen; 580 if (mb->m_len < eth_hdr_len) 581 return (0); 582 return (eth_hdr_len); 583} 584 585static volatile struct mlx4_wqe_data_seg * 586mlx4_en_store_inline_data(volatile struct mlx4_wqe_data_seg *dseg, 587 struct mbuf *mb, int len, __be32 owner_bit) 588{ 589 uint8_t *inl = __DEVOLATILE(uint8_t *, dseg); 590 const int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - 4; 591 592 if (unlikely(len < MIN_PKT_LEN)) { 593 m_copydata(mb, 0, len, inl + 4); 594 memset(inl + 4 + len, 0, MIN_PKT_LEN - len); 595 dseg += DIV_ROUND_UP(4 + MIN_PKT_LEN, DS_SIZE_ALIGNMENT); 596 } else if (len <= spc) { 597 m_copydata(mb, 0, len, inl + 4); 598 dseg += DIV_ROUND_UP(4 + len, DS_SIZE_ALIGNMENT); 599 } else { 600 m_copydata(mb, 0, spc, inl + 4); 601 m_copydata(mb, spc, len - spc, inl + 8 + spc); 602 dseg += DIV_ROUND_UP(8 + len, DS_SIZE_ALIGNMENT); 603 } 604 return (dseg); 605} 606 607static void 608mlx4_en_store_inline_header(volatile struct mlx4_wqe_data_seg *dseg, 609 int len, __be32 owner_bit) 610{ 611 uint8_t *inl = __DEVOLATILE(uint8_t *, dseg); 612 const int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - 4; 613 614 if (unlikely(len < MIN_PKT_LEN)) { 615 *(volatile uint32_t *)inl = 616 SET_BYTE_COUNT((1 << 31) | MIN_PKT_LEN); 617 } else if (len <= spc) { 618 *(volatile uint32_t *)inl = 619 SET_BYTE_COUNT((1 << 31) | len); 620 } else { 621 *(volatile uint32_t *)(inl + 4 + spc) = 622 SET_BYTE_COUNT((1 << 31) | (len - spc)); 623 wmb(); 624 *(volatile uint32_t *)inl = 625 SET_BYTE_COUNT((1 << 31) | spc); 626 } 627} 628 629static uint32_t hashrandom; 630static void hashrandom_init(void *arg) 631{ 632 /* 633 * It is assumed that the random subsystem has been 634 * initialized when this function is called: 635 */ 636 hashrandom = m_ether_tcpip_hash_init(); 637} 638SYSINIT(hashrandom_init, SI_SUB_RANDOM, SI_ORDER_ANY, &hashrandom_init, NULL); 639 640u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb) 641{ 642 struct mlx4_en_priv *priv = netdev_priv(dev); 643 u32 rings_p_up = priv->num_tx_rings_p_up; 644 u32 up = 0; 645 u32 queue_index; 646 647#if (MLX4_EN_NUM_UP > 1) 648 /* Obtain VLAN information if present */ 649 if (mb->m_flags & M_VLANTAG) { 650 u32 vlan_tag = mb->m_pkthdr.ether_vtag; 651 up = (vlan_tag >> 13) % MLX4_EN_NUM_UP; 652 } 653#endif 654 queue_index = m_ether_tcpip_hash(MBUF_HASHFLAG_L3 | MBUF_HASHFLAG_L4, mb, hashrandom); 655 656 return ((queue_index % rings_p_up) + (up * rings_p_up)); 657} 658 659static void mlx4_bf_copy(void __iomem *dst, volatile unsigned long *src, unsigned bytecnt) 660{ 661 __iowrite64_copy(dst, __DEVOLATILE(void *, src), bytecnt / 8); 662} 663 664static u64 mlx4_en_mac_to_u64(u8 *addr) 665{ 666 u64 mac = 0; 667 int i; 668 669 for (i = 0; i < ETHER_ADDR_LEN; i++) { 670 mac <<= 8; 671 mac |= addr[i]; 672 } 673 return mac; 674} 675 676static int mlx4_en_xmit(struct mlx4_en_priv *priv, int tx_ind, struct mbuf **mbp) 677{ 678 enum { 679 DS_FACT = TXBB_SIZE / DS_SIZE_ALIGNMENT, 680 CTRL_FLAGS = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE | 681 MLX4_WQE_CTRL_SOLICITED), 682 }; 683 bus_dma_segment_t segs[MLX4_EN_TX_MAX_MBUF_FRAGS]; 684 volatile struct mlx4_wqe_data_seg *dseg; 685 volatile struct mlx4_wqe_data_seg *dseg_inline; 686 volatile struct mlx4_en_tx_desc *tx_desc; 687 struct mlx4_en_tx_ring *ring = priv->tx_ring[tx_ind]; 688 struct ifnet *ifp = priv->dev; 689 struct mlx4_en_tx_info *tx_info; 690 struct mbuf *mb = *mbp; 691 struct mbuf *m; 692 __be32 owner_bit; 693 int nr_segs; 694 int pad; 695 int err; 696 u32 bf_size; 697 u32 bf_prod; 698 u32 opcode; 699 u16 index; 700 u16 ds_cnt; 701 u16 ihs; 702 703 if (unlikely(!priv->port_up)) { 704 err = EINVAL; 705 goto tx_drop; 706 } 707 708 /* check if TX ring is full */ 709 if (unlikely(mlx4_en_tx_ring_is_full(ring))) { 710 /* every full native Tx ring stops queue */ 711 if (ring->blocked == 0) 712 atomic_add_int(&priv->blocked, 1); 713 /* Set HW-queue-is-full flag */ 714 atomic_set_int(&ifp->if_drv_flags, IFF_DRV_OACTIVE); 715 priv->port_stats.queue_stopped++; 716 ring->blocked = 1; 717 priv->port_stats.queue_stopped++; 718 ring->queue_stopped++; 719 720 /* Use interrupts to find out when queue opened */ 721 mlx4_en_arm_cq(priv, priv->tx_cq[tx_ind]); 722 return (ENOBUFS); 723 } 724 725 /* sanity check we are not wrapping around */ 726 KASSERT(((~ring->prod) & ring->size_mask) >= 727 (MLX4_EN_TX_WQE_MAX_WQEBBS - 1), ("Wrapping around TX ring")); 728 729 /* Track current inflight packets for performance analysis */ 730 AVG_PERF_COUNTER(priv->pstats.inflight_avg, 731 (u32) (ring->prod - ring->cons - 1)); 732 733 /* Track current mbuf packet header length */ 734 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, mb->m_pkthdr.len); 735 736 /* Grab an index and try to transmit packet */ 737 owner_bit = (ring->prod & ring->size) ? 738 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0; 739 index = ring->prod & ring->size_mask; 740 tx_desc = (volatile struct mlx4_en_tx_desc *) 741 (ring->buf + index * TXBB_SIZE); 742 tx_info = &ring->tx_info[index]; 743 dseg = &tx_desc->data; 744 745 /* send a copy of the frame to the BPF listener, if any */ 746 if (ifp != NULL && ifp->if_bpf != NULL) 747 ETHER_BPF_MTAP(ifp, mb); 748 749 /* get default flags */ 750 tx_desc->ctrl.srcrb_flags = CTRL_FLAGS; 751 752 if (mb->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)) 753 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); 754 755 if (mb->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | 756 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 757 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_TCP_UDP_CSUM); 758 759 /* do statistics */ 760 if (likely(tx_desc->ctrl.srcrb_flags != CTRL_FLAGS)) { 761 priv->port_stats.tx_chksum_offload++; 762 ring->tx_csum++; 763 } 764 765 /* check for VLAN tag */ 766 if (mb->m_flags & M_VLANTAG) { 767 tx_desc->ctrl.vlan_tag = cpu_to_be16(mb->m_pkthdr.ether_vtag); 768 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN; 769 } else { 770 tx_desc->ctrl.vlan_tag = 0; 771 tx_desc->ctrl.ins_vlan = 0; 772 } 773 774 /* clear immediate field */ 775 tx_desc->ctrl.imm = 0; 776 777 /* Handle LSO (TSO) packets */ 778 if (mb->m_pkthdr.csum_flags & CSUM_TSO) { 779 u32 payload_len; 780 u32 mss = mb->m_pkthdr.tso_segsz; 781 u32 num_pkts; 782 783 opcode = cpu_to_be32(MLX4_OPCODE_LSO | MLX4_WQE_CTRL_RR) | 784 owner_bit; 785 ihs = mlx4_en_get_header_size(mb); 786 if (unlikely(ihs > MAX_INLINE)) { 787 ring->oversized_packets++; 788 err = EINVAL; 789 goto tx_drop; 790 } 791 tx_desc->lso.mss_hdr_size = cpu_to_be32((mss << 16) | ihs); 792 payload_len = mb->m_pkthdr.len - ihs; 793 if (unlikely(payload_len == 0)) 794 num_pkts = 1; 795 else 796 num_pkts = DIV_ROUND_UP(payload_len, mss); 797 ring->bytes += payload_len + (num_pkts * ihs); 798 ring->packets += num_pkts; 799 priv->port_stats.tso_packets++; 800 /* store pointer to inline header */ 801 dseg_inline = dseg; 802 /* copy data inline */ 803 dseg = mlx4_en_store_inline_lso_data(dseg, 804 mb, ihs, owner_bit); 805 } else { 806 opcode = cpu_to_be32(MLX4_OPCODE_SEND) | 807 owner_bit; 808 ihs = mlx4_en_get_inline_hdr_size(ring, mb); 809 ring->bytes += max_t (unsigned int, 810 mb->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN); 811 ring->packets++; 812 /* store pointer to inline header */ 813 dseg_inline = dseg; 814 /* copy data inline */ 815 dseg = mlx4_en_store_inline_data(dseg, 816 mb, ihs, owner_bit); 817 } 818 m_adj(mb, ihs); 819 820 /* trim off empty mbufs */ 821 while (mb->m_len == 0) { 822 mb = m_free(mb); 823 /* check if all data has been inlined */ 824 if (mb == NULL) { 825 nr_segs = 0; 826 goto skip_dma; 827 } 828 } 829 830 err = bus_dmamap_load_mbuf_sg(ring->dma_tag, tx_info->dma_map, 831 mb, segs, &nr_segs, BUS_DMA_NOWAIT); 832 if (unlikely(err == EFBIG)) { 833 /* Too many mbuf fragments */ 834 m = m_defrag(mb, M_NOWAIT); 835 if (m == NULL) { 836 ring->oversized_packets++; 837 goto tx_drop; 838 } 839 mb = m; 840 /* Try again */ 841 err = bus_dmamap_load_mbuf_sg(ring->dma_tag, tx_info->dma_map, 842 mb, segs, &nr_segs, BUS_DMA_NOWAIT); 843 } 844 /* catch errors */ 845 if (unlikely(err != 0)) { 846 ring->oversized_packets++; 847 goto tx_drop; 848 } 849 /* make sure all mbuf data is written to RAM */ 850 bus_dmamap_sync(ring->dma_tag, tx_info->dma_map, 851 BUS_DMASYNC_PREWRITE); 852 853skip_dma: 854 /* compute number of DS needed */ 855 ds_cnt = (dseg - ((volatile struct mlx4_wqe_data_seg *)tx_desc)) + nr_segs; 856 857 /* 858 * Check if the next request can wrap around and fill the end 859 * of the current request with zero immediate data: 860 */ 861 pad = DIV_ROUND_UP(ds_cnt, DS_FACT); 862 pad = (~(ring->prod + pad)) & ring->size_mask; 863 864 if (unlikely(pad < (MLX4_EN_TX_WQE_MAX_WQEBBS - 1))) { 865 /* 866 * Compute the least number of DS blocks we need to 867 * pad in order to achieve a TX ring wraparound: 868 */ 869 pad = (DS_FACT * (pad + 1)); 870 } else { 871 /* 872 * The hardware will automatically jump to the next 873 * TXBB. No need for padding. 874 */ 875 pad = 0; 876 } 877 878 /* compute total number of DS blocks */ 879 ds_cnt += pad; 880 /* 881 * When modifying this code, please ensure that the following 882 * computation is always less than or equal to 0x3F: 883 * 884 * ((MLX4_EN_TX_WQE_MAX_WQEBBS - 1) * DS_FACT) + 885 * (MLX4_EN_TX_WQE_MAX_WQEBBS * DS_FACT) 886 * 887 * Else the "ds_cnt" variable can become too big. 888 */ 889 tx_desc->ctrl.fence_size = (ds_cnt & 0x3f); 890 891 /* store pointer to mbuf */ 892 tx_info->mb = mb; 893 tx_info->nr_txbb = DIV_ROUND_UP(ds_cnt, DS_FACT); 894 bf_size = ds_cnt * DS_SIZE_ALIGNMENT; 895 bf_prod = ring->prod; 896 897 /* compute end of "dseg" array */ 898 dseg += nr_segs + pad; 899 900 /* pad using zero immediate dseg */ 901 while (pad--) { 902 dseg--; 903 dseg->addr = 0; 904 dseg->lkey = 0; 905 wmb(); 906 dseg->byte_count = SET_BYTE_COUNT((1 << 31)|0); 907 } 908 909 /* fill segment list */ 910 while (nr_segs--) { 911 if (unlikely(segs[nr_segs].ds_len == 0)) { 912 dseg--; 913 dseg->addr = 0; 914 dseg->lkey = 0; 915 wmb(); 916 dseg->byte_count = SET_BYTE_COUNT((1 << 31)|0); 917 } else { 918 dseg--; 919 dseg->addr = cpu_to_be64((uint64_t)segs[nr_segs].ds_addr); 920 dseg->lkey = cpu_to_be32(priv->mdev->mr.key); 921 wmb(); 922 dseg->byte_count = SET_BYTE_COUNT((uint32_t)segs[nr_segs].ds_len); 923 } 924 } 925 926 wmb(); 927 928 /* write owner bits in reverse order */ 929 if ((opcode & cpu_to_be32(0x1F)) == cpu_to_be32(MLX4_OPCODE_LSO)) 930 mlx4_en_store_inline_lso_header(dseg_inline, ihs, owner_bit); 931 else 932 mlx4_en_store_inline_header(dseg_inline, ihs, owner_bit); 933 934 if (unlikely(priv->validate_loopback)) { 935 /* Copy dst mac address to wqe */ 936 struct ether_header *ethh; 937 u64 mac; 938 u32 mac_l, mac_h; 939 940 ethh = mtod(mb, struct ether_header *); 941 mac = mlx4_en_mac_to_u64(ethh->ether_dhost); 942 if (mac) { 943 mac_h = (u32) ((mac & 0xffff00000000ULL) >> 16); 944 mac_l = (u32) (mac & 0xffffffff); 945 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(mac_h); 946 tx_desc->ctrl.imm = cpu_to_be32(mac_l); 947 } 948 } 949 950 /* update producer counter */ 951 ring->prod += tx_info->nr_txbb; 952 953 if (ring->bf_enabled && bf_size <= MAX_BF && 954 (tx_desc->ctrl.ins_vlan != MLX4_WQE_CTRL_INS_VLAN)) { 955 956 /* store doorbell number */ 957 *(volatile __be32 *) (&tx_desc->ctrl.vlan_tag) |= cpu_to_be32(ring->doorbell_qpn); 958 959 /* or in producer number for this WQE */ 960 opcode |= cpu_to_be32((bf_prod & 0xffff) << 8); 961 962 /* 963 * Ensure the new descriptor hits memory before 964 * setting ownership of this descriptor to HW: 965 */ 966 wmb(); 967 tx_desc->ctrl.owner_opcode = opcode; 968 wmb(); 969 mlx4_bf_copy(((u8 *)ring->bf.reg) + ring->bf.offset, 970 (volatile unsigned long *) &tx_desc->ctrl, bf_size); 971 wmb(); 972 ring->bf.offset ^= ring->bf.buf_size; 973 } else { 974 /* 975 * Ensure the new descriptor hits memory before 976 * setting ownership of this descriptor to HW: 977 */ 978 wmb(); 979 tx_desc->ctrl.owner_opcode = opcode; 980 wmb(); 981 writel(cpu_to_be32(ring->doorbell_qpn), 982 ((u8 *)ring->bf.uar->map) + MLX4_SEND_DOORBELL); 983 } 984 985 return (0); 986tx_drop: 987 *mbp = NULL; 988 m_freem(mb); 989 return (err); 990} 991 992static int 993mlx4_en_transmit_locked(struct ifnet *dev, int tx_ind, struct mbuf *m) 994{ 995 struct mlx4_en_priv *priv = netdev_priv(dev); 996 struct mlx4_en_tx_ring *ring; 997 struct mbuf *next; 998 int enqueued, err = 0; 999 1000 ring = priv->tx_ring[tx_ind]; 1001 if ((dev->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1002 IFF_DRV_RUNNING || priv->port_up == 0) { 1003 if (m != NULL) 1004 err = drbr_enqueue(dev, ring->br, m); 1005 return (err); 1006 } 1007 1008 enqueued = 0; 1009 if (m != NULL) 1010 /* 1011 * If we can't insert mbuf into drbr, try to xmit anyway. 1012 * We keep the error we got so we could return that after xmit. 1013 */ 1014 err = drbr_enqueue(dev, ring->br, m); 1015 1016 /* Process the queue */ 1017 while ((next = drbr_peek(dev, ring->br)) != NULL) { 1018 if (mlx4_en_xmit(priv, tx_ind, &next) != 0) { 1019 if (next == NULL) { 1020 drbr_advance(dev, ring->br); 1021 } else { 1022 drbr_putback(dev, ring->br, next); 1023 } 1024 break; 1025 } 1026 drbr_advance(dev, ring->br); 1027 enqueued++; 1028 if ((dev->if_drv_flags & IFF_DRV_RUNNING) == 0) 1029 break; 1030 } 1031 1032 if (enqueued > 0) 1033 ring->watchdog_time = ticks; 1034 1035 return (err); 1036} 1037 1038void 1039mlx4_en_tx_que(void *context, int pending) 1040{ 1041 struct mlx4_en_tx_ring *ring; 1042 struct mlx4_en_priv *priv; 1043 struct net_device *dev; 1044 struct mlx4_en_cq *cq; 1045 int tx_ind; 1046 cq = context; 1047 dev = cq->dev; 1048 priv = dev->if_softc; 1049 tx_ind = cq->ring; 1050 ring = priv->tx_ring[tx_ind]; 1051 1052 if (priv->port_up != 0 && 1053 (dev->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1054 mlx4_en_xmit_poll(priv, tx_ind); 1055 spin_lock(&ring->tx_lock); 1056 if (!drbr_empty(dev, ring->br)) 1057 mlx4_en_transmit_locked(dev, tx_ind, NULL); 1058 spin_unlock(&ring->tx_lock); 1059 } 1060} 1061 1062int 1063mlx4_en_transmit(struct ifnet *dev, struct mbuf *m) 1064{ 1065 struct mlx4_en_priv *priv = netdev_priv(dev); 1066 struct mlx4_en_tx_ring *ring; 1067 struct mlx4_en_cq *cq; 1068 int i, err = 0; 1069 1070 if (priv->port_up == 0) { 1071 m_freem(m); 1072 return (ENETDOWN); 1073 } 1074 1075 /* Compute which queue to use */ 1076 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) { 1077 i = (m->m_pkthdr.flowid % 128) % priv->tx_ring_num; 1078 } 1079 else { 1080 i = mlx4_en_select_queue(dev, m); 1081 } 1082 1083 ring = priv->tx_ring[i]; 1084 if (spin_trylock(&ring->tx_lock)) { 1085 err = mlx4_en_transmit_locked(dev, i, m); 1086 spin_unlock(&ring->tx_lock); 1087 /* Poll CQ here */ 1088 mlx4_en_xmit_poll(priv, i); 1089 } else { 1090 err = drbr_enqueue(dev, ring->br, m); 1091 cq = priv->tx_cq[i]; 1092 taskqueue_enqueue(cq->tq, &cq->cq_task); 1093 } 1094 1095 return (err); 1096} 1097 1098/* 1099 * Flush ring buffers. 1100 */ 1101void 1102mlx4_en_qflush(struct ifnet *dev) 1103{ 1104 struct mlx4_en_priv *priv = netdev_priv(dev); 1105 struct mlx4_en_tx_ring *ring; 1106 struct mbuf *m; 1107 1108 if (priv->port_up == 0) 1109 return; 1110 1111 for (int i = 0; i < priv->tx_ring_num; i++) { 1112 ring = priv->tx_ring[i]; 1113 spin_lock(&ring->tx_lock); 1114 while ((m = buf_ring_dequeue_sc(ring->br)) != NULL) 1115 m_freem(m); 1116 spin_unlock(&ring->tx_lock); 1117 } 1118 if_qflush(dev); 1119} 1120