1/* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006 Cisco Systems, Inc. All rights reserved. 5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37#include <linux/hardirq.h> 38#include <linux/sched.h> 39 40#include <asm/io.h> 41 42#include <rdma/ib_pack.h> 43 44#include "mthca_dev.h" 45#include "mthca_cmd.h" 46#include "mthca_memfree.h" 47 48enum { 49 MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE 50}; 51 52enum { 53 MTHCA_CQ_ENTRY_SIZE = 0x20 54}; 55 56enum { 57 MTHCA_ATOMIC_BYTE_LEN = 8 58}; 59 60/* 61 * Must be packed because start is 64 bits but only aligned to 32 bits. 62 */ 63struct mthca_cq_context { 64 __be32 flags; 65 __be64 start; 66 __be32 logsize_usrpage; 67 __be32 error_eqn; /* Tavor only */ 68 __be32 comp_eqn; 69 __be32 pd; 70 __be32 lkey; 71 __be32 last_notified_index; 72 __be32 solicit_producer_index; 73 __be32 consumer_index; 74 __be32 producer_index; 75 __be32 cqn; 76 __be32 ci_db; /* Arbel only */ 77 __be32 state_db; /* Arbel only */ 78 u32 reserved; 79} __attribute__((packed)); 80 81#define MTHCA_CQ_STATUS_OK ( 0 << 28) 82#define MTHCA_CQ_STATUS_OVERFLOW ( 9 << 28) 83#define MTHCA_CQ_STATUS_WRITE_FAIL (10 << 28) 84#define MTHCA_CQ_FLAG_TR ( 1 << 18) 85#define MTHCA_CQ_FLAG_OI ( 1 << 17) 86#define MTHCA_CQ_STATE_DISARMED ( 0 << 8) 87#define MTHCA_CQ_STATE_ARMED ( 1 << 8) 88#define MTHCA_CQ_STATE_ARMED_SOL ( 4 << 8) 89#define MTHCA_EQ_STATE_FIRED (10 << 8) 90 91enum { 92 MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe 93}; 94 95enum { 96 SYNDROME_LOCAL_LENGTH_ERR = 0x01, 97 SYNDROME_LOCAL_QP_OP_ERR = 0x02, 98 SYNDROME_LOCAL_EEC_OP_ERR = 0x03, 99 SYNDROME_LOCAL_PROT_ERR = 0x04, 100 SYNDROME_WR_FLUSH_ERR = 0x05, 101 SYNDROME_MW_BIND_ERR = 0x06, 102 SYNDROME_BAD_RESP_ERR = 0x10, 103 SYNDROME_LOCAL_ACCESS_ERR = 0x11, 104 SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12, 105 SYNDROME_REMOTE_ACCESS_ERR = 0x13, 106 SYNDROME_REMOTE_OP_ERR = 0x14, 107 SYNDROME_RETRY_EXC_ERR = 0x15, 108 SYNDROME_RNR_RETRY_EXC_ERR = 0x16, 109 SYNDROME_LOCAL_RDD_VIOL_ERR = 0x20, 110 SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21, 111 SYNDROME_REMOTE_ABORTED_ERR = 0x22, 112 SYNDROME_INVAL_EECN_ERR = 0x23, 113 SYNDROME_INVAL_EEC_STATE_ERR = 0x24 114}; 115 116struct mthca_cqe { 117 __be32 my_qpn; 118 __be32 my_ee; 119 __be32 rqpn; 120 u8 sl_ipok; 121 u8 g_mlpath; 122 __be16 rlid; 123 __be32 imm_etype_pkey_eec; 124 __be32 byte_cnt; 125 __be32 wqe; 126 u8 opcode; 127 u8 is_send; 128 u8 reserved; 129 u8 owner; 130}; 131 132struct mthca_err_cqe { 133 __be32 my_qpn; 134 u32 reserved1[3]; 135 u8 syndrome; 136 u8 vendor_err; 137 __be16 db_cnt; 138 u32 reserved2; 139 __be32 wqe; 140 u8 opcode; 141 u8 reserved3[2]; 142 u8 owner; 143}; 144 145#define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7) 146#define MTHCA_CQ_ENTRY_OWNER_HW (1 << 7) 147 148#define MTHCA_TAVOR_CQ_DB_INC_CI (1 << 24) 149#define MTHCA_TAVOR_CQ_DB_REQ_NOT (2 << 24) 150#define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL (3 << 24) 151#define MTHCA_TAVOR_CQ_DB_SET_CI (4 << 24) 152#define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24) 153 154#define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL (1 << 24) 155#define MTHCA_ARBEL_CQ_DB_REQ_NOT (2 << 24) 156#define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24) 157 158static inline struct mthca_cqe *get_cqe_from_buf(struct mthca_cq_buf *buf, 159 int entry) 160{ 161 if (buf->is_direct) 162 return buf->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE); 163 else 164 return buf->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf 165 + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE; 166} 167 168static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry) 169{ 170 return get_cqe_from_buf(&cq->buf, entry); 171} 172 173static inline struct mthca_cqe *cqe_sw(struct mthca_cqe *cqe) 174{ 175 return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe; 176} 177 178static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq) 179{ 180 return cqe_sw(get_cqe(cq, cq->cons_index & cq->ibcq.cqe)); 181} 182 183static inline void set_cqe_hw(struct mthca_cqe *cqe) 184{ 185 cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW; 186} 187 188static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr) 189{ 190 __be32 *cqe = cqe_ptr; 191 192 (void) cqe; /* avoid warning if mthca_dbg compiled away... */ 193 mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", 194 be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]), 195 be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]), 196 be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7])); 197} 198 199/* 200 * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index 201 * should be correct before calling update_cons_index(). 202 */ 203static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq, 204 int incr) 205{ 206 if (mthca_is_memfree(dev)) { 207 *cq->set_ci_db = cpu_to_be32(cq->cons_index); 208 wmb(); 209 } else { 210 mthca_write64(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn, incr - 1, 211 dev->kar + MTHCA_CQ_DOORBELL, 212 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 213 /* 214 * Make sure doorbells don't leak out of CQ spinlock 215 * and reach the HCA out of order: 216 */ 217 mmiowb(); 218 } 219} 220 221void mthca_cq_completion(struct mthca_dev *dev, u32 cqn) 222{ 223 struct mthca_cq *cq; 224 225 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1)); 226 227 if (!cq) { 228 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn); 229 return; 230 } 231 232 ++cq->arm_sn; 233 234 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 235} 236 237void mthca_cq_event(struct mthca_dev *dev, u32 cqn, 238 enum ib_event_type event_type) 239{ 240 struct mthca_cq *cq; 241 struct ib_event event; 242 243 spin_lock(&dev->cq_table.lock); 244 245 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1)); 246 if (cq) 247 ++cq->refcount; 248 249 spin_unlock(&dev->cq_table.lock); 250 251 if (!cq) { 252 mthca_warn(dev, "Async event for bogus CQ %08x\n", cqn); 253 return; 254 } 255 256 event.device = &dev->ib_dev; 257 event.event = event_type; 258 event.element.cq = &cq->ibcq; 259 if (cq->ibcq.event_handler) 260 cq->ibcq.event_handler(&event, cq->ibcq.cq_context); 261 262 spin_lock(&dev->cq_table.lock); 263 if (!--cq->refcount) 264 wake_up(&cq->wait); 265 spin_unlock(&dev->cq_table.lock); 266} 267 268static inline int is_recv_cqe(struct mthca_cqe *cqe) 269{ 270 if ((cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) == 271 MTHCA_ERROR_CQE_OPCODE_MASK) 272 return !(cqe->opcode & 0x01); 273 else 274 return !(cqe->is_send & 0x80); 275} 276 277void mthca_cq_clean(struct mthca_dev *dev, struct mthca_cq *cq, u32 qpn, 278 struct mthca_srq *srq) 279{ 280 struct mthca_cqe *cqe; 281 u32 prod_index; 282 int i, nfreed = 0; 283 284 spin_lock_irq(&cq->lock); 285 286 /* 287 * First we need to find the current producer index, so we 288 * know where to start cleaning from. It doesn't matter if HW 289 * adds new entries after this loop -- the QP we're worried 290 * about is already in RESET, so the new entries won't come 291 * from our QP and therefore don't need to be checked. 292 */ 293 for (prod_index = cq->cons_index; 294 cqe_sw(get_cqe(cq, prod_index & cq->ibcq.cqe)); 295 ++prod_index) 296 if (prod_index == cq->cons_index + cq->ibcq.cqe) 297 break; 298 299 if (0) 300 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n", 301 qpn, cq->cqn, cq->cons_index, prod_index); 302 303 /* 304 * Now sweep backwards through the CQ, removing CQ entries 305 * that match our QP by copying older entries on top of them. 306 */ 307 while ((int) --prod_index - (int) cq->cons_index >= 0) { 308 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 309 if (cqe->my_qpn == cpu_to_be32(qpn)) { 310 if (srq && is_recv_cqe(cqe)) 311 mthca_free_srq_wqe(srq, be32_to_cpu(cqe->wqe)); 312 ++nfreed; 313 } else if (nfreed) 314 memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe), 315 cqe, MTHCA_CQ_ENTRY_SIZE); 316 } 317 318 if (nfreed) { 319 for (i = 0; i < nfreed; ++i) 320 set_cqe_hw(get_cqe(cq, (cq->cons_index + i) & cq->ibcq.cqe)); 321 wmb(); 322 cq->cons_index += nfreed; 323 update_cons_index(dev, cq, nfreed); 324 } 325 326 spin_unlock_irq(&cq->lock); 327} 328 329void mthca_cq_resize_copy_cqes(struct mthca_cq *cq) 330{ 331 int i; 332 333 /* 334 * In Tavor mode, the hardware keeps the consumer and producer 335 * indices mod the CQ size. Since we might be making the CQ 336 * bigger, we need to deal with the case where the producer 337 * index wrapped around before the CQ was resized. 338 */ 339 if (!mthca_is_memfree(to_mdev(cq->ibcq.device)) && 340 cq->ibcq.cqe < cq->resize_buf->cqe) { 341 cq->cons_index &= cq->ibcq.cqe; 342 if (cqe_sw(get_cqe(cq, cq->ibcq.cqe))) 343 cq->cons_index -= cq->ibcq.cqe + 1; 344 } 345 346 for (i = cq->cons_index; cqe_sw(get_cqe(cq, i & cq->ibcq.cqe)); ++i) 347 memcpy(get_cqe_from_buf(&cq->resize_buf->buf, 348 i & cq->resize_buf->cqe), 349 get_cqe(cq, i & cq->ibcq.cqe), MTHCA_CQ_ENTRY_SIZE); 350} 351 352int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent) 353{ 354 int ret; 355 int i; 356 357 ret = mthca_buf_alloc(dev, nent * MTHCA_CQ_ENTRY_SIZE, 358 MTHCA_MAX_DIRECT_CQ_SIZE, 359 &buf->queue, &buf->is_direct, 360 &dev->driver_pd, 1, &buf->mr); 361 if (ret) 362 return ret; 363 364 for (i = 0; i < nent; ++i) 365 set_cqe_hw(get_cqe_from_buf(buf, i)); 366 367 return 0; 368} 369 370void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe) 371{ 372 mthca_buf_free(dev, (cqe + 1) * MTHCA_CQ_ENTRY_SIZE, &buf->queue, 373 buf->is_direct, &buf->mr); 374} 375 376static void handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq, 377 struct mthca_qp *qp, int wqe_index, int is_send, 378 struct mthca_err_cqe *cqe, 379 struct ib_wc *entry, int *free_cqe) 380{ 381 int dbd; 382 __be32 new_wqe; 383 384 if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) { 385 mthca_dbg(dev, "local QP operation err " 386 "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n", 387 be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe), 388 cq->cqn, cq->cons_index); 389 dump_cqe(dev, cqe); 390 } 391 392 /* 393 * For completions in error, only work request ID, status, vendor error 394 * (and freed resource count for RD) have to be set. 395 */ 396 switch (cqe->syndrome) { 397 case SYNDROME_LOCAL_LENGTH_ERR: 398 entry->status = IB_WC_LOC_LEN_ERR; 399 break; 400 case SYNDROME_LOCAL_QP_OP_ERR: 401 entry->status = IB_WC_LOC_QP_OP_ERR; 402 break; 403 case SYNDROME_LOCAL_EEC_OP_ERR: 404 entry->status = IB_WC_LOC_EEC_OP_ERR; 405 break; 406 case SYNDROME_LOCAL_PROT_ERR: 407 entry->status = IB_WC_LOC_PROT_ERR; 408 break; 409 case SYNDROME_WR_FLUSH_ERR: 410 entry->status = IB_WC_WR_FLUSH_ERR; 411 break; 412 case SYNDROME_MW_BIND_ERR: 413 entry->status = IB_WC_MW_BIND_ERR; 414 break; 415 case SYNDROME_BAD_RESP_ERR: 416 entry->status = IB_WC_BAD_RESP_ERR; 417 break; 418 case SYNDROME_LOCAL_ACCESS_ERR: 419 entry->status = IB_WC_LOC_ACCESS_ERR; 420 break; 421 case SYNDROME_REMOTE_INVAL_REQ_ERR: 422 entry->status = IB_WC_REM_INV_REQ_ERR; 423 break; 424 case SYNDROME_REMOTE_ACCESS_ERR: 425 entry->status = IB_WC_REM_ACCESS_ERR; 426 break; 427 case SYNDROME_REMOTE_OP_ERR: 428 entry->status = IB_WC_REM_OP_ERR; 429 break; 430 case SYNDROME_RETRY_EXC_ERR: 431 entry->status = IB_WC_RETRY_EXC_ERR; 432 break; 433 case SYNDROME_RNR_RETRY_EXC_ERR: 434 entry->status = IB_WC_RNR_RETRY_EXC_ERR; 435 break; 436 case SYNDROME_LOCAL_RDD_VIOL_ERR: 437 entry->status = IB_WC_LOC_RDD_VIOL_ERR; 438 break; 439 case SYNDROME_REMOTE_INVAL_RD_REQ_ERR: 440 entry->status = IB_WC_REM_INV_RD_REQ_ERR; 441 break; 442 case SYNDROME_REMOTE_ABORTED_ERR: 443 entry->status = IB_WC_REM_ABORT_ERR; 444 break; 445 case SYNDROME_INVAL_EECN_ERR: 446 entry->status = IB_WC_INV_EECN_ERR; 447 break; 448 case SYNDROME_INVAL_EEC_STATE_ERR: 449 entry->status = IB_WC_INV_EEC_STATE_ERR; 450 break; 451 default: 452 entry->status = IB_WC_GENERAL_ERR; 453 break; 454 } 455 456 entry->vendor_err = cqe->vendor_err; 457 458 /* 459 * Mem-free HCAs always generate one CQE per WQE, even in the 460 * error case, so we don't have to check the doorbell count, etc. 461 */ 462 if (mthca_is_memfree(dev)) 463 return; 464 465 mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe); 466 467 /* 468 * If we're at the end of the WQE chain, or we've used up our 469 * doorbell count, free the CQE. Otherwise just update it for 470 * the next poll operation. 471 */ 472 if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd)) 473 return; 474 475 be16_add_cpu(&cqe->db_cnt, -dbd); 476 cqe->wqe = new_wqe; 477 cqe->syndrome = SYNDROME_WR_FLUSH_ERR; 478 479 *free_cqe = 0; 480} 481 482static inline int mthca_poll_one(struct mthca_dev *dev, 483 struct mthca_cq *cq, 484 struct mthca_qp **cur_qp, 485 int *freed, 486 struct ib_wc *entry) 487{ 488 struct mthca_wq *wq; 489 struct mthca_cqe *cqe; 490 int wqe_index; 491 int is_error; 492 int is_send; 493 int free_cqe = 1; 494 int err = 0; 495 u16 checksum; 496 497 cqe = next_cqe_sw(cq); 498 if (!cqe) 499 return -EAGAIN; 500 501 /* 502 * Make sure we read CQ entry contents after we've checked the 503 * ownership bit. 504 */ 505 rmb(); 506 507 if (0) { 508 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n", 509 cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn), 510 be32_to_cpu(cqe->wqe)); 511 dump_cqe(dev, cqe); 512 } 513 514 is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) == 515 MTHCA_ERROR_CQE_OPCODE_MASK; 516 is_send = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80; 517 518 if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) { 519 /* 520 * We do not have to take the QP table lock here, 521 * because CQs will be locked while QPs are removed 522 * from the table. 523 */ 524 *cur_qp = mthca_array_get(&dev->qp_table.qp, 525 be32_to_cpu(cqe->my_qpn) & 526 (dev->limits.num_qps - 1)); 527 if (!*cur_qp) { 528 mthca_warn(dev, "CQ entry for unknown QP %06x\n", 529 be32_to_cpu(cqe->my_qpn) & 0xffffff); 530 err = -EINVAL; 531 goto out; 532 } 533 } 534 535 entry->qp = &(*cur_qp)->ibqp; 536 537 if (is_send) { 538 wq = &(*cur_qp)->sq; 539 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset) 540 >> wq->wqe_shift); 541 entry->wr_id = (*cur_qp)->wrid[wqe_index]; 542 } else if ((*cur_qp)->ibqp.srq) { 543 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq); 544 u32 wqe = be32_to_cpu(cqe->wqe); 545 wq = NULL; 546 wqe_index = wqe >> srq->wqe_shift; 547 entry->wr_id = srq->wrid[wqe_index]; 548 mthca_free_srq_wqe(srq, wqe); 549 } else { 550 s32 wqe; 551 wq = &(*cur_qp)->rq; 552 wqe = be32_to_cpu(cqe->wqe); 553 wqe_index = wqe >> wq->wqe_shift; 554 /* 555 * WQE addr == base - 1 might be reported in receive completion 556 * with error instead of (rq size - 1) by Sinai FW 1.0.800 and 557 * Arbel FW 5.1.400. This bug should be fixed in later FW revs. 558 */ 559 if (unlikely(wqe_index < 0)) 560 wqe_index = wq->max - 1; 561 entry->wr_id = (*cur_qp)->wrid[wqe_index + (*cur_qp)->sq.max]; 562 } 563 564 if (wq) { 565 if (wq->last_comp < wqe_index) 566 wq->tail += wqe_index - wq->last_comp; 567 else 568 wq->tail += wqe_index + wq->max - wq->last_comp; 569 570 wq->last_comp = wqe_index; 571 } 572 573 if (is_error) { 574 handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send, 575 (struct mthca_err_cqe *) cqe, 576 entry, &free_cqe); 577 goto out; 578 } 579 580 if (is_send) { 581 entry->wc_flags = 0; 582 switch (cqe->opcode) { 583 case MTHCA_OPCODE_RDMA_WRITE: 584 entry->opcode = IB_WC_RDMA_WRITE; 585 break; 586 case MTHCA_OPCODE_RDMA_WRITE_IMM: 587 entry->opcode = IB_WC_RDMA_WRITE; 588 entry->wc_flags |= IB_WC_WITH_IMM; 589 break; 590 case MTHCA_OPCODE_SEND: 591 entry->opcode = IB_WC_SEND; 592 break; 593 case MTHCA_OPCODE_SEND_IMM: 594 entry->opcode = IB_WC_SEND; 595 entry->wc_flags |= IB_WC_WITH_IMM; 596 break; 597 case MTHCA_OPCODE_RDMA_READ: 598 entry->opcode = IB_WC_RDMA_READ; 599 entry->byte_len = be32_to_cpu(cqe->byte_cnt); 600 break; 601 case MTHCA_OPCODE_ATOMIC_CS: 602 entry->opcode = IB_WC_COMP_SWAP; 603 entry->byte_len = MTHCA_ATOMIC_BYTE_LEN; 604 break; 605 case MTHCA_OPCODE_ATOMIC_FA: 606 entry->opcode = IB_WC_FETCH_ADD; 607 entry->byte_len = MTHCA_ATOMIC_BYTE_LEN; 608 break; 609 case MTHCA_OPCODE_BIND_MW: 610 entry->opcode = IB_WC_BIND_MW; 611 break; 612 default: 613 entry->opcode = MTHCA_OPCODE_INVALID; 614 break; 615 } 616 } else { 617 entry->byte_len = be32_to_cpu(cqe->byte_cnt); 618 switch (cqe->opcode & 0x1f) { 619 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE: 620 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE: 621 entry->wc_flags = IB_WC_WITH_IMM; 622 entry->ex.imm_data = cqe->imm_etype_pkey_eec; 623 entry->opcode = IB_WC_RECV; 624 break; 625 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE: 626 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE: 627 entry->wc_flags = IB_WC_WITH_IMM; 628 entry->ex.imm_data = cqe->imm_etype_pkey_eec; 629 entry->opcode = IB_WC_RECV_RDMA_WITH_IMM; 630 break; 631 default: 632 entry->wc_flags = 0; 633 entry->opcode = IB_WC_RECV; 634 break; 635 } 636 entry->slid = be16_to_cpu(cqe->rlid); 637 entry->sl = cqe->sl_ipok >> 4; 638 entry->src_qp = be32_to_cpu(cqe->rqpn) & 0xffffff; 639 entry->dlid_path_bits = cqe->g_mlpath & 0x7f; 640 entry->pkey_index = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16; 641 entry->wc_flags |= cqe->g_mlpath & 0x80 ? IB_WC_GRH : 0; 642 checksum = (be32_to_cpu(cqe->rqpn) >> 24) | 643 ((be32_to_cpu(cqe->my_ee) >> 16) & 0xff00); 644 entry->csum_ok = (cqe->sl_ipok & 1 && checksum == 0xffff); 645 } 646 647 entry->status = IB_WC_SUCCESS; 648 649 out: 650 if (likely(free_cqe)) { 651 set_cqe_hw(cqe); 652 ++(*freed); 653 ++cq->cons_index; 654 } 655 656 return err; 657} 658 659int mthca_poll_cq(struct ib_cq *ibcq, int num_entries, 660 struct ib_wc *entry) 661{ 662 struct mthca_dev *dev = to_mdev(ibcq->device); 663 struct mthca_cq *cq = to_mcq(ibcq); 664 struct mthca_qp *qp = NULL; 665 unsigned long flags; 666 int err = 0; 667 int freed = 0; 668 int npolled; 669 670 spin_lock_irqsave(&cq->lock, flags); 671 672 npolled = 0; 673repoll: 674 while (npolled < num_entries) { 675 err = mthca_poll_one(dev, cq, &qp, 676 &freed, entry + npolled); 677 if (err) 678 break; 679 ++npolled; 680 } 681 682 if (freed) { 683 wmb(); 684 update_cons_index(dev, cq, freed); 685 } 686 687 /* 688 * If a CQ resize is in progress and we discovered that the 689 * old buffer is empty, then peek in the new buffer, and if 690 * it's not empty, switch to the new buffer and continue 691 * polling there. 692 */ 693 if (unlikely(err == -EAGAIN && cq->resize_buf && 694 cq->resize_buf->state == CQ_RESIZE_READY)) { 695 /* 696 * In Tavor mode, the hardware keeps the producer 697 * index modulo the CQ size. Since we might be making 698 * the CQ bigger, we need to mask our consumer index 699 * using the size of the old CQ buffer before looking 700 * in the new CQ buffer. 701 */ 702 if (!mthca_is_memfree(dev)) 703 cq->cons_index &= cq->ibcq.cqe; 704 705 if (cqe_sw(get_cqe_from_buf(&cq->resize_buf->buf, 706 cq->cons_index & cq->resize_buf->cqe))) { 707 struct mthca_cq_buf tbuf; 708 int tcqe; 709 710 tbuf = cq->buf; 711 tcqe = cq->ibcq.cqe; 712 cq->buf = cq->resize_buf->buf; 713 cq->ibcq.cqe = cq->resize_buf->cqe; 714 715 cq->resize_buf->buf = tbuf; 716 cq->resize_buf->cqe = tcqe; 717 cq->resize_buf->state = CQ_RESIZE_SWAPPED; 718 719 goto repoll; 720 } 721 } 722 723 spin_unlock_irqrestore(&cq->lock, flags); 724 725 return err == 0 || err == -EAGAIN ? npolled : err; 726} 727 728int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags) 729{ 730 u32 dbhi = ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 731 MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL : 732 MTHCA_TAVOR_CQ_DB_REQ_NOT) | 733 to_mcq(cq)->cqn; 734 735 mthca_write64(dbhi, 0xffffffff, to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL, 736 MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock)); 737 738 return 0; 739} 740 741int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 742{ 743 struct mthca_cq *cq = to_mcq(ibcq); 744 __be32 db_rec[2]; 745 u32 dbhi; 746 u32 sn = cq->arm_sn & 3; 747 748 db_rec[0] = cpu_to_be32(cq->cons_index); 749 db_rec[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) | 750 ((flags & IB_CQ_SOLICITED_MASK) == 751 IB_CQ_SOLICITED ? 1 : 2)); 752 753 mthca_write_db_rec(db_rec, cq->arm_db); 754 755 /* 756 * Make sure that the doorbell record in host memory is 757 * written before ringing the doorbell via PCI MMIO. 758 */ 759 wmb(); 760 761 dbhi = (sn << 28) | 762 ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 763 MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL : 764 MTHCA_ARBEL_CQ_DB_REQ_NOT) | cq->cqn; 765 766 mthca_write64(dbhi, cq->cons_index, 767 to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL, 768 MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock)); 769 770 return 0; 771} 772 773int mthca_init_cq(struct mthca_dev *dev, int nent, 774 struct mthca_ucontext *ctx, u32 pdn, 775 struct mthca_cq *cq) 776{ 777 struct mthca_mailbox *mailbox; 778 struct mthca_cq_context *cq_context; 779 int err = -ENOMEM; 780 u8 status; 781 782 cq->ibcq.cqe = nent - 1; 783 cq->is_kernel = !ctx; 784 785 cq->cqn = mthca_alloc(&dev->cq_table.alloc); 786 if (cq->cqn == -1) 787 return -ENOMEM; 788 789 if (mthca_is_memfree(dev)) { 790 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn); 791 if (err) 792 goto err_out; 793 794 if (cq->is_kernel) { 795 cq->arm_sn = 1; 796 797 err = -ENOMEM; 798 799 cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, 800 cq->cqn, &cq->set_ci_db); 801 if (cq->set_ci_db_index < 0) 802 goto err_out_icm; 803 804 cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM, 805 cq->cqn, &cq->arm_db); 806 if (cq->arm_db_index < 0) 807 goto err_out_ci; 808 } 809 } 810 811 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 812 if (IS_ERR(mailbox)) 813 goto err_out_arm; 814 815 cq_context = mailbox->buf; 816 817 if (cq->is_kernel) { 818 err = mthca_alloc_cq_buf(dev, &cq->buf, nent); 819 if (err) 820 goto err_out_mailbox; 821 } 822 823 spin_lock_init(&cq->lock); 824 cq->refcount = 1; 825 init_waitqueue_head(&cq->wait); 826 mutex_init(&cq->mutex); 827 828 memset(cq_context, 0, sizeof *cq_context); 829 cq_context->flags = cpu_to_be32(MTHCA_CQ_STATUS_OK | 830 MTHCA_CQ_STATE_DISARMED | 831 MTHCA_CQ_FLAG_TR); 832 cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24); 833 if (ctx) 834 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index); 835 else 836 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index); 837 cq_context->error_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn); 838 cq_context->comp_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn); 839 cq_context->pd = cpu_to_be32(pdn); 840 cq_context->lkey = cpu_to_be32(cq->buf.mr.ibmr.lkey); 841 cq_context->cqn = cpu_to_be32(cq->cqn); 842 843 if (mthca_is_memfree(dev)) { 844 cq_context->ci_db = cpu_to_be32(cq->set_ci_db_index); 845 cq_context->state_db = cpu_to_be32(cq->arm_db_index); 846 } 847 848 err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status); 849 if (err) { 850 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err); 851 goto err_out_free_mr; 852 } 853 854 if (status) { 855 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n", 856 status); 857 err = -EINVAL; 858 goto err_out_free_mr; 859 } 860 861 spin_lock_irq(&dev->cq_table.lock); 862 if (mthca_array_set(&dev->cq_table.cq, 863 cq->cqn & (dev->limits.num_cqs - 1), 864 cq)) { 865 spin_unlock_irq(&dev->cq_table.lock); 866 goto err_out_free_mr; 867 } 868 spin_unlock_irq(&dev->cq_table.lock); 869 870 cq->cons_index = 0; 871 872 mthca_free_mailbox(dev, mailbox); 873 874 return 0; 875 876err_out_free_mr: 877 if (cq->is_kernel) 878 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 879 880err_out_mailbox: 881 mthca_free_mailbox(dev, mailbox); 882 883err_out_arm: 884 if (cq->is_kernel && mthca_is_memfree(dev)) 885 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index); 886 887err_out_ci: 888 if (cq->is_kernel && mthca_is_memfree(dev)) 889 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index); 890 891err_out_icm: 892 mthca_table_put(dev, dev->cq_table.table, cq->cqn); 893 894err_out: 895 mthca_free(&dev->cq_table.alloc, cq->cqn); 896 897 return err; 898} 899 900static inline int get_cq_refcount(struct mthca_dev *dev, struct mthca_cq *cq) 901{ 902 int c; 903 904 spin_lock_irq(&dev->cq_table.lock); 905 c = cq->refcount; 906 spin_unlock_irq(&dev->cq_table.lock); 907 908 return c; 909} 910 911void mthca_free_cq(struct mthca_dev *dev, 912 struct mthca_cq *cq) 913{ 914 struct mthca_mailbox *mailbox; 915 int err; 916 u8 status; 917 918 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 919 if (IS_ERR(mailbox)) { 920 mthca_warn(dev, "No memory for mailbox to free CQ.\n"); 921 return; 922 } 923 924 err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status); 925 if (err) 926 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err); 927 else if (status) 928 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status); 929 930 if (0) { 931 __be32 *ctx = mailbox->buf; 932 int j; 933 934 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n", 935 cq->cqn, cq->cons_index, 936 cq->is_kernel ? !!next_cqe_sw(cq) : 0); 937 for (j = 0; j < 16; ++j) 938 printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j])); 939 } 940 941 spin_lock_irq(&dev->cq_table.lock); 942 mthca_array_clear(&dev->cq_table.cq, 943 cq->cqn & (dev->limits.num_cqs - 1)); 944 --cq->refcount; 945 spin_unlock_irq(&dev->cq_table.lock); 946 947 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) 948 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector); 949 else 950 synchronize_irq(dev->pdev->irq); 951 952 wait_event(cq->wait, !get_cq_refcount(dev, cq)); 953 954 if (cq->is_kernel) { 955 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 956 if (mthca_is_memfree(dev)) { 957 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index); 958 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index); 959 } 960 } 961 962 mthca_table_put(dev, dev->cq_table.table, cq->cqn); 963 mthca_free(&dev->cq_table.alloc, cq->cqn); 964 mthca_free_mailbox(dev, mailbox); 965} 966 967int mthca_init_cq_table(struct mthca_dev *dev) 968{ 969 int err; 970 971 spin_lock_init(&dev->cq_table.lock); 972 973 err = mthca_alloc_init(&dev->cq_table.alloc, 974 dev->limits.num_cqs, 975 (1 << 24) - 1, 976 dev->limits.reserved_cqs); 977 if (err) 978 return err; 979 980 err = mthca_array_init(&dev->cq_table.cq, 981 dev->limits.num_cqs); 982 if (err) 983 mthca_alloc_cleanup(&dev->cq_table.alloc); 984 985 return err; 986} 987 988void mthca_cleanup_cq_table(struct mthca_dev *dev) 989{ 990 mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs); 991 mthca_alloc_cleanup(&dev->cq_table.alloc); 992} 993