1220297Sadrian/*- 2292699Sadrian * Copyright (c) 2015 Stanislav Galabov. 3220297Sadrian * Copyright (c) 2010 Aleksandr Rybalko. 4220297Sadrian * All rights reserved. 5220297Sadrian * 6220297Sadrian * Redistribution and use in source and binary forms, with or without 7220297Sadrian * modification, are permitted provided that the following conditions 8220297Sadrian * are met: 9220297Sadrian * 1. Redistributions of source code must retain the above copyright 10220297Sadrian * notice, this list of conditions and the following disclaimer. 11220297Sadrian * 2. Redistributions in binary form must reproduce the above copyright 12220297Sadrian * notice, this list of conditions and the following disclaimer in the 13220297Sadrian * documentation and/or other materials provided with the distribution. 14220297Sadrian * 15220297Sadrian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16220297Sadrian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17220297Sadrian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18220297Sadrian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19220297Sadrian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20220297Sadrian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21220297Sadrian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22220297Sadrian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23220297Sadrian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24220297Sadrian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25220297Sadrian * SUCH DAMAGE. 26220297Sadrian * 27220297Sadrian * $FreeBSD: releng/11.0/sys/mips/rt305x/rt305xreg.h 292699 2015-12-24 18:31:55Z adrian $ 28220297Sadrian */ 29220297Sadrian 30220297Sadrian#ifndef _RT305XREG_H_ 31220297Sadrian#define _RT305XREG_H_ 32220297Sadrian 33292699Sadrian#include "opt_rt305x.h" 34220297Sadrian 35220297Sadrian#ifdef RT3052F 36220297Sadrian#define PLATFORM_COUNTER_FREQ (384 * 1000 * 1000) 37220297Sadrian#endif 38220297Sadrian#ifdef RT3050F 39220297Sadrian#define PLATFORM_COUNTER_FREQ (320 * 1000 * 1000) 40220297Sadrian#endif 41292699Sadrian#ifdef MT7620 42292699Sadrian#define PLATFORM_COUNTER_FREQ (580 * 1000 * 1000) 43292699Sadrian#endif 44292699Sadrian#ifdef RT5350 45292699Sadrian#define PLATFORM_COUNTER_FREQ (360 * 1000 * 1000) 46292699Sadrian#endif 47220297Sadrian#ifndef PLATFORM_COUNTER_FREQ 48292699Sadrian#error "No platform selected" 49220297Sadrian#endif 50220297Sadrian 51292699Sadrian#ifndef MT7620 52292699Sadrian 53220297Sadrian#define SYSTEM_CLOCK (PLATFORM_COUNTER_FREQ/3) 54220297Sadrian 55220297Sadrian#define SDRAM_BASE 0x00000000 56220297Sadrian#define SDRAM_END 0x03FFFFFF 57220297Sadrian 58220297Sadrian#define SYSCTL_BASE 0x10000000 59220297Sadrian#define SYSCTL_END 0x100000FF 60220297Sadrian#define TIMER_BASE 0x10000100 61220297Sadrian#define TIMER_END 0x100001FF 62220297Sadrian#define INTCTL_BASE 0x10000200 63220297Sadrian#define INTCTL_END 0x100002FF 64220297Sadrian#define MEMCTRL_BASE 0x10000300 65220297Sadrian#define MEMCTRL_END 0x100003FF /* SDRAM & Flash/SRAM */ 66292699Sadrian#ifndef RT5350 67220297Sadrian#define PCM_BASE 0x10000400 68220297Sadrian#define PCM_END 0x100004FF 69292699Sadrian#else 70292699Sadrian#define PCM_BASE 0x10002000 71292699Sadrian#define PCM_END 0x100027FF 72292699Sadrian#endif 73220297Sadrian#define UART_BASE 0x10000500 74220297Sadrian#define UART_END 0x100005FF 75220297Sadrian#define PIO_BASE 0x10000600 76220297Sadrian#define PIO_END 0x100006FF 77292699Sadrian#ifndef RT5350 78220297Sadrian#define GDMA_BASE 0x10000700 79220297Sadrian#define GDMA_END 0x100007FF /* Generic DMA */ 80220297Sadrian#define NANDFC_BASE 0x10000800 81220297Sadrian#define NANDFC_END 0x100008FF /* NAND Flash Controller */ 82292699Sadrian#else 83292699Sadrian#define GDMA_BASE 0x10002800 84292699Sadrian#define GDMA_END 0x10002FFF 85292699Sadrian#endif 86220297Sadrian#define I2C_BASE 0x10000900 87220297Sadrian#define I2C_END 0x100009FF 88220297Sadrian#define I2S_BASE 0x10000A00 89220297Sadrian#define I2S_END 0x10000AFF 90220297Sadrian#define SPI_BASE 0x10000B00 91220297Sadrian#define SPI_END 0x10000BFF 92220297Sadrian#define UARTLITE_BASE 0x10000C00 93220297Sadrian#define UARTLITE_END 0x10000CFF 94220297Sadrian 95220297Sadrian#define FRENG_BASE 0x10100000 96220297Sadrian#define FRENG_END 0x1010FFFF /* Frame Engine */ 97220297Sadrian#define ETHSW_BASE 0x10110000 98220297Sadrian#define ETHSW_END 0x10117FFF /* Ethernet Switch */ 99220297Sadrian#define ROM_BASE 0x10118000 100220297Sadrian#define ROM_END 0x10119FFF 101220297Sadrian#define WLAN_BASE 0x10180000 102220297Sadrian#define WLAN_END 0x101BFFFF /* 802.11n MAC/BBP */ 103292699Sadrian#ifndef RT5350 104220297Sadrian#define USB_OTG_BASE 0x101C0000 105220297Sadrian#define USB_OTG_END 0x101FFFFF 106292699Sadrian#else 107292699Sadrian#define USB_OTG_BASE 0x101C0000 108292699Sadrian#define USB_OTG_END 0x101C0FFF 109292699Sadrian#define USB_OHCI_BASE 0x101C1000 110292699Sadrian#define USB_OHCI_END 0x101C1FFF 111292699Sadrian#endif 112220297Sadrian#define EMEM_BASE 0x1B000000 113220297Sadrian#define EMEM_END 0x1BFFFFFF /* External SRAM/Flash */ 114292699Sadrian#ifdef RT5350 115292699Sadrian#define BOOT_ROM_BASE 0x1C000000 116292699Sadrian#define BOOT_ROM_END 0x1C003FFF 117292699Sadrian#endif 118292699Sadrian#ifndef RT5350 119220297Sadrian#define FLASH_BASE 0x1F000000 120220297Sadrian#define FLASH_END 0x1FFFFFFF /* Flash window */ 121292699Sadrian#endif 122220297Sadrian 123220297Sadrian#define OBIO_MEM_BASE SYSCTL_BASE 124220297Sadrian#define OBIO_MEM_START OBIO_MEM_BASE 125292699Sadrian#ifndef RT5350 126220297Sadrian#define OBIO_MEM_END FLASH_END 127292699Sadrian#else 128292699Sadrian#define OBIO_MEM_END BOOT_ROM_END 129292699Sadrian#endif 130220297Sadrian 131292699Sadrian#else /* MT7620 */ 132220297Sadrian 133292699Sadrian#define SYSTEM_CLOCK (40 * 1000 * 1000) 134220297Sadrian 135292699Sadrian#define SDRAM_BASE 0x00000000 136292699Sadrian#define SDRAM_END 0x0FFFFFFF 137292699Sadrian 138292699Sadrian#define SYSCTL_BASE 0x10000000 139292699Sadrian#define SYSCTL_END 0x100000FF 140292699Sadrian#define TIMER_BASE 0x10000100 141292699Sadrian#define TIMER_END 0x100001FF 142292699Sadrian#define INTCTL_BASE 0x10000200 143292699Sadrian#define INTCTL_END 0x100002FF 144292699Sadrian#define MEMCTRL_BASE 0x10000300 145292699Sadrian#define MEMCTRL_END 0x100003FF /* SDRAM & Flash/SRAM */ 146292699Sadrian#define PCM_BASE 0x10002000 147292699Sadrian#define PCM_END 0x100027FF 148292699Sadrian#define UART_BASE 0x10000500 149292699Sadrian#define UART_END 0x100005FF 150292699Sadrian#define PIO_BASE 0x10000600 151292699Sadrian#define PIO_END 0x100006FF 152292699Sadrian#define GDMA_BASE 0x10002800 153292699Sadrian#define GDMA_END 0x10002FFF /* Generic DMA */ 154292699Sadrian#define NANDFC_BASE 0x10000800 155292699Sadrian#define NANDFC_END 0x100008FF /* NAND Flash Controller */ 156292699Sadrian#define I2C_BASE 0x10000900 157292699Sadrian#define I2C_END 0x100009FF 158292699Sadrian#define I2S_BASE 0x10000A00 159292699Sadrian#define I2S_END 0x10000AFF 160292699Sadrian#define SPI_BASE 0x10000B00 161292699Sadrian#define SPI_END 0x10000BFF 162292699Sadrian#define UARTLITE_BASE 0x10000C00 163292699Sadrian#define UARTLITE_END 0x10000CFF 164292699Sadrian 165292699Sadrian#define FRENG_BASE 0x10100000 166292699Sadrian#define FRENG_END 0x1010FFFF /* Frame Engine */ 167292699Sadrian#define ETHSW_BASE 0x10110000 168292699Sadrian#define ETHSW_END 0x10117FFF /* Ethernet Switch */ 169292699Sadrian#define ROM_BASE 0x10118000 170292699Sadrian#define ROM_END 0x1011FFFF 171292699Sadrian#define WLAN_BASE 0x10180000 172292699Sadrian#define WLAN_END 0x101BFFFF /* 802.11n MAC/BBP */ 173292699Sadrian#define USB_OTG_BASE 0x101C0000 174292699Sadrian#define USB_OTG_END 0x101C0FFF 175292699Sadrian#define USB_OHCI_BASE 0x101C1000 176292699Sadrian#define USB_OHCI_END 0x101C1FFF 177292699Sadrian#define PCIE_BASE 0x10140000 178292699Sadrian#define PCIE_END 0x1017FFFF 179292699Sadrian#define SDHC_BASE 0x10130000 180292699Sadrian#define SDHC_END 0x10133FFF 181292699Sadrian 182292699Sadrian#define PCIE_IO_BASE 0x10160000 183292699Sadrian#define PCIE_IO_END 0x1016FFFF 184292699Sadrian#define PCIE_MEM_BASE 0x20000000 185292699Sadrian#define PCIE_MEM_END 0x2FFFFFFF 186292699Sadrian 187292699Sadrian// TODO: fix below mappings? 188292699Sadrian#define EMEM_BASE 0x1B000000 189292699Sadrian#define EMEM_END 0x1BFFFFFF /* External SRAM/Flash */ 190292699Sadrian#define FLASH_BASE 0x1F000000 191292699Sadrian#define FLASH_END 0x1FFFFFFF /* Flash window */ 192292699Sadrian 193292699Sadrian#define OBIO_MEM_BASE SYSCTL_BASE 194292699Sadrian#define OBIO_MEM_START OBIO_MEM_BASE 195292699Sadrian#define OBIO_MEM_END FLASH_END 196292699Sadrian#endif 197292699Sadrian 198220297Sadrian/* System Control */ 199292699Sadrian#define SYSCTL_CHIPID0_3 0x00 200292699Sadrian#define SYSCTL_CHIPID4_7 0x04 201292699Sadrian#ifdef RT5350 202292699Sadrian#define SYSCTL_REVID 0x0C 203292699Sadrian#endif 204292699Sadrian 205220297Sadrian#define SYSCTL_SYSCFG 0x10 206292699Sadrian#if !defined(RT5350) && !defined(MT7620) 207220297Sadrian#define SYSCTL_SYSCFG_INIC_EE_SDRAM (1<<29) 208220297Sadrian#define SYSCTL_SYSCFG_INIC_8MB_SDRAM (1<<28) 209220297Sadrian#define SYSCTL_SYSCFG_GE0_MODE_MASK 0x03000000 210220297Sadrian#define SYSCTL_SYSCFG_GE0_MODE_SHIFT 24 211220297Sadrian#define SYSCTL_SYSCFG_GE0_MODE_RGMII 0 /* RGMII Mode */ 212220297Sadrian#define SYSCTL_SYSCFG_GE0_MODE_MII 1 /* MII Mode */ 213220297Sadrian#define SYSCTL_SYSCFG_GE0_MODE_REV_MII 2 /*Reversed MII Mode*/ 214220297Sadrian#define SYSCTL_SYSCFG_BOOT_ADDR_1F00 (1<<22) 215220297Sadrian#define SYSCTL_SYSCFG_BYPASS_PLL (1<<21) 216220297Sadrian#define SYSCTL_SYSCFG_BIG_ENDIAN (1<<20) 217220297Sadrian#define SYSCTL_SYSCFG_CPU_CLK_SEL_384MHZ (1<<18) 218220297Sadrian#define SYSCTL_SYSCFG_BOOT_FROM_MASK 0x00030000 219220297Sadrian#define SYSCTL_SYSCFG_BOOT_FROM_SHIFT 16 220220297Sadrian#define SYSCTL_SYSCFG_BOOT_FROM_FLASH16 0 221220297Sadrian#define SYSCTL_SYSCFG_BOOT_FROM_FLASH8 1 222220297Sadrian#define SYSCTL_SYSCFG_BOOT_FROM_NANDFLASH 2 223220297Sadrian#define SYSCTL_SYSCFG_BOOT_FROM_ROM 3 224220297Sadrian#define SYSCTL_SYSCFG_TEST_CODE_MASK 0x0000ff00 225220297Sadrian#define SYSCTL_SYSCFG_TEST_CODE_SHIFT 8 226220297Sadrian#define SYSCTL_SYSCFG_SRAM_CS_MODE_MASK 0x0000000c 227220297Sadrian#define SYSCTL_SYSCFG_SRAM_CS_MODE_SHIFT 2 228220297Sadrian#define SYSCTL_SYSCFG_SRAM_CS_MODE_SRAM 0 229220297Sadrian#define SYSCTL_SYSCFG_SRAM_CS_MODE_WDOG_RST 1 230220297Sadrian#define SYSCTL_SYSCFG_SRAM_CS_MODE_BT_COEX 2 231220297Sadrian#define SYSCTL_SYSCFG_SDRAM_CLK_DRV (1<<0) /* 8mA/12mA */ 232292699Sadrian#endif 233292699Sadrian#ifdef RT5350 234292699Sadrian#define SYSCTL1_SYSCFG_PULL_EN (1<<26) 235292699Sadrian#define SYSCTL1_SYSCFG_SDR_PAD_DRV_MASK 0x0700000 236292699Sadrian#define SYSCTL1_SYSCFG_SDR_PAD_DRV_SHIFT 20 237292699Sadrian#define SYSCTL1_SYSCFG_SDR_PAD_DRV_0 0 238292699Sadrian#define SYSCTL1_SYSCFG_SDR_PAD_DRV_1 1 239292699Sadrian#define SYSCTL1_SYSCFG_SDR_PAD_DRV_2 2 240292699Sadrian#endif 241220297Sadrian 242292699Sadrian#define SYSCTL_SYSCFG1 0x14 243292699Sadrian#define SYSCTL_SYSCFG1_USB0_HOST_MODE (1 << 10) 244292699Sadrian 245220297Sadrian#define SYSCTL_TESTSTAT 0x18 246220297Sadrian#define SYSCTL_TESTSTAT2 0x1C 247220297Sadrian 248220297Sadrian#define SYSCTL_CLKCFG0 0x2C 249220297Sadrian#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_MASK 0xc0000000 250220297Sadrian#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_SHIFT 30 251220297Sadrian#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_ZERO_DELAY 0 252220297Sadrian#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_1NS_DELAY 1 253220297Sadrian#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_2NS_DELAY 2 254220297Sadrian#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_3NS_DELAY 3 255220297Sadrian 256220297Sadrian#define SYSCTL_CLKCFG1 0x30 257292699Sadrian#if !defined(RT5350) 258220297Sadrian#define SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2 (1<<30) 259292699Sadrian#define SYSCTL_CLKCFG1_UPHY0_CLK_EN (1<<25) 260292699Sadrian#define SYSCTL_CLKCFG1_UPHY1_CLK_EN (1<<22) 261220297Sadrian#define SYSCTL_CLKCFG1_OTG_CLK_EN (1<<18) 262220297Sadrian#define SYSCTL_CLKCFG1_I2S_CLK_EN (1<<15) 263220297Sadrian#define SYSCTL_CLKCFG1_I2S_CLK_SEL_EXT (1<<14) 264220297Sadrian#define SYSCTL_CLKCFG1_I2S_CLK_DIV_MASK 0x00003f00 265220297Sadrian#define SYSCTL_CLKCFG1_I2S_CLK_DIV_SHIFT 8 266220297Sadrian#define SYSCTL_CLKCFG1_PCM_CLK_EN (1<<7) 267220297Sadrian#define SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT (1<<6) 268220297Sadrian#define SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK 0x0000003f 269220297Sadrian#define SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT 0 270292699Sadrian#endif 271292699Sadrian#ifdef RT5350 272292699Sadrian#define SYSCTL_CLKCFG1_SYSTICK_EN (1<<29) 273292699Sadrian#define SYSCTL_CLKCFG1_PDMA_CSR_CLK_GATE_BYP (1<<23) 274292699Sadrian#define SYSCTL_CLKCFG1_UPHY0_CLK_EN (1<<18) 275292699Sadrian#endif 276220297Sadrian 277220297Sadrian#define SYSCTL_RSTCTRL 0x34 278220297Sadrian#define SYSCTL_RSTCTRL_ETHSW (1<<23) 279292699Sadrian#if !defined(MT7620) && !defined(RT5350) 280220297Sadrian#define SYSCTL_RSTCTRL_OTG (1<<22) 281292699Sadrian#else 282292699Sadrian#define SYSCTL_RSTCTRL_UPHY0 (1<<25) 283292699Sadrian#define SYSCTL_RSTCTRL_UPHY1 (1<<22) 284292699Sadrian#endif 285220297Sadrian#define SYSCTL_RSTCTRL_FRENG (1<<21) 286220297Sadrian#define SYSCTL_RSTCTRL_WLAN (1<<20) 287220297Sadrian#define SYSCTL_RSTCTRL_UARTL (1<<19) 288220297Sadrian#define SYSCTL_RSTCTRL_SPI (1<<18) 289220297Sadrian#define SYSCTL_RSTCTRL_I2S (1<<17) 290220297Sadrian#define SYSCTL_RSTCTRL_I2C (1<<16) 291220297Sadrian#define SYSCTL_RSTCTRL_DMA (1<<14) 292220297Sadrian#define SYSCTL_RSTCTRL_PIO (1<<13) 293220297Sadrian#define SYSCTL_RSTCTRL_UART (1<<12) 294220297Sadrian#define SYSCTL_RSTCTRL_PCM (1<<11) 295220297Sadrian#define SYSCTL_RSTCTRL_MC (1<<10) 296220297Sadrian#define SYSCTL_RSTCTRL_INTC (1<<9) 297220297Sadrian#define SYSCTL_RSTCTRL_TIMER (1<<8) 298220297Sadrian#define SYSCTL_RSTCTRL_SYS (1<<0) 299220297Sadrian 300220297Sadrian#define SYSCTL_RSTSTAT 0x38 301220297Sadrian#define SYSCTL_RSTSTAT_SWCPURST (1<<3) 302220297Sadrian#define SYSCTL_RSTSTAT_SWSYSRST (1<<2) 303220297Sadrian#define SYSCTL_RSTSTAT_WDRST (1<<1) 304220297Sadrian 305220297Sadrian#define SYSCTL_GPIOMODE 0x60 306220297Sadrian#define SYSCTL_GPIOMODE_RGMII_GPIO_MODE (1<<9) 307220297Sadrian#define SYSCTL_GPIOMODE_SDRAM_GPIO_MODE (1<<8) 308220297Sadrian#define SYSCTL_GPIOMODE_MDIO_GPIO_MODE (1<<7) 309220297Sadrian#define SYSCTL_GPIOMODE_JTAG_GPIO_MODE (1<<6) 310220297Sadrian#define SYSCTL_GPIOMODE_UARTL_GPIO_MODE (1<<5) 311220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_UARTF (0<<2) 312220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_UARTF (1<<2) 313220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_I2S (2<<2) 314220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_I2S_UARTF (3<<2) 315220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_GPIO (4<<2) 316220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO_UARTF (5<<2) 317220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO_I2S (6<<2) 318220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO (7<<2) 319220297Sadrian#define SYSCTL_GPIOMODE_SPI_GPIO_MODE (1<<1) 320220297Sadrian#define SYSCTL_GPIOMODE_I2C_GPIO_MODE (1<<0) 321220297Sadrian 322220297Sadrian#define SYSCTL_MEMO0 0x68 323220297Sadrian#define SYSCTL_MEMO1 0x6C 324220297Sadrian 325292699Sadrian#define SYSCTL_PPLL_CFG1 0x9C 326292699Sadrian#define SYSCTL_PPLL_DRV 0xA0 327292699Sadrian 328220297Sadrian/* Timer */ 329220297Sadrian#define TIMER_TMRSTAT 0x00 330220297Sadrian#define TIMER_TMRSTAT_TMR1RST (1<<5) 331220297Sadrian#define TIMER_TMRSTAT_TMR0RST (1<<4) 332220297Sadrian#define TIMER_TMRSTAT_TMR1INT (1<<1) 333220297Sadrian#define TIMER_TMRSTAT_TMR0INT (1<<0) 334220297Sadrian#define TIMER_TMR0LOAD 0x10 335220297Sadrian#define TIMER_TMR0VAL 0x14 336220297Sadrian#define TIMER_TMR0CTL 0x18 337220297Sadrian#define TIMER_TMR1LOAD 0x20 338220297Sadrian#define TIMER_TMR1VAL 0x24 339220297Sadrian#define TIMER_TMR1CTL 0x28 340220297Sadrian 341220297Sadrian#define TIMER_TMRLOAD_TMR0LOAD_MASK 0xffff 342220297Sadrian 343220297Sadrian#define TIMER_TMRVAL_TMR0VAL_MASK 0xffff 344220297Sadrian 345220297Sadrian#define TIMER_TMRCTL_ENABLE (1<<7) 346220297Sadrian#define TIMER_TMRCTL_MODE_MASK 0x00000030 347220297Sadrian#define TIMER_TMRCTL_MODE_SHIFT 4 348220297Sadrian#define TIMER_TMRCTL_MODE_FREE 0 349220297Sadrian#define TIMER_TMRCTL_MODE_PERIODIC 1 350220297Sadrian#define TIMER_TMRCTL_MODE_TIMOUT 2 351220297Sadrian#define TIMER_TMRCTL_MODE_TIMOUT3 3 352220297Sadrian#define TIMER_TMRCTL_PRESCALE_MASK 0x0000000f 353220297Sadrian#define TIMER_TMRCTL_PRESCALE_SHIFT 0 354220297Sadrian#define TIMER_TMRCTL_PRESCALE_NONE 0 355220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_4 1 356220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_8 2 357220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_16 3 358220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_32 4 359220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_64 5 360220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_128 6 361220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_256 7 362220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_512 8 363220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_1K 9 364220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_2K 10 365220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_4K 11 366220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_8K 12 367220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_16K 13 368220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_32K 14 369220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_64K 15 370220297Sadrian 371220297Sadrian/* Interrupt Controller */ 372220297Sadrian#define IC_IRQ0STAT 0x00 373220297Sadrian#define IC_IRQ1STAT 0x04 374220297Sadrian#define IC_INTTYPE 0x20 375220297Sadrian#define IC_INTRAW 0x30 376220297Sadrian#define IC_INT_ENA 0x34 377220297Sadrian#define IC_INT_DIS 0x38 378220297Sadrian 379220297Sadrian#define IC_OTG 18 380220297Sadrian#define IC_ETHSW 17 381292699Sadrian#define IC_R2P 15 382292699Sadrian#define IC_SDHC 14 383220297Sadrian#define IC_UARTLITE 12 384292699Sadrian#define IC_SPI 11 385220297Sadrian#define IC_I2S 10 386220297Sadrian#define IC_PERFC 9 387220297Sadrian#define IC_NAND 8 388220297Sadrian#define IC_DMA 7 389220297Sadrian#define IC_PIO 6 390220297Sadrian#define IC_UART 5 391220297Sadrian#define IC_PCM 4 392220297Sadrian#define IC_ILL_ACCESS 3 393220297Sadrian#define IC_WDTIMER 2 394220297Sadrian#define IC_TIMER0 1 395220297Sadrian#define IC_SYSCTL 0 396220297Sadrian 397220297Sadrian#define IC_LINE_GLOBAL (1<<31) /* Only for DIS/ENA regs */ 398220297Sadrian#define IC_LINE_OTG (1<<18) 399220297Sadrian#define IC_LINE_ETHSW (1<<17) 400220297Sadrian#define IC_LINE_UARTLITE (1<<12) 401220297Sadrian#define IC_LINE_I2S (1<<10) 402220297Sadrian#define IC_LINE_PERFC (1<<9) 403220297Sadrian#define IC_LINE_NAND (1<<8) 404220297Sadrian#define IC_LINE_DMA (1<<7) 405220297Sadrian#define IC_LINE_PIO (1<<6) 406220297Sadrian#define IC_LINE_UART (1<<5) 407220297Sadrian#define IC_LINE_PCM (1<<4) 408220297Sadrian#define IC_LINE_ILL_ACCESS (1<<3) 409220297Sadrian#define IC_LINE_WDTIMER (1<<2) 410220297Sadrian#define IC_LINE_TIMER0 (1<<1) 411220297Sadrian#define IC_LINE_SYSCTL (1<<0) 412220297Sadrian 413220297Sadrian#define IC_INT_MASK 0x000617ff 414220297Sadrian 415220297Sadrian/* GPIO */ 416220297Sadrian 417220297Sadrian#define GPIO23_00_INT 0x00 /* Programmed I/O Int Status */ 418220297Sadrian#define GPIO23_00_EDGE 0x04 /* Programmed I/O Edge Status */ 419220297Sadrian#define GPIO23_00_RENA 0x08 /* Programmed I/O Int on Rising */ 420220297Sadrian#define GPIO23_00_FENA 0x0C /* Programmed I/O Int on Falling */ 421220297Sadrian#define GPIO23_00_DATA 0x20 /* Programmed I/O Data */ 422220297Sadrian#define GPIO23_00_DIR 0x24 /* Programmed I/O Direction */ 423220297Sadrian#define GPIO23_00_POL 0x28 /* Programmed I/O Pin Polarity */ 424220297Sadrian#define GPIO23_00_SET 0x2C /* Set PIO Data Bit */ 425220297Sadrian#define GPIO23_00_RESET 0x30 /* Clear PIO Data bit */ 426220297Sadrian#define GPIO23_00_TOG 0x34 /* Toggle PIO Data bit */ 427220297Sadrian 428220297Sadrian#define GPIO39_24_INT 0x38 429220297Sadrian#define GPIO39_24_EDGE 0x3c 430220297Sadrian#define GPIO39_24_RENA 0x40 431220297Sadrian#define GPIO39_24_FENA 0x44 432220297Sadrian#define GPIO39_24_DATA 0x48 433220297Sadrian#define GPIO39_24_DIR 0x4c 434220297Sadrian#define GPIO39_24_POL 0x50 435220297Sadrian#define GPIO39_24_SET 0x54 436220297Sadrian#define GPIO39_24_RESET 0x58 437220297Sadrian#define GPIO39_24_TOG 0x5c 438220297Sadrian 439220297Sadrian#define GPIO51_40_INT 0x60 440220297Sadrian#define GPIO51_40_EDGE 0x64 441220297Sadrian#define GPIO51_40_RENA 0x68 442220297Sadrian#define GPIO51_40_FENA 0x6C 443220297Sadrian#define GPIO51_40_DATA 0x70 444220297Sadrian#define GPIO51_40_DIR 0x74 445220297Sadrian#define GPIO51_40_POL 0x78 446220297Sadrian#define GPIO51_40_SET 0x7C 447220297Sadrian#define GPIO51_40_RESET 0x80 448220297Sadrian#define GPIO51_40_TOG 0x84 449220297Sadrian 450220297Sadrian 451220297Sadrian 452220297Sadrian 453220297Sadrian#define GDMA_CHANNEL_REQ0 0 454220297Sadrian#define GDMA_CHANNEL_REQ1 1 /* (NAND-flash) */ 455220297Sadrian#define GDMA_CHANNEL_REQ2 2 /* (I2S) */ 456220297Sadrian#define GDMA_CHANNEL_REQ3 3 /* (PCM0-RX) */ 457220297Sadrian#define GDMA_CHANNEL_REQ4 4 /* (PCM1-RX) */ 458220297Sadrian#define GDMA_CHANNEL_REQ5 5 /* (PCM0-TX) */ 459220297Sadrian#define GDMA_CHANNEL_REQ6 6 /* (PCM1-TX) */ 460220297Sadrian#define GDMA_CHANNEL_REQ7 7 461220297Sadrian#define GDMA_CHANNEL_MEM 8 462220297Sadrian 463220297Sadrian/* Generic DMA Controller */ 464220297Sadrian/* GDMA Channel n Source Address */ 465220297Sadrian#define GDMASA(n) (0x00 + 0x10*n) 466220297Sadrian /* GDMA Channel n Destination Address */ 467220297Sadrian#define GDMADA(n) (0x04 + 0x10*n) 468220297Sadrian /* GDMA Channel n Control Register 0 */ 469220297Sadrian#define GDMACT0(n) (0x08 + 0x10*n) 470220297Sadrian 471220297Sadrian#define GDMACT0_TR_COUNT_MASK 0x0fff0000 472220297Sadrian#define GDMACT0_TR_COUNT_SHIFT 16 473220297Sadrian#define GDMACT0_SRC_CHAN_SHIFT 12 474220297Sadrian#define GDMACT0_SRC_CHAN_MASK 0x0000f000 475220297Sadrian#define GDMACT0_DST_CHAN_SHIFT 8 476220297Sadrian#define GDMACT0_DST_CHAN_MASK 0x00000f00 477220297Sadrian#define GDMACT0_SRC_BURST_MODE (1<<7) 478220297Sadrian#define GDMACT0_DST_BURST_MODE (1<<6) 479220297Sadrian#define GDMACT0_BURST_SIZE_SHIFT 3 480220297Sadrian#define GDMACT0_BURST_SIZE_MASK 0x00000038 481220297Sadrian#define GDMACT0_BURST_SIZE_1 0 482220297Sadrian#define GDMACT0_BURST_SIZE_2 1 483220297Sadrian#define GDMACT0_BURST_SIZE_4 2 484220297Sadrian#define GDMACT0_BURST_SIZE_8 3 485220297Sadrian#define GDMACT0_BURST_SIZE_16 4 486220297Sadrian 487220297Sadrian#define GDMACT0_DONE_INT_EN (1<<2) 488220297Sadrian#define GDMACT0_CHAN_EN (1<<1) 489220297Sadrian/* 490220297Sadrian * In software mode, the data transfer will start when the Channel Enable bit 491220297Sadrian * is set. 492220297Sadrian * In hardware mode, the data transfer will start when the DMA Request is 493220297Sadrian * asserted. 494220297Sadrian*/ 495220297Sadrian#define GDMACT0_SWMODE (1<<0) 496220297Sadrian 497292699Sadrian/* SPI controller interface */ 498292699Sadrian 499292699Sadrian#define RT305X_SPISTAT 0x00 500292699Sadrian/* SPIBUSY is alias for SPIBUSY, because SPISTAT have only BUSY bit*/ 501292699Sadrian#define RT305X_SPIBUSY RT305X_SPISTAT 502292699Sadrian 503292699Sadrian#define RT305X_SPICFG 0x10 504292699Sadrian#define MSBFIRST (1<<8) 505292699Sadrian#define SPICLKPOL (1<<6) 506292699Sadrian#define CAPT_ON_CLK_FALL (1<<5) 507292699Sadrian#define TX_ON_CLK_FALL (1<<4) 508292699Sadrian#define HIZSPI (1<<3) /* Set SPI pins to Tri-state */ 509292699Sadrian#define SPI_CLK_SHIFT 0 /* SPI clock divide control */ 510292699Sadrian#define SPI_CLK_MASK 0x00000007 511292699Sadrian#define SPI_CLK_DIV2 0 512292699Sadrian#define SPI_CLK_DIV4 1 513292699Sadrian#define SPI_CLK_DIV8 2 514292699Sadrian#define SPI_CLK_DIV16 3 515292699Sadrian#define SPI_CLK_DIV32 4 516292699Sadrian#define SPI_CLK_DIV64 5 517292699Sadrian#define SPI_CLK_DIV128 6 518292699Sadrian#define SPI_CLK_DISABLED 7 519292699Sadrian 520292699Sadrian#define RT305X_SPICTL 0x14 521292699Sadrian#define HIZSMOSI (1<<3) 522292699Sadrian#define START_WRITE (1<<2) 523292699Sadrian#define START_READ (1<<1) 524292699Sadrian#define CS_HIGH (1<<0) 525220297Sadrian 526292699Sadrian#define RT305X_SPIDATA 0x20 527292699Sadrian#define SPIDATA_MASK 0x000000ff 528220297Sadrian 529292699Sadrian#define RT305X_SPI_WRITE 1 530292699Sadrian#define RT305X_SPI_READ 0 531220297Sadrian 532220297Sadrian#endif /* _RT305XREG_H_ */ 533