1/*- 2 * Copyright (c) 2015 Stanislav Galabov. 3 * Copyright (c) 2010 Aleksandr Rybalko. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: releng/11.0/sys/mips/rt305x/rt305xreg.h 292699 2015-12-24 18:31:55Z adrian $ 28 */ 29 30#ifndef _RT305XREG_H_ 31#define _RT305XREG_H_ 32 33#include "opt_rt305x.h" 34 35#ifdef RT3052F 36#define PLATFORM_COUNTER_FREQ (384 * 1000 * 1000) 37#endif 38#ifdef RT3050F 39#define PLATFORM_COUNTER_FREQ (320 * 1000 * 1000) 40#endif 41#ifdef MT7620 42#define PLATFORM_COUNTER_FREQ (580 * 1000 * 1000) 43#endif 44#ifdef RT5350 45#define PLATFORM_COUNTER_FREQ (360 * 1000 * 1000) 46#endif 47#ifndef PLATFORM_COUNTER_FREQ 48#error "No platform selected" 49#endif 50 51#ifndef MT7620 52 53#define SYSTEM_CLOCK (PLATFORM_COUNTER_FREQ/3) 54 55#define SDRAM_BASE 0x00000000 56#define SDRAM_END 0x03FFFFFF 57 58#define SYSCTL_BASE 0x10000000 59#define SYSCTL_END 0x100000FF 60#define TIMER_BASE 0x10000100 61#define TIMER_END 0x100001FF 62#define INTCTL_BASE 0x10000200 63#define INTCTL_END 0x100002FF 64#define MEMCTRL_BASE 0x10000300 65#define MEMCTRL_END 0x100003FF /* SDRAM & Flash/SRAM */ 66#ifndef RT5350 67#define PCM_BASE 0x10000400 68#define PCM_END 0x100004FF 69#else 70#define PCM_BASE 0x10002000 71#define PCM_END 0x100027FF 72#endif 73#define UART_BASE 0x10000500 74#define UART_END 0x100005FF 75#define PIO_BASE 0x10000600 76#define PIO_END 0x100006FF 77#ifndef RT5350 78#define GDMA_BASE 0x10000700 79#define GDMA_END 0x100007FF /* Generic DMA */ 80#define NANDFC_BASE 0x10000800 81#define NANDFC_END 0x100008FF /* NAND Flash Controller */ 82#else 83#define GDMA_BASE 0x10002800 84#define GDMA_END 0x10002FFF 85#endif 86#define I2C_BASE 0x10000900 87#define I2C_END 0x100009FF 88#define I2S_BASE 0x10000A00 89#define I2S_END 0x10000AFF 90#define SPI_BASE 0x10000B00 91#define SPI_END 0x10000BFF 92#define UARTLITE_BASE 0x10000C00 93#define UARTLITE_END 0x10000CFF 94 95#define FRENG_BASE 0x10100000 96#define FRENG_END 0x1010FFFF /* Frame Engine */ 97#define ETHSW_BASE 0x10110000 98#define ETHSW_END 0x10117FFF /* Ethernet Switch */ 99#define ROM_BASE 0x10118000 100#define ROM_END 0x10119FFF 101#define WLAN_BASE 0x10180000 102#define WLAN_END 0x101BFFFF /* 802.11n MAC/BBP */ 103#ifndef RT5350 104#define USB_OTG_BASE 0x101C0000 105#define USB_OTG_END 0x101FFFFF 106#else 107#define USB_OTG_BASE 0x101C0000 108#define USB_OTG_END 0x101C0FFF 109#define USB_OHCI_BASE 0x101C1000 110#define USB_OHCI_END 0x101C1FFF 111#endif 112#define EMEM_BASE 0x1B000000 113#define EMEM_END 0x1BFFFFFF /* External SRAM/Flash */ 114#ifdef RT5350 115#define BOOT_ROM_BASE 0x1C000000 116#define BOOT_ROM_END 0x1C003FFF 117#endif 118#ifndef RT5350 119#define FLASH_BASE 0x1F000000 120#define FLASH_END 0x1FFFFFFF /* Flash window */ 121#endif 122 123#define OBIO_MEM_BASE SYSCTL_BASE 124#define OBIO_MEM_START OBIO_MEM_BASE 125#ifndef RT5350 126#define OBIO_MEM_END FLASH_END 127#else 128#define OBIO_MEM_END BOOT_ROM_END 129#endif 130 131#else /* MT7620 */ 132 133#define SYSTEM_CLOCK (40 * 1000 * 1000) 134 135#define SDRAM_BASE 0x00000000 136#define SDRAM_END 0x0FFFFFFF 137 138#define SYSCTL_BASE 0x10000000 139#define SYSCTL_END 0x100000FF 140#define TIMER_BASE 0x10000100 141#define TIMER_END 0x100001FF 142#define INTCTL_BASE 0x10000200 143#define INTCTL_END 0x100002FF 144#define MEMCTRL_BASE 0x10000300 145#define MEMCTRL_END 0x100003FF /* SDRAM & Flash/SRAM */ 146#define PCM_BASE 0x10002000 147#define PCM_END 0x100027FF 148#define UART_BASE 0x10000500 149#define UART_END 0x100005FF 150#define PIO_BASE 0x10000600 151#define PIO_END 0x100006FF 152#define GDMA_BASE 0x10002800 153#define GDMA_END 0x10002FFF /* Generic DMA */ 154#define NANDFC_BASE 0x10000800 155#define NANDFC_END 0x100008FF /* NAND Flash Controller */ 156#define I2C_BASE 0x10000900 157#define I2C_END 0x100009FF 158#define I2S_BASE 0x10000A00 159#define I2S_END 0x10000AFF 160#define SPI_BASE 0x10000B00 161#define SPI_END 0x10000BFF 162#define UARTLITE_BASE 0x10000C00 163#define UARTLITE_END 0x10000CFF 164 165#define FRENG_BASE 0x10100000 166#define FRENG_END 0x1010FFFF /* Frame Engine */ 167#define ETHSW_BASE 0x10110000 168#define ETHSW_END 0x10117FFF /* Ethernet Switch */ 169#define ROM_BASE 0x10118000 170#define ROM_END 0x1011FFFF 171#define WLAN_BASE 0x10180000 172#define WLAN_END 0x101BFFFF /* 802.11n MAC/BBP */ 173#define USB_OTG_BASE 0x101C0000 174#define USB_OTG_END 0x101C0FFF 175#define USB_OHCI_BASE 0x101C1000 176#define USB_OHCI_END 0x101C1FFF 177#define PCIE_BASE 0x10140000 178#define PCIE_END 0x1017FFFF 179#define SDHC_BASE 0x10130000 180#define SDHC_END 0x10133FFF 181 182#define PCIE_IO_BASE 0x10160000 183#define PCIE_IO_END 0x1016FFFF 184#define PCIE_MEM_BASE 0x20000000 185#define PCIE_MEM_END 0x2FFFFFFF 186 187// TODO: fix below mappings? 188#define EMEM_BASE 0x1B000000 189#define EMEM_END 0x1BFFFFFF /* External SRAM/Flash */ 190#define FLASH_BASE 0x1F000000 191#define FLASH_END 0x1FFFFFFF /* Flash window */ 192 193#define OBIO_MEM_BASE SYSCTL_BASE 194#define OBIO_MEM_START OBIO_MEM_BASE 195#define OBIO_MEM_END FLASH_END 196#endif 197 198/* System Control */ 199#define SYSCTL_CHIPID0_3 0x00 200#define SYSCTL_CHIPID4_7 0x04 201#ifdef RT5350 202#define SYSCTL_REVID 0x0C 203#endif 204 205#define SYSCTL_SYSCFG 0x10 206#if !defined(RT5350) && !defined(MT7620) 207#define SYSCTL_SYSCFG_INIC_EE_SDRAM (1<<29) 208#define SYSCTL_SYSCFG_INIC_8MB_SDRAM (1<<28) 209#define SYSCTL_SYSCFG_GE0_MODE_MASK 0x03000000 210#define SYSCTL_SYSCFG_GE0_MODE_SHIFT 24 211#define SYSCTL_SYSCFG_GE0_MODE_RGMII 0 /* RGMII Mode */ 212#define SYSCTL_SYSCFG_GE0_MODE_MII 1 /* MII Mode */ 213#define SYSCTL_SYSCFG_GE0_MODE_REV_MII 2 /*Reversed MII Mode*/ 214#define SYSCTL_SYSCFG_BOOT_ADDR_1F00 (1<<22) 215#define SYSCTL_SYSCFG_BYPASS_PLL (1<<21) 216#define SYSCTL_SYSCFG_BIG_ENDIAN (1<<20) 217#define SYSCTL_SYSCFG_CPU_CLK_SEL_384MHZ (1<<18) 218#define SYSCTL_SYSCFG_BOOT_FROM_MASK 0x00030000 219#define SYSCTL_SYSCFG_BOOT_FROM_SHIFT 16 220#define SYSCTL_SYSCFG_BOOT_FROM_FLASH16 0 221#define SYSCTL_SYSCFG_BOOT_FROM_FLASH8 1 222#define SYSCTL_SYSCFG_BOOT_FROM_NANDFLASH 2 223#define SYSCTL_SYSCFG_BOOT_FROM_ROM 3 224#define SYSCTL_SYSCFG_TEST_CODE_MASK 0x0000ff00 225#define SYSCTL_SYSCFG_TEST_CODE_SHIFT 8 226#define SYSCTL_SYSCFG_SRAM_CS_MODE_MASK 0x0000000c 227#define SYSCTL_SYSCFG_SRAM_CS_MODE_SHIFT 2 228#define SYSCTL_SYSCFG_SRAM_CS_MODE_SRAM 0 229#define SYSCTL_SYSCFG_SRAM_CS_MODE_WDOG_RST 1 230#define SYSCTL_SYSCFG_SRAM_CS_MODE_BT_COEX 2 231#define SYSCTL_SYSCFG_SDRAM_CLK_DRV (1<<0) /* 8mA/12mA */ 232#endif 233#ifdef RT5350 234#define SYSCTL1_SYSCFG_PULL_EN (1<<26) 235#define SYSCTL1_SYSCFG_SDR_PAD_DRV_MASK 0x0700000 236#define SYSCTL1_SYSCFG_SDR_PAD_DRV_SHIFT 20 237#define SYSCTL1_SYSCFG_SDR_PAD_DRV_0 0 238#define SYSCTL1_SYSCFG_SDR_PAD_DRV_1 1 239#define SYSCTL1_SYSCFG_SDR_PAD_DRV_2 2 240#endif 241 242#define SYSCTL_SYSCFG1 0x14 243#define SYSCTL_SYSCFG1_USB0_HOST_MODE (1 << 10) 244 245#define SYSCTL_TESTSTAT 0x18 246#define SYSCTL_TESTSTAT2 0x1C 247 248#define SYSCTL_CLKCFG0 0x2C 249#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_MASK 0xc0000000 250#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_SHIFT 30 251#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_ZERO_DELAY 0 252#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_1NS_DELAY 1 253#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_2NS_DELAY 2 254#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_3NS_DELAY 3 255 256#define SYSCTL_CLKCFG1 0x30 257#if !defined(RT5350) 258#define SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2 (1<<30) 259#define SYSCTL_CLKCFG1_UPHY0_CLK_EN (1<<25) 260#define SYSCTL_CLKCFG1_UPHY1_CLK_EN (1<<22) 261#define SYSCTL_CLKCFG1_OTG_CLK_EN (1<<18) 262#define SYSCTL_CLKCFG1_I2S_CLK_EN (1<<15) 263#define SYSCTL_CLKCFG1_I2S_CLK_SEL_EXT (1<<14) 264#define SYSCTL_CLKCFG1_I2S_CLK_DIV_MASK 0x00003f00 265#define SYSCTL_CLKCFG1_I2S_CLK_DIV_SHIFT 8 266#define SYSCTL_CLKCFG1_PCM_CLK_EN (1<<7) 267#define SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT (1<<6) 268#define SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK 0x0000003f 269#define SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT 0 270#endif 271#ifdef RT5350 272#define SYSCTL_CLKCFG1_SYSTICK_EN (1<<29) 273#define SYSCTL_CLKCFG1_PDMA_CSR_CLK_GATE_BYP (1<<23) 274#define SYSCTL_CLKCFG1_UPHY0_CLK_EN (1<<18) 275#endif 276 277#define SYSCTL_RSTCTRL 0x34 278#define SYSCTL_RSTCTRL_ETHSW (1<<23) 279#if !defined(MT7620) && !defined(RT5350) 280#define SYSCTL_RSTCTRL_OTG (1<<22) 281#else 282#define SYSCTL_RSTCTRL_UPHY0 (1<<25) 283#define SYSCTL_RSTCTRL_UPHY1 (1<<22) 284#endif 285#define SYSCTL_RSTCTRL_FRENG (1<<21) 286#define SYSCTL_RSTCTRL_WLAN (1<<20) 287#define SYSCTL_RSTCTRL_UARTL (1<<19) 288#define SYSCTL_RSTCTRL_SPI (1<<18) 289#define SYSCTL_RSTCTRL_I2S (1<<17) 290#define SYSCTL_RSTCTRL_I2C (1<<16) 291#define SYSCTL_RSTCTRL_DMA (1<<14) 292#define SYSCTL_RSTCTRL_PIO (1<<13) 293#define SYSCTL_RSTCTRL_UART (1<<12) 294#define SYSCTL_RSTCTRL_PCM (1<<11) 295#define SYSCTL_RSTCTRL_MC (1<<10) 296#define SYSCTL_RSTCTRL_INTC (1<<9) 297#define SYSCTL_RSTCTRL_TIMER (1<<8) 298#define SYSCTL_RSTCTRL_SYS (1<<0) 299 300#define SYSCTL_RSTSTAT 0x38 301#define SYSCTL_RSTSTAT_SWCPURST (1<<3) 302#define SYSCTL_RSTSTAT_SWSYSRST (1<<2) 303#define SYSCTL_RSTSTAT_WDRST (1<<1) 304 305#define SYSCTL_GPIOMODE 0x60 306#define SYSCTL_GPIOMODE_RGMII_GPIO_MODE (1<<9) 307#define SYSCTL_GPIOMODE_SDRAM_GPIO_MODE (1<<8) 308#define SYSCTL_GPIOMODE_MDIO_GPIO_MODE (1<<7) 309#define SYSCTL_GPIOMODE_JTAG_GPIO_MODE (1<<6) 310#define SYSCTL_GPIOMODE_UARTL_GPIO_MODE (1<<5) 311#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_UARTF (0<<2) 312#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_UARTF (1<<2) 313#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_I2S (2<<2) 314#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_I2S_UARTF (3<<2) 315#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_GPIO (4<<2) 316#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO_UARTF (5<<2) 317#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO_I2S (6<<2) 318#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO (7<<2) 319#define SYSCTL_GPIOMODE_SPI_GPIO_MODE (1<<1) 320#define SYSCTL_GPIOMODE_I2C_GPIO_MODE (1<<0) 321 322#define SYSCTL_MEMO0 0x68 323#define SYSCTL_MEMO1 0x6C 324 325#define SYSCTL_PPLL_CFG1 0x9C 326#define SYSCTL_PPLL_DRV 0xA0 327 328/* Timer */ 329#define TIMER_TMRSTAT 0x00 330#define TIMER_TMRSTAT_TMR1RST (1<<5) 331#define TIMER_TMRSTAT_TMR0RST (1<<4) 332#define TIMER_TMRSTAT_TMR1INT (1<<1) 333#define TIMER_TMRSTAT_TMR0INT (1<<0) 334#define TIMER_TMR0LOAD 0x10 335#define TIMER_TMR0VAL 0x14 336#define TIMER_TMR0CTL 0x18 337#define TIMER_TMR1LOAD 0x20 338#define TIMER_TMR1VAL 0x24 339#define TIMER_TMR1CTL 0x28 340 341#define TIMER_TMRLOAD_TMR0LOAD_MASK 0xffff 342 343#define TIMER_TMRVAL_TMR0VAL_MASK 0xffff 344 345#define TIMER_TMRCTL_ENABLE (1<<7) 346#define TIMER_TMRCTL_MODE_MASK 0x00000030 347#define TIMER_TMRCTL_MODE_SHIFT 4 348#define TIMER_TMRCTL_MODE_FREE 0 349#define TIMER_TMRCTL_MODE_PERIODIC 1 350#define TIMER_TMRCTL_MODE_TIMOUT 2 351#define TIMER_TMRCTL_MODE_TIMOUT3 3 352#define TIMER_TMRCTL_PRESCALE_MASK 0x0000000f 353#define TIMER_TMRCTL_PRESCALE_SHIFT 0 354#define TIMER_TMRCTL_PRESCALE_NONE 0 355#define TIMER_TMRCTL_PRESCALE_BY_4 1 356#define TIMER_TMRCTL_PRESCALE_BY_8 2 357#define TIMER_TMRCTL_PRESCALE_BY_16 3 358#define TIMER_TMRCTL_PRESCALE_BY_32 4 359#define TIMER_TMRCTL_PRESCALE_BY_64 5 360#define TIMER_TMRCTL_PRESCALE_BY_128 6 361#define TIMER_TMRCTL_PRESCALE_BY_256 7 362#define TIMER_TMRCTL_PRESCALE_BY_512 8 363#define TIMER_TMRCTL_PRESCALE_BY_1K 9 364#define TIMER_TMRCTL_PRESCALE_BY_2K 10 365#define TIMER_TMRCTL_PRESCALE_BY_4K 11 366#define TIMER_TMRCTL_PRESCALE_BY_8K 12 367#define TIMER_TMRCTL_PRESCALE_BY_16K 13 368#define TIMER_TMRCTL_PRESCALE_BY_32K 14 369#define TIMER_TMRCTL_PRESCALE_BY_64K 15 370 371/* Interrupt Controller */ 372#define IC_IRQ0STAT 0x00 373#define IC_IRQ1STAT 0x04 374#define IC_INTTYPE 0x20 375#define IC_INTRAW 0x30 376#define IC_INT_ENA 0x34 377#define IC_INT_DIS 0x38 378 379#define IC_OTG 18 380#define IC_ETHSW 17 381#define IC_R2P 15 382#define IC_SDHC 14 383#define IC_UARTLITE 12 384#define IC_SPI 11 385#define IC_I2S 10 386#define IC_PERFC 9 387#define IC_NAND 8 388#define IC_DMA 7 389#define IC_PIO 6 390#define IC_UART 5 391#define IC_PCM 4 392#define IC_ILL_ACCESS 3 393#define IC_WDTIMER 2 394#define IC_TIMER0 1 395#define IC_SYSCTL 0 396 397#define IC_LINE_GLOBAL (1<<31) /* Only for DIS/ENA regs */ 398#define IC_LINE_OTG (1<<18) 399#define IC_LINE_ETHSW (1<<17) 400#define IC_LINE_UARTLITE (1<<12) 401#define IC_LINE_I2S (1<<10) 402#define IC_LINE_PERFC (1<<9) 403#define IC_LINE_NAND (1<<8) 404#define IC_LINE_DMA (1<<7) 405#define IC_LINE_PIO (1<<6) 406#define IC_LINE_UART (1<<5) 407#define IC_LINE_PCM (1<<4) 408#define IC_LINE_ILL_ACCESS (1<<3) 409#define IC_LINE_WDTIMER (1<<2) 410#define IC_LINE_TIMER0 (1<<1) 411#define IC_LINE_SYSCTL (1<<0) 412 413#define IC_INT_MASK 0x000617ff 414 415/* GPIO */ 416 417#define GPIO23_00_INT 0x00 /* Programmed I/O Int Status */ 418#define GPIO23_00_EDGE 0x04 /* Programmed I/O Edge Status */ 419#define GPIO23_00_RENA 0x08 /* Programmed I/O Int on Rising */ 420#define GPIO23_00_FENA 0x0C /* Programmed I/O Int on Falling */ 421#define GPIO23_00_DATA 0x20 /* Programmed I/O Data */ 422#define GPIO23_00_DIR 0x24 /* Programmed I/O Direction */ 423#define GPIO23_00_POL 0x28 /* Programmed I/O Pin Polarity */ 424#define GPIO23_00_SET 0x2C /* Set PIO Data Bit */ 425#define GPIO23_00_RESET 0x30 /* Clear PIO Data bit */ 426#define GPIO23_00_TOG 0x34 /* Toggle PIO Data bit */ 427 428#define GPIO39_24_INT 0x38 429#define GPIO39_24_EDGE 0x3c 430#define GPIO39_24_RENA 0x40 431#define GPIO39_24_FENA 0x44 432#define GPIO39_24_DATA 0x48 433#define GPIO39_24_DIR 0x4c 434#define GPIO39_24_POL 0x50 435#define GPIO39_24_SET 0x54 436#define GPIO39_24_RESET 0x58 437#define GPIO39_24_TOG 0x5c 438 439#define GPIO51_40_INT 0x60 440#define GPIO51_40_EDGE 0x64 441#define GPIO51_40_RENA 0x68 442#define GPIO51_40_FENA 0x6C 443#define GPIO51_40_DATA 0x70 444#define GPIO51_40_DIR 0x74 445#define GPIO51_40_POL 0x78 446#define GPIO51_40_SET 0x7C 447#define GPIO51_40_RESET 0x80 448#define GPIO51_40_TOG 0x84 449 450 451 452 453#define GDMA_CHANNEL_REQ0 0 454#define GDMA_CHANNEL_REQ1 1 /* (NAND-flash) */ 455#define GDMA_CHANNEL_REQ2 2 /* (I2S) */ 456#define GDMA_CHANNEL_REQ3 3 /* (PCM0-RX) */ 457#define GDMA_CHANNEL_REQ4 4 /* (PCM1-RX) */ 458#define GDMA_CHANNEL_REQ5 5 /* (PCM0-TX) */ 459#define GDMA_CHANNEL_REQ6 6 /* (PCM1-TX) */ 460#define GDMA_CHANNEL_REQ7 7 461#define GDMA_CHANNEL_MEM 8 462 463/* Generic DMA Controller */ 464/* GDMA Channel n Source Address */ 465#define GDMASA(n) (0x00 + 0x10*n) 466 /* GDMA Channel n Destination Address */ 467#define GDMADA(n) (0x04 + 0x10*n) 468 /* GDMA Channel n Control Register 0 */ 469#define GDMACT0(n) (0x08 + 0x10*n) 470 471#define GDMACT0_TR_COUNT_MASK 0x0fff0000 472#define GDMACT0_TR_COUNT_SHIFT 16 473#define GDMACT0_SRC_CHAN_SHIFT 12 474#define GDMACT0_SRC_CHAN_MASK 0x0000f000 475#define GDMACT0_DST_CHAN_SHIFT 8 476#define GDMACT0_DST_CHAN_MASK 0x00000f00 477#define GDMACT0_SRC_BURST_MODE (1<<7) 478#define GDMACT0_DST_BURST_MODE (1<<6) 479#define GDMACT0_BURST_SIZE_SHIFT 3 480#define GDMACT0_BURST_SIZE_MASK 0x00000038 481#define GDMACT0_BURST_SIZE_1 0 482#define GDMACT0_BURST_SIZE_2 1 483#define GDMACT0_BURST_SIZE_4 2 484#define GDMACT0_BURST_SIZE_8 3 485#define GDMACT0_BURST_SIZE_16 4 486 487#define GDMACT0_DONE_INT_EN (1<<2) 488#define GDMACT0_CHAN_EN (1<<1) 489/* 490 * In software mode, the data transfer will start when the Channel Enable bit 491 * is set. 492 * In hardware mode, the data transfer will start when the DMA Request is 493 * asserted. 494*/ 495#define GDMACT0_SWMODE (1<<0) 496 497/* SPI controller interface */ 498 499#define RT305X_SPISTAT 0x00 500/* SPIBUSY is alias for SPIBUSY, because SPISTAT have only BUSY bit*/ 501#define RT305X_SPIBUSY RT305X_SPISTAT 502 503#define RT305X_SPICFG 0x10 504#define MSBFIRST (1<<8) 505#define SPICLKPOL (1<<6) 506#define CAPT_ON_CLK_FALL (1<<5) 507#define TX_ON_CLK_FALL (1<<4) 508#define HIZSPI (1<<3) /* Set SPI pins to Tri-state */ 509#define SPI_CLK_SHIFT 0 /* SPI clock divide control */ 510#define SPI_CLK_MASK 0x00000007 511#define SPI_CLK_DIV2 0 512#define SPI_CLK_DIV4 1 513#define SPI_CLK_DIV8 2 514#define SPI_CLK_DIV16 3 515#define SPI_CLK_DIV32 4 516#define SPI_CLK_DIV64 5 517#define SPI_CLK_DIV128 6 518#define SPI_CLK_DISABLED 7 519 520#define RT305X_SPICTL 0x14 521#define HIZSMOSI (1<<3) 522#define START_WRITE (1<<2) 523#define START_READ (1<<1) 524#define CS_HIGH (1<<0) 525 526#define RT305X_SPIDATA 0x20 527#define SPIDATA_MASK 0x000000ff 528 529#define RT305X_SPI_WRITE 1 530#define RT305X_SPI_READ 0 531 532#endif /* _RT305XREG_H_ */ 533