cpufunc.h revision 216947
1234353Sdim/* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */ 2193323Sed 3193323Sed/*- 4193323Sed * Copyright (c) 2002-2004 Juli Mallett. All rights reserved. 5193323Sed * 6193323Sed * Redistribution and use in source and binary forms, with or without 7193323Sed * modification, are permitted provided that the following conditions 8193323Sed * are met: 9193323Sed * 1. Redistributions of source code must retain the above copyright 10193323Sed * notice, this list of conditions and the following disclaimer. 11193323Sed * 2. Redistributions in binary form must reproduce the above copyright 12193323Sed * notice, this list of conditions and the following disclaimer in the 13193323Sed * documentation and/or other materials provided with the distribution. 14249423Sdim * 15249423Sdim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16239462Sdim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17249423Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18193323Sed * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19249423Sdim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20193323Sed * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21193399Sed * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22198090Srdivacky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23226633Sdim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24224145Sdim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25224145Sdim * SUCH DAMAGE. 26193323Sed */ 27193323Sed/* 28193323Sed * Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved. 29193323Sed * 30239462Sdim * Redistribution and use in source and binary forms, with or without 31224145Sdim * modification, are permitted provided that the following conditions 32239462Sdim * are met: 33193323Sed * 1. Redistributions of source code must retain the above copyright 34239462Sdim * notice, this list of conditions and the following disclaimer. 35239462Sdim * 2. Redistributions in binary form must reproduce the above copyright 36239462Sdim * notice, this list of conditions and the following disclaimer in the 37239462Sdim * documentation and/or other materials provided with the distribution. 38239462Sdim * 3. All advertising materials mentioning features or use of this software 39224145Sdim * must display the following acknowledgement: 40224145Sdim * This product includes software developed by Per Fogelstrom. 41239462Sdim * 4. The name of the author may not be used to endorse or promote products 42193323Sed * derived from this software without specific prior written permission 43193323Sed * 44193323Sed * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45193323Sed * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46193323Sed * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47193323Sed * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48221345Sdim * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49193323Sed * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50206124Srdivacky * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51193323Sed * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52193323Sed * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53193323Sed * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54239462Sdim * 55239462Sdim * JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta 56234353Sdim * $FreeBSD: head/sys/mips/include/cpufunc.h 216947 2011-01-04 02:33:48Z jmallett $ 57234353Sdim */ 58234353Sdim 59234353Sdim#ifndef _MACHINE_CPUFUNC_H_ 60234353Sdim#define _MACHINE_CPUFUNC_H_ 61234353Sdim 62234353Sdim#include <sys/types.h> 63234353Sdim#include <machine/cpuregs.h> 64224145Sdim 65224145Sdim/* 66224145Sdim * These functions are required by user-land atomi ops 67224145Sdim */ 68224145Sdim 69224145Sdimstatic __inline void 70224145Sdimmips_barrier(void) 71224145Sdim{ 72224145Sdim __asm __volatile (".set noreorder\n\t" 73193323Sed "nop\n\t" 74193323Sed "nop\n\t" 75193323Sed "nop\n\t" 76193323Sed "nop\n\t" 77239462Sdim "nop\n\t" 78239462Sdim "nop\n\t" 79239462Sdim "nop\n\t" 80221345Sdim "nop\n\t" 81221345Sdim ".set reorder\n\t" 82234353Sdim : : : "memory"); 83221345Sdim} 84221345Sdim 85221345Sdimstatic __inline void 86221345Sdimmips_cp0_sync(void) 87221345Sdim{ 88221345Sdim __asm __volatile (__XSTRING(COP0_SYNC)); 89221345Sdim} 90193323Sed 91193323Sedstatic __inline void 92221345Sdimmips_wbflush(void) 93193323Sed{ 94193323Sed __asm __volatile ("sync" : : : "memory"); 95193323Sed mips_barrier(); 96249423Sdim} 97249423Sdim 98249423Sdimstatic __inline void 99243830Sdimmips_read_membar(void) 100249423Sdim{ 101234353Sdim /* Nil */ 102234353Sdim} 103221345Sdim 104221345Sdimstatic __inline void 105221345Sdimmips_write_membar(void) 106221345Sdim{ 107221345Sdim mips_wbflush(); 108224145Sdim} 109224145Sdim 110193323Sed#ifdef _KERNEL 111243830Sdim/* 112243830Sdim * XXX 113243830Sdim * It would be nice to add variants that read/write register_t, to avoid some 114243830Sdim * ABI checks. 115243830Sdim */ 116243830Sdim#if defined(__mips_n32) || defined(__mips_n64) 117243830Sdim#define MIPS_RDRW64_COP0(n,r) \ 118243830Sdimstatic __inline uint64_t \ 119221345Sdimmips_rd_ ## n (void) \ 120193323Sed{ \ 121193323Sed int v0; \ 122193323Sed __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \ 123221345Sdim : [v0] "=&r"(v0)); \ 124193323Sed mips_barrier(); \ 125210299Sed return (v0); \ 126210299Sed} \ 127193323Sedstatic __inline void \ 128193323Sedmips_wr_ ## n (uint64_t a0) \ 129193323Sed{ \ 130221345Sdim __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \ 131221345Sdim __XSTRING(COP0_SYNC)";" \ 132221345Sdim "nop;" \ 133221345Sdim "nop;" \ 134221345Sdim : \ 135221345Sdim : [a0] "r"(a0)); \ 136221345Sdim mips_barrier(); \ 137193323Sed} struct __hack 138221345Sdim 139221345Sdim#if defined(__mips_n64) 140221345SdimMIPS_RDRW64_COP0(excpc, MIPS_COP_0_EXC_PC); 141234353SdimMIPS_RDRW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0); 142221345SdimMIPS_RDRW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1); 143193323SedMIPS_RDRW64_COP0(entryhi, MIPS_COP_0_TLB_HI); 144193323SedMIPS_RDRW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); 145221345Sdim#endif 146221345SdimMIPS_RDRW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT); 147221345Sdim 148234353Sdim#undef MIPS_RDRW64_COP0 149221345Sdim#endif 150221345Sdim 151221345Sdim#define MIPS_RDRW32_COP0(n,r) \ 152193323Sedstatic __inline uint32_t \ 153193323Sedmips_rd_ ## n (void) \ 154193323Sed{ \ 155221345Sdim int v0; \ 156193323Sed __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \ 157221345Sdim : [v0] "=&r"(v0)); \ 158221345Sdim mips_barrier(); \ 159221345Sdim return (v0); \ 160221345Sdim} \ 161221345Sdimstatic __inline void \ 162221345Sdimmips_wr_ ## n (uint32_t a0) \ 163221345Sdim{ \ 164221345Sdim __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \ 165221345Sdim __XSTRING(COP0_SYNC)";" \ 166221345Sdim "nop;" \ 167221345Sdim "nop;" \ 168221345Sdim : \ 169221345Sdim : [a0] "r"(a0)); \ 170221345Sdim mips_barrier(); \ 171221345Sdim} struct __hack 172221345Sdim 173221345Sdim#define MIPS_RDRW32_COP0_SEL(n,r,s) \ 174221345Sdimstatic __inline uint32_t \ 175221345Sdimmips_rd_ ## n(void) \ 176193323Sed{ \ 177193323Sed int v0; \ 178221345Sdim __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \ 179193323Sed : [v0] "=&r"(v0)); \ 180193323Sed mips_barrier(); \ 181221345Sdim return (v0); \ 182193323Sed} \ 183221345Sdimstatic __inline void \ 184193323Sedmips_wr_ ## n(uint32_t a0) \ 185239462Sdim{ \ 186193323Sed __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \ 187193323Sed __XSTRING(COP0_SYNC)";" \ 188193399Sed "nop;" \ 189249423Sdim "nop;" \ 190249423Sdim : \ 191249423Sdim : [a0] "r"(a0)); \ 192249423Sdim mips_barrier(); \ 193249423Sdim} struct __hack 194249423Sdim 195249423Sdim#ifdef CPU_CNMIPS 196249423Sdimstatic __inline void mips_sync_icache (void) 197249423Sdim{ 198249423Sdim __asm __volatile ( 199249423Sdim ".set push\n" 200249423Sdim ".set mips64\n" 201249423Sdim ".word 0x041f0000\n" /* xxx ICACHE */ 202249423Sdim "nop\n" 203249423Sdim ".set pop\n" 204249423Sdim : : ); 205249423Sdim} 206249423Sdim#endif 207249423Sdim 208249423SdimMIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE); 209249423SdimMIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG); 210249423SdimMIPS_RDRW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1); 211249423SdimMIPS_RDRW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2); 212249423SdimMIPS_RDRW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3); 213249423SdimMIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT); 214249423SdimMIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX); 215249423SdimMIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED); 216249423SdimMIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE); 217249423Sdim#if !defined(__mips_n64) 218249423SdimMIPS_RDWR32_COP0(excpc, MIPS_COP_0_EXC_PC); 219249423Sdim#endif 220249423SdimMIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS); 221249423Sdim 222249423Sdim/* XXX: Some of these registers are specific to MIPS32. */ 223249423Sdim#if !defined(__mips_n64) 224249423SdimMIPS_RDRW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0); 225249423SdimMIPS_RDRW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1); 226249423SdimMIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI); 227249423SdimMIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); 228249423Sdim#endif 229249423SdimMIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID); 230249423Sdim/* XXX 64-bit? */ 231249423SdimMIPS_RDRW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1); 232249423SdimMIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO); 233249423SdimMIPS_RDRW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1); 234249423SdimMIPS_RDRW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2); 235249423SdimMIPS_RDRW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3); 236249423SdimMIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI); 237249423SdimMIPS_RDRW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1); 238249423SdimMIPS_RDRW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2); 239249423SdimMIPS_RDRW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3); 240249423Sdim 241249423SdimMIPS_RDRW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0); 242249423SdimMIPS_RDRW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1); 243249423SdimMIPS_RDRW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2); 244249423SdimMIPS_RDRW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3); 245249423Sdim 246249423Sdim#undef MIPS_RDRW32_COP0 247249423Sdim 248249423Sdimstatic __inline register_t 249249423Sdimintr_disable(void) 250249423Sdim{ 251249423Sdim register_t s; 252249423Sdim 253249423Sdim s = mips_rd_status(); 254249423Sdim mips_wr_status(s & ~MIPS_SR_INT_IE); 255249423Sdim 256249423Sdim return (s & MIPS_SR_INT_IE); 257249423Sdim} 258249423Sdim 259249423Sdimstatic __inline register_t 260249423Sdimintr_enable(void) 261249423Sdim{ 262249423Sdim register_t s; 263249423Sdim 264249423Sdim s = mips_rd_status(); 265249423Sdim mips_wr_status(s | MIPS_SR_INT_IE); 266249423Sdim 267249423Sdim return (s); 268249423Sdim} 269249423Sdim 270249423Sdimstatic __inline void 271249423Sdimintr_restore(register_t ie) 272249423Sdim{ 273239462Sdim if (ie == MIPS_SR_INT_IE) { 274239462Sdim intr_enable(); 275239462Sdim } 276239462Sdim} 277239462Sdim 278239462Sdimstatic __inline uint32_t 279239462Sdimset_intr_mask(uint32_t mask) 280239462Sdim{ 281239462Sdim uint32_t ostatus; 282239462Sdim 283239462Sdim ostatus = mips_rd_status(); 284239462Sdim mask = (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_INT_MASK); 285 mips_wr_status(mask); 286 return (ostatus); 287} 288 289static __inline uint32_t 290get_intr_mask(void) 291{ 292 293 return (mips_rd_status() & MIPS_SR_INT_MASK); 294} 295 296static __inline void 297breakpoint(void) 298{ 299 __asm __volatile ("break"); 300} 301 302#if defined(__GNUC__) && !defined(__mips_o32) 303static inline uint64_t 304mips3_ld(const volatile uint64_t *va) 305{ 306 uint64_t rv; 307 308#if defined(_LP64) 309 rv = *va; 310#else 311 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 312#endif 313 314 return (rv); 315} 316 317static inline void 318mips3_sd(volatile uint64_t *va, uint64_t v) 319{ 320#if defined(_LP64) 321 *va = v; 322#else 323 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 324#endif 325} 326#else 327uint64_t mips3_ld(volatile uint64_t *va); 328void mips3_sd(volatile uint64_t *, uint64_t); 329#endif /* __GNUC__ */ 330 331#endif /* _KERNEL */ 332 333#define readb(va) (*(volatile uint8_t *) (va)) 334#define readw(va) (*(volatile uint16_t *) (va)) 335#define readl(va) (*(volatile uint32_t *) (va)) 336 337#define writeb(va, d) (*(volatile uint8_t *) (va) = (d)) 338#define writew(va, d) (*(volatile uint16_t *) (va) = (d)) 339#define writel(va, d) (*(volatile uint32_t *) (va) = (d)) 340 341/* 342 * I/O macros. 343 */ 344 345#define outb(a,v) (*(volatile unsigned char*)(a) = (v)) 346#define out8(a,v) (*(volatile unsigned char*)(a) = (v)) 347#define outw(a,v) (*(volatile unsigned short*)(a) = (v)) 348#define out16(a,v) outw(a,v) 349#define outl(a,v) (*(volatile unsigned int*)(a) = (v)) 350#define out32(a,v) outl(a,v) 351#define inb(a) (*(volatile unsigned char*)(a)) 352#define in8(a) (*(volatile unsigned char*)(a)) 353#define inw(a) (*(volatile unsigned short*)(a)) 354#define in16(a) inw(a) 355#define inl(a) (*(volatile unsigned int*)(a)) 356#define in32(a) inl(a) 357 358#define out8rb(a,v) (*(volatile unsigned char*)(a) = (v)) 359#define out16rb(a,v) (__out16rb((volatile uint16_t *)(a), v)) 360#define out32rb(a,v) (__out32rb((volatile uint32_t *)(a), v)) 361#define in8rb(a) (*(volatile unsigned char*)(a)) 362#define in16rb(a) (__in16rb((volatile uint16_t *)(a))) 363#define in32rb(a) (__in32rb((volatile uint32_t *)(a))) 364 365#define _swap_(x) (((x) >> 24) | ((x) << 24) | \ 366 (((x) >> 8) & 0xff00) | (((x) & 0xff00) << 8)) 367 368static __inline void __out32rb(volatile uint32_t *, uint32_t); 369static __inline void __out16rb(volatile uint16_t *, uint16_t); 370static __inline uint32_t __in32rb(volatile uint32_t *); 371static __inline uint16_t __in16rb(volatile uint16_t *); 372 373static __inline void 374__out32rb(volatile uint32_t *a, uint32_t v) 375{ 376 uint32_t _v_ = v; 377 378 _v_ = _swap_(_v_); 379 out32(a, _v_); 380} 381 382static __inline void 383__out16rb(volatile uint16_t *a, uint16_t v) 384{ 385 uint16_t _v_; 386 387 _v_ = ((v >> 8) & 0xff) | (v << 8); 388 out16(a, _v_); 389} 390 391static __inline uint32_t 392__in32rb(volatile uint32_t *a) 393{ 394 uint32_t _v_; 395 396 _v_ = in32(a); 397 _v_ = _swap_(_v_); 398 return _v_; 399} 400 401static __inline uint16_t 402__in16rb(volatile uint16_t *a) 403{ 404 uint16_t _v_; 405 406 _v_ = in16(a); 407 _v_ = ((_v_ >> 8) & 0xff) | (_v_ << 8); 408 return _v_; 409} 410 411void insb(uint8_t *, uint8_t *,int); 412void insw(uint16_t *, uint16_t *,int); 413void insl(uint32_t *, uint32_t *,int); 414void outsb(uint8_t *, const uint8_t *,int); 415void outsw(uint16_t *, const uint16_t *,int); 416void outsl(uint32_t *, const uint32_t *,int); 417u_int loadandclear(volatile u_int *addr); 418 419#endif /* !_MACHINE_CPUFUNC_H_ */ 420