cpufunc.h revision 216947
1/* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */ 2 3/*- 4 * Copyright (c) 2002-2004 Juli Mallett. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27/* 28 * Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved. 29 * 30 * Redistribution and use in source and binary forms, with or without 31 * modification, are permitted provided that the following conditions 32 * are met: 33 * 1. Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * 2. Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in the 37 * documentation and/or other materials provided with the distribution. 38 * 3. All advertising materials mentioning features or use of this software 39 * must display the following acknowledgement: 40 * This product includes software developed by Per Fogelstrom. 41 * 4. The name of the author may not be used to endorse or promote products 42 * derived from this software without specific prior written permission 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta 56 * $FreeBSD: head/sys/mips/include/cpufunc.h 216947 2011-01-04 02:33:48Z jmallett $ 57 */ 58 59#ifndef _MACHINE_CPUFUNC_H_ 60#define _MACHINE_CPUFUNC_H_ 61 62#include <sys/types.h> 63#include <machine/cpuregs.h> 64 65/* 66 * These functions are required by user-land atomi ops 67 */ 68 69static __inline void 70mips_barrier(void) 71{ 72 __asm __volatile (".set noreorder\n\t" 73 "nop\n\t" 74 "nop\n\t" 75 "nop\n\t" 76 "nop\n\t" 77 "nop\n\t" 78 "nop\n\t" 79 "nop\n\t" 80 "nop\n\t" 81 ".set reorder\n\t" 82 : : : "memory"); 83} 84 85static __inline void 86mips_cp0_sync(void) 87{ 88 __asm __volatile (__XSTRING(COP0_SYNC)); 89} 90 91static __inline void 92mips_wbflush(void) 93{ 94 __asm __volatile ("sync" : : : "memory"); 95 mips_barrier(); 96} 97 98static __inline void 99mips_read_membar(void) 100{ 101 /* Nil */ 102} 103 104static __inline void 105mips_write_membar(void) 106{ 107 mips_wbflush(); 108} 109 110#ifdef _KERNEL 111/* 112 * XXX 113 * It would be nice to add variants that read/write register_t, to avoid some 114 * ABI checks. 115 */ 116#if defined(__mips_n32) || defined(__mips_n64) 117#define MIPS_RDRW64_COP0(n,r) \ 118static __inline uint64_t \ 119mips_rd_ ## n (void) \ 120{ \ 121 int v0; \ 122 __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \ 123 : [v0] "=&r"(v0)); \ 124 mips_barrier(); \ 125 return (v0); \ 126} \ 127static __inline void \ 128mips_wr_ ## n (uint64_t a0) \ 129{ \ 130 __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \ 131 __XSTRING(COP0_SYNC)";" \ 132 "nop;" \ 133 "nop;" \ 134 : \ 135 : [a0] "r"(a0)); \ 136 mips_barrier(); \ 137} struct __hack 138 139#if defined(__mips_n64) 140MIPS_RDRW64_COP0(excpc, MIPS_COP_0_EXC_PC); 141MIPS_RDRW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0); 142MIPS_RDRW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1); 143MIPS_RDRW64_COP0(entryhi, MIPS_COP_0_TLB_HI); 144MIPS_RDRW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); 145#endif 146MIPS_RDRW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT); 147 148#undef MIPS_RDRW64_COP0 149#endif 150 151#define MIPS_RDRW32_COP0(n,r) \ 152static __inline uint32_t \ 153mips_rd_ ## n (void) \ 154{ \ 155 int v0; \ 156 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \ 157 : [v0] "=&r"(v0)); \ 158 mips_barrier(); \ 159 return (v0); \ 160} \ 161static __inline void \ 162mips_wr_ ## n (uint32_t a0) \ 163{ \ 164 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \ 165 __XSTRING(COP0_SYNC)";" \ 166 "nop;" \ 167 "nop;" \ 168 : \ 169 : [a0] "r"(a0)); \ 170 mips_barrier(); \ 171} struct __hack 172 173#define MIPS_RDRW32_COP0_SEL(n,r,s) \ 174static __inline uint32_t \ 175mips_rd_ ## n(void) \ 176{ \ 177 int v0; \ 178 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \ 179 : [v0] "=&r"(v0)); \ 180 mips_barrier(); \ 181 return (v0); \ 182} \ 183static __inline void \ 184mips_wr_ ## n(uint32_t a0) \ 185{ \ 186 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \ 187 __XSTRING(COP0_SYNC)";" \ 188 "nop;" \ 189 "nop;" \ 190 : \ 191 : [a0] "r"(a0)); \ 192 mips_barrier(); \ 193} struct __hack 194 195#ifdef CPU_CNMIPS 196static __inline void mips_sync_icache (void) 197{ 198 __asm __volatile ( 199 ".set push\n" 200 ".set mips64\n" 201 ".word 0x041f0000\n" /* xxx ICACHE */ 202 "nop\n" 203 ".set pop\n" 204 : : ); 205} 206#endif 207 208MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE); 209MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG); 210MIPS_RDRW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1); 211MIPS_RDRW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2); 212MIPS_RDRW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3); 213MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT); 214MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX); 215MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED); 216MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE); 217#if !defined(__mips_n64) 218MIPS_RDWR32_COP0(excpc, MIPS_COP_0_EXC_PC); 219#endif 220MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS); 221 222/* XXX: Some of these registers are specific to MIPS32. */ 223#if !defined(__mips_n64) 224MIPS_RDRW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0); 225MIPS_RDRW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1); 226MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI); 227MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); 228#endif 229MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID); 230/* XXX 64-bit? */ 231MIPS_RDRW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1); 232MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO); 233MIPS_RDRW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1); 234MIPS_RDRW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2); 235MIPS_RDRW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3); 236MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI); 237MIPS_RDRW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1); 238MIPS_RDRW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2); 239MIPS_RDRW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3); 240 241MIPS_RDRW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0); 242MIPS_RDRW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1); 243MIPS_RDRW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2); 244MIPS_RDRW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3); 245 246#undef MIPS_RDRW32_COP0 247 248static __inline register_t 249intr_disable(void) 250{ 251 register_t s; 252 253 s = mips_rd_status(); 254 mips_wr_status(s & ~MIPS_SR_INT_IE); 255 256 return (s & MIPS_SR_INT_IE); 257} 258 259static __inline register_t 260intr_enable(void) 261{ 262 register_t s; 263 264 s = mips_rd_status(); 265 mips_wr_status(s | MIPS_SR_INT_IE); 266 267 return (s); 268} 269 270static __inline void 271intr_restore(register_t ie) 272{ 273 if (ie == MIPS_SR_INT_IE) { 274 intr_enable(); 275 } 276} 277 278static __inline uint32_t 279set_intr_mask(uint32_t mask) 280{ 281 uint32_t ostatus; 282 283 ostatus = mips_rd_status(); 284 mask = (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_INT_MASK); 285 mips_wr_status(mask); 286 return (ostatus); 287} 288 289static __inline uint32_t 290get_intr_mask(void) 291{ 292 293 return (mips_rd_status() & MIPS_SR_INT_MASK); 294} 295 296static __inline void 297breakpoint(void) 298{ 299 __asm __volatile ("break"); 300} 301 302#if defined(__GNUC__) && !defined(__mips_o32) 303static inline uint64_t 304mips3_ld(const volatile uint64_t *va) 305{ 306 uint64_t rv; 307 308#if defined(_LP64) 309 rv = *va; 310#else 311 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 312#endif 313 314 return (rv); 315} 316 317static inline void 318mips3_sd(volatile uint64_t *va, uint64_t v) 319{ 320#if defined(_LP64) 321 *va = v; 322#else 323 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 324#endif 325} 326#else 327uint64_t mips3_ld(volatile uint64_t *va); 328void mips3_sd(volatile uint64_t *, uint64_t); 329#endif /* __GNUC__ */ 330 331#endif /* _KERNEL */ 332 333#define readb(va) (*(volatile uint8_t *) (va)) 334#define readw(va) (*(volatile uint16_t *) (va)) 335#define readl(va) (*(volatile uint32_t *) (va)) 336 337#define writeb(va, d) (*(volatile uint8_t *) (va) = (d)) 338#define writew(va, d) (*(volatile uint16_t *) (va) = (d)) 339#define writel(va, d) (*(volatile uint32_t *) (va) = (d)) 340 341/* 342 * I/O macros. 343 */ 344 345#define outb(a,v) (*(volatile unsigned char*)(a) = (v)) 346#define out8(a,v) (*(volatile unsigned char*)(a) = (v)) 347#define outw(a,v) (*(volatile unsigned short*)(a) = (v)) 348#define out16(a,v) outw(a,v) 349#define outl(a,v) (*(volatile unsigned int*)(a) = (v)) 350#define out32(a,v) outl(a,v) 351#define inb(a) (*(volatile unsigned char*)(a)) 352#define in8(a) (*(volatile unsigned char*)(a)) 353#define inw(a) (*(volatile unsigned short*)(a)) 354#define in16(a) inw(a) 355#define inl(a) (*(volatile unsigned int*)(a)) 356#define in32(a) inl(a) 357 358#define out8rb(a,v) (*(volatile unsigned char*)(a) = (v)) 359#define out16rb(a,v) (__out16rb((volatile uint16_t *)(a), v)) 360#define out32rb(a,v) (__out32rb((volatile uint32_t *)(a), v)) 361#define in8rb(a) (*(volatile unsigned char*)(a)) 362#define in16rb(a) (__in16rb((volatile uint16_t *)(a))) 363#define in32rb(a) (__in32rb((volatile uint32_t *)(a))) 364 365#define _swap_(x) (((x) >> 24) | ((x) << 24) | \ 366 (((x) >> 8) & 0xff00) | (((x) & 0xff00) << 8)) 367 368static __inline void __out32rb(volatile uint32_t *, uint32_t); 369static __inline void __out16rb(volatile uint16_t *, uint16_t); 370static __inline uint32_t __in32rb(volatile uint32_t *); 371static __inline uint16_t __in16rb(volatile uint16_t *); 372 373static __inline void 374__out32rb(volatile uint32_t *a, uint32_t v) 375{ 376 uint32_t _v_ = v; 377 378 _v_ = _swap_(_v_); 379 out32(a, _v_); 380} 381 382static __inline void 383__out16rb(volatile uint16_t *a, uint16_t v) 384{ 385 uint16_t _v_; 386 387 _v_ = ((v >> 8) & 0xff) | (v << 8); 388 out16(a, _v_); 389} 390 391static __inline uint32_t 392__in32rb(volatile uint32_t *a) 393{ 394 uint32_t _v_; 395 396 _v_ = in32(a); 397 _v_ = _swap_(_v_); 398 return _v_; 399} 400 401static __inline uint16_t 402__in16rb(volatile uint16_t *a) 403{ 404 uint16_t _v_; 405 406 _v_ = in16(a); 407 _v_ = ((_v_ >> 8) & 0xff) | (_v_ << 8); 408 return _v_; 409} 410 411void insb(uint8_t *, uint8_t *,int); 412void insw(uint16_t *, uint16_t *,int); 413void insl(uint32_t *, uint32_t *,int); 414void outsb(uint8_t *, const uint8_t *,int); 415void outsw(uint16_t *, const uint16_t *,int); 416void outsl(uint32_t *, const uint32_t *,int); 417u_int loadandclear(volatile u_int *addr); 418 419#endif /* !_MACHINE_CPUFUNC_H_ */ 420