if_krreg.h revision 178173
1178173Simp/*- 2178173Simp * Copyright (C) 2007 3178173Simp * Oleksandr Tymoshenko <gonzo@freebsd.org>. All rights reserved. 4178173Simp * 5178173Simp * Redistribution and use in source and binary forms, with or without 6178173Simp * modification, are permitted provided that the following conditions 7178173Simp * are met: 8178173Simp * 1. Redistributions of source code must retain the above copyright 9178173Simp * notice, this list of conditions and the following disclaimer. 10178173Simp * 2. Redistributions in binary form must reproduce the above copyright 11178173Simp * notice, this list of conditions and the following disclaimer in the 12178173Simp * documentation and/or other materials provided with the distribution. 13178173Simp * 14178173Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15178173Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16178173Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17178173Simp * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 18178173Simp * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19178173Simp * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20178173Simp * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21178173Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22178173Simp * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 23178173Simp * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24178173Simp * THE POSSIBILITY OF SUCH DAMAGE. 25178173Simp * 26178173Simp * $FreeBSD: head/sys/mips/mips32/idt/if_krreg.h 178173 2008-04-13 07:44:55Z imp $ 27178173Simp * 28178173Simp */ 29178173Simp 30178173Simp#ifndef __IF_KRREG_H__ 31178173Simp#define __IF_KRREG_H__ 32178173Simp 33178173Simp#define KR_ETHINTFC 0x0000 /* Ethernet interface control */ 34178173Simp#define ETH_INTFC_EN 0x0001 35178173Simp#define ETH_INTFC_RIP 0x0004 36178173Simp#define ETH_INTFC_EN 0x0001 37178173Simp#define KR_ETHFIFOTT 0x0004 /* Ethernet FIFO transmit threshold */ 38178173Simp#define KR_ETHARC 0x0008 /* Ethernet address recognition control */ 39178173Simp#define KR_ETHHASH0 0x000C /* Ethernet hash table 0 */ 40178173Simp#define KR_ETHHASH1 0x0010 /* Ethernet hash table 1 */ 41178173Simp#define KR_ETHPFS 0x0024 /* Ethernet pause frame status */ 42178173Simp#define KR_ETHMCP 0x0028 /* Ethernet management clock prescalar */ 43178173Simp#define KR_ETHSAL0 0x0100 /* Ethernet station address 0 low */ 44178173Simp#define KR_ETHSAH0 0x0104 /* Ethernet station address 0 high */ 45178173Simp#define KR_ETHSAL1 0x0108 /* Ethernet station address 1 low */ 46178173Simp#define KR_ETHSAH1 0x010C /* Ethernet station address 1 high */ 47178173Simp#define KR_ETHSAL2 0x0110 /* Ethernet station address 2 low */ 48178173Simp#define KR_ETHSAH2 0x0114 /* Ethernet station address 2 high */ 49178173Simp#define KR_ETHSAL3 0x0118 /* Ethernet station address 3 low */ 50178173Simp#define KR_ETHSAH3 0x011C /* Ethernet station address 3 high */ 51178173Simp#define KR_ETHRBC 0x0120 /* Ethernet receive byte count */ 52178173Simp#define KR_ETHRPC 0x0124 /* Ethernet receive packet count */ 53178173Simp#define KR_ETHRUPC 0x0128 /* Ethernet receive undersized packet cnt */ 54178173Simp#define KR_ETHRFC 0x012C /* Ethernet receive fragment count */ 55178173Simp#define KR_ETHTBC 0x0130 /* Ethernet transmit byte count */ 56178173Simp#define KR_ETHGPF 0x0134 /* Ethernet generate pause frame */ 57178173Simp#define KR_ETHMAC1 0x0200 /* Ethernet MAC configuration 1 */ 58178173Simp#define KR_ETH_MAC1_RE 0x01 59178173Simp#define KR_ETH_MAC1_PAF 0x02 60178173Simp#define KR_ETH_MAC1_MR 0x80 61178173Simp#define KR_ETHMAC2 0x0204 /* Ethernet MAC configuration 2 */ 62178173Simp#define KR_ETH_MAC2_FD 0x01 63178173Simp#define KR_ETH_MAC2_FLC 0x02 64178173Simp#define KR_ETH_MAC2_HFE 0x04 65178173Simp#define KR_ETH_MAC2_DC 0x08 66178173Simp#define KR_ETH_MAC2_CEN 0x10 67178173Simp#define KR_ETH_MAC2_PEN 0x20 68178173Simp#define KR_ETH_MAC2_VPE 0x08 69178173Simp#define KR_ETHIPGT 0x0208 /* Ethernet back-to-back inter-packet gap */ 70178173Simp#define KR_ETHIPGR 0x020C /* Ethernet non back-to-back inter-packet gap */ 71178173Simp#define KR_ETHCLRT 0x0210 /* Ethernet collision window retry */ 72178173Simp#define KR_ETHMAXF 0x0214 /* Ethernet maximum frame length */ 73178173Simp#define KR_ETHMTEST 0x021C /* Ethernet MAC test */ 74178173Simp#define KR_MIIMCFG 0x0220 /* MII management configuration */ 75178173Simp#define KR_MIIMCFG_R 0x8000 76178173Simp#define KR_MIIMCMD 0x0224 /* MII management command */ 77178173Simp#define KR_MIIMCMD_RD 0x01 78178173Simp#define KR_MIIMCMD_SCN 0x02 79178173Simp#define KR_MIIMADDR 0x0228 /* MII management address */ 80178173Simp#define KR_MIIMWTD 0x022C /* MII management write data */ 81178173Simp#define KR_MIIMRDD 0x0230 /* MII management read data */ 82178173Simp#define KR_MIIMIND 0x0234 /* MII management indicators */ 83178173Simp#define KR_MIIMIND_BSY 0x1 84178173Simp#define KR_MIIMIND_SCN 0x2 85178173Simp#define KR_MIIMIND_NV 0x4 86178173Simp#define KR_ETHCFSA0 0x0240 /* Ethernet control frame station address 0 */ 87178173Simp#define KR_ETHCFSA1 0x0244 /* Ethernet control frame station address 1 */ 88178173Simp#define KR_ETHCFSA2 0x0248 /* Ethernet control frame station address 2 */ 89178173Simp 90178173Simp#define KR_ETHIPGT_HALF_DUPLEX 0x12 91178173Simp#define KR_ETHIPGT_FULL_DUPLEX 0x15 92178173Simp 93178173Simp#define KR_TIMEOUT 0xf000 94178173Simp#define KR_MII_TIMEOUT 0xf000 95178173Simp 96178173Simp#define KR_RX_IRQ 40 97178173Simp#define KR_TX_IRQ 41 98178173Simp#define KR_RX_UND_IRQ 42 99178173Simp#define KR_TX_OVR_IRQ 43 100178173Simp#define RC32434_DMA_BASE_ADDR MIPS_PHYS_TO_KSEG1(0x18040000) 101178173Simp#define DMA_C 0x00 102178173Simp#define DMA_C_R 0x01 103178173Simp#define DMA_C_ABORT 0x10 104178173Simp#define DMA_S 0x04 105178173Simp#define DMA_S_F 0x01 106178173Simp#define DMA_S_D 0x02 107178173Simp#define DMA_S_C 0x04 108178173Simp#define DMA_S_E 0x08 109178173Simp#define DMA_S_H 0x10 110178173Simp#define DMA_SM 0x08 111178173Simp#define DMA_SM_F 0x01 112178173Simp#define DMA_SM_D 0x02 113178173Simp#define DMA_SM_C 0x04 114178173Simp#define DMA_SM_E 0x08 115178173Simp#define DMA_SM_H 0x10 116178173Simp#define DMA_DPTR 0x0C 117178173Simp#define DMA_NDPTR 0x10 118178173Simp 119178173Simp#define RC32434_DMA_CHAN_SIZE 0x14 120178173Simp#define KR_DMA_RXCHAN 0 121178173Simp#define KR_DMA_TXCHAN 1 122178173Simp 123178173Simp#define KR_DMA_READ_REG(chan, reg) \ 124178173Simp (*(volatile uint32_t *) \ 125178173Simp (RC32434_DMA_BASE_ADDR + chan * RC32434_DMA_CHAN_SIZE + reg)) 126178173Simp 127178173Simp#define KR_DMA_WRITE_REG(chan, reg, val) \ 128178173Simp ((*(volatile uint32_t *) \ 129178173Simp (RC32434_DMA_BASE_ADDR + chan * RC32434_DMA_CHAN_SIZE + reg)) = val) 130178173Simp 131178173Simp#define KR_DMA_SETBITS_REG(chan, reg, bits) \ 132178173Simp KR_DMA_WRITE_REG((chan), (reg), KR_DMA_READ_REG((chan), (reg)) | (bits)) 133178173Simp 134178173Simp#define KR_DMA_CLEARBITS_REG(chan, reg, bits) \ 135178173Simp KR_DMA_WRITE_REG((chan), (reg), \ 136178173Simp KR_DMA_READ_REG((chan), (reg)) & ~(bits)) 137178173Simp 138178173Simpstruct kr_desc { 139178173Simp uint32_t kr_ctl; 140178173Simp uint32_t kr_ca; 141178173Simp uint32_t kr_devcs; 142178173Simp uint32_t kr_link; 143178173Simp}; 144178173Simp 145178173Simp 146178173Simp#define KR_DMASIZE(len) ((len) & ((1 << 18)-1)) 147178173Simp#define KR_PKTSIZE(len) ((len & 0xffff0000) >> 16) 148178173Simp 149178173Simp#define KR_CTL_COF 0x02000000 150178173Simp#define KR_CTL_COD 0x04000000 151178173Simp#define KR_CTL_IOF 0x08000000 152178173Simp#define KR_CTL_IOD 0x10000000 153178173Simp#define KR_CTL_T 0x20000000 154178173Simp#define KR_CTL_D 0x40000000 155178173Simp#define KR_CTL_F 0x80000000 156178173Simp 157178173Simp#define KR_DMARX_DEVCS_RSV 0x00000001 158178173Simp#define KR_DMARX_DEVCS_LD 0x00000002 159178173Simp#define KR_DMARX_DEVCS_ROK 0x00000004 160178173Simp#define KR_DMARX_DEVCS_FM 0x00000008 161178173Simp#define KR_DMARX_DEVCS_MP 0x00000010 162178173Simp#define KR_DMARX_DEVCS_BP 0x00000020 163178173Simp#define KR_DMARX_DEVCS_VLT 0x00000040 164178173Simp#define KR_DMARX_DEVCS_CF 0x00000080 165178173Simp#define KR_DMARX_DEVCS_OVR 0x00000100 166178173Simp#define KR_DMARX_DEVCS_CRC 0x00000200 167178173Simp#define KR_DMARX_DEVCS_CV 0x00000400 168178173Simp#define KR_DMARX_DEVCS_DB 0x00000800 169178173Simp#define KR_DMARX_DEVCS_LE 0x00001000 170178173Simp#define KR_DMARX_DEVCS_LOR 0x00002000 171178173Simp#define KR_DMARX_DEVCS_CES 0x00004000 172178173Simp 173178173Simp#define KR_DMATX_DEVCS_FD 0x00000001 174178173Simp#define KR_DMATX_DEVCS_LD 0x00000002 175178173Simp#define KR_DMATX_DEVCS_OEN 0x00000004 176178173Simp#define KR_DMATX_DEVCS_PEN 0x00000008 177178173Simp#define KR_DMATX_DEVCS_CEN 0x00000010 178178173Simp#define KR_DMATX_DEVCS_HEN 0x00000020 179178173Simp#define KR_DMATX_DEVCS_TOK 0x00000040 180178173Simp#define KR_DMATX_DEVCS_MP 0x00000080 181178173Simp#define KR_DMATX_DEVCS_BP 0x00000100 182178173Simp#define KR_DMATX_DEVCS_UND 0x00000200 183178173Simp#define KR_DMATX_DEVCS_OF 0x00000400 184178173Simp#define KR_DMATX_DEVCS_ED 0x00000800 185178173Simp#define KR_DMATX_DEVCS_EC 0x00001000 186178173Simp#define KR_DMATX_DEVCS_LC 0x00002000 187178173Simp#define KR_DMATX_DEVCS_TD 0x00004000 188178173Simp#define KR_DMATX_DEVCS_CRC 0x00008000 189178173Simp#define KR_DMATX_DEVCS_LE 0x00010000 190178173Simp 191178173Simp#define KR_RX_RING_CNT 128 192178173Simp#define KR_TX_RING_CNT 128 193178173Simp#define KR_TX_RING_SIZE sizeof(struct kr_desc) * KR_TX_RING_CNT 194178173Simp#define KR_RX_RING_SIZE sizeof(struct kr_desc) * KR_RX_RING_CNT 195178173Simp#define KR_RING_ALIGN sizeof(struct kr_desc) 196178173Simp#define KR_RX_ALIGN sizeof(uint32_t) 197178173Simp#define KR_MAXFRAGS 8 198178173Simp#define KR_TX_INTR_THRESH 8 199178173Simp 200178173Simp#define KR_TX_RING_ADDR(sc, i) \ 201178173Simp ((sc)->kr_rdata.kr_tx_ring_paddr + sizeof(struct kr_desc) * (i)) 202178173Simp#define KR_RX_RING_ADDR(sc, i) \ 203178173Simp ((sc)->kr_rdata.kr_rx_ring_paddr + sizeof(struct kr_desc) * (i)) 204178173Simp#define KR_INC(x,y) (x) = (((x) + 1) % y) 205178173Simp 206178173Simpstruct kr_txdesc { 207178173Simp struct mbuf *tx_m; 208178173Simp bus_dmamap_t tx_dmamap; 209178173Simp}; 210178173Simp 211178173Simpstruct kr_rxdesc { 212178173Simp struct mbuf *rx_m; 213178173Simp bus_dmamap_t rx_dmamap; 214178173Simp struct kr_desc *desc; 215178173Simp /* Use this values on error instead of allocating new mbuf */ 216178173Simp uint32_t saved_ctl, saved_ca; 217178173Simp}; 218178173Simp 219178173Simpstruct kr_chain_data { 220178173Simp bus_dma_tag_t kr_parent_tag; 221178173Simp bus_dma_tag_t kr_tx_tag; 222178173Simp struct kr_txdesc kr_txdesc[KR_TX_RING_CNT]; 223178173Simp bus_dma_tag_t kr_rx_tag; 224178173Simp struct kr_rxdesc kr_rxdesc[KR_RX_RING_CNT]; 225178173Simp bus_dma_tag_t kr_tx_ring_tag; 226178173Simp bus_dma_tag_t kr_rx_ring_tag; 227178173Simp bus_dmamap_t kr_tx_ring_map; 228178173Simp bus_dmamap_t kr_rx_ring_map; 229178173Simp bus_dmamap_t kr_rx_sparemap; 230178173Simp int kr_tx_pkts; 231178173Simp int kr_tx_prod; 232178173Simp int kr_tx_cons; 233178173Simp int kr_tx_cnt; 234178173Simp int kr_rx_cons; 235178173Simp}; 236178173Simp 237178173Simpstruct kr_ring_data { 238178173Simp struct kr_desc *kr_rx_ring; 239178173Simp struct kr_desc *kr_tx_ring; 240178173Simp bus_addr_t kr_rx_ring_paddr; 241178173Simp bus_addr_t kr_tx_ring_paddr; 242178173Simp}; 243178173Simp 244178173Simpstruct kr_softc { 245178173Simp struct ifnet *kr_ifp; /* interface info */ 246178173Simp bus_space_handle_t kr_bhandle; /* bus space handle */ 247178173Simp bus_space_tag_t kr_btag; /* bus space tag */ 248178173Simp device_t kr_dev; 249178173Simp struct resource *kr_res; 250178173Simp int kr_rid; 251178173Simp struct resource *kr_rx_irq; 252178173Simp void *kr_rx_intrhand; 253178173Simp struct resource *kr_tx_irq; 254178173Simp void *kr_tx_intrhand; 255178173Simp struct resource *kr_rx_und_irq; 256178173Simp void *kr_rx_und_intrhand; 257178173Simp struct resource *kr_tx_ovr_irq; 258178173Simp void *kr_tx_ovr_intrhand; 259178173Simp device_t kr_miibus; 260178173Simp bus_dma_tag_t kr_parent_tag; 261178173Simp bus_dma_tag_t kr_tag; 262178173Simp struct mtx kr_mtx; 263178173Simp struct callout kr_stat_callout; 264178173Simp struct task kr_link_task; 265178173Simp struct kr_chain_data kr_cdata; 266178173Simp struct kr_ring_data kr_rdata; 267178173Simp int kr_link_status; 268178173Simp int kr_detach; 269178173Simp}; 270178173Simp 271178173Simp#define KR_LOCK(_sc) mtx_lock(&(_sc)->kr_mtx) 272178173Simp#define KR_UNLOCK(_sc) mtx_unlock(&(_sc)->kr_mtx) 273178173Simp#define KR_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->kr_mtx, MA_OWNED) 274178173Simp 275178173Simp/* 276178173Simp * register space access macros 277178173Simp */ 278178173Simp#define CSR_WRITE_4(sc, reg, val) \ 279178173Simp bus_space_write_4(sc->kr_btag, sc->kr_bhandle, reg, val) 280178173Simp 281178173Simp#define CSR_READ_4(sc, reg) \ 282178173Simp bus_space_read_4(sc->kr_btag, sc->kr_bhandle, reg) 283178173Simp 284178173Simp#endif /* __IF_KRREG_H__ */ 285