1/*- 2 * Copyright (C) 2007 3 * Oleksandr Tymoshenko <gonzo@freebsd.org>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 23 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: releng/11.0/sys/mips/idt/if_krreg.h 202175 2010-01-12 21:36:08Z imp $ 27 * 28 */ 29 30#ifndef __IF_KRREG_H__ 31#define __IF_KRREG_H__ 32 33#define KR_ETHINTFC 0x0000 /* Ethernet interface control */ 34#define ETH_INTFC_EN 0x0001 35#define ETH_INTFC_RIP 0x0004 36#define ETH_INTFC_EN 0x0001 37#define KR_ETHFIFOTT 0x0004 /* Ethernet FIFO transmit threshold */ 38#define KR_ETHARC 0x0008 /* Ethernet address recognition control */ 39#define KR_ETHHASH0 0x000C /* Ethernet hash table 0 */ 40#define KR_ETHHASH1 0x0010 /* Ethernet hash table 1 */ 41#define KR_ETHPFS 0x0024 /* Ethernet pause frame status */ 42#define KR_ETHMCP 0x0028 /* Ethernet management clock prescalar */ 43#define KR_ETHSAL0 0x0100 /* Ethernet station address 0 low */ 44#define KR_ETHSAH0 0x0104 /* Ethernet station address 0 high */ 45#define KR_ETHSAL1 0x0108 /* Ethernet station address 1 low */ 46#define KR_ETHSAH1 0x010C /* Ethernet station address 1 high */ 47#define KR_ETHSAL2 0x0110 /* Ethernet station address 2 low */ 48#define KR_ETHSAH2 0x0114 /* Ethernet station address 2 high */ 49#define KR_ETHSAL3 0x0118 /* Ethernet station address 3 low */ 50#define KR_ETHSAH3 0x011C /* Ethernet station address 3 high */ 51#define KR_ETHRBC 0x0120 /* Ethernet receive byte count */ 52#define KR_ETHRPC 0x0124 /* Ethernet receive packet count */ 53#define KR_ETHRUPC 0x0128 /* Ethernet receive undersized packet cnt */ 54#define KR_ETHRFC 0x012C /* Ethernet receive fragment count */ 55#define KR_ETHTBC 0x0130 /* Ethernet transmit byte count */ 56#define KR_ETHGPF 0x0134 /* Ethernet generate pause frame */ 57#define KR_ETHMAC1 0x0200 /* Ethernet MAC configuration 1 */ 58#define KR_ETH_MAC1_RE 0x01 59#define KR_ETH_MAC1_PAF 0x02 60#define KR_ETH_MAC1_MR 0x80 61#define KR_ETHMAC2 0x0204 /* Ethernet MAC configuration 2 */ 62#define KR_ETH_MAC2_FD 0x01 63#define KR_ETH_MAC2_FLC 0x02 64#define KR_ETH_MAC2_HFE 0x04 65#define KR_ETH_MAC2_DC 0x08 66#define KR_ETH_MAC2_CEN 0x10 67#define KR_ETH_MAC2_PEN 0x20 68#define KR_ETH_MAC2_VPE 0x08 69#define KR_ETHIPGT 0x0208 /* Ethernet back-to-back inter-packet gap */ 70#define KR_ETHIPGR 0x020C /* Ethernet non back-to-back inter-packet gap */ 71#define KR_ETHCLRT 0x0210 /* Ethernet collision window retry */ 72#define KR_ETHMAXF 0x0214 /* Ethernet maximum frame length */ 73#define KR_ETHMTEST 0x021C /* Ethernet MAC test */ 74#define KR_MIIMCFG 0x0220 /* MII management configuration */ 75#define KR_MIIMCFG_R 0x8000 76#define KR_MIIMCMD 0x0224 /* MII management command */ 77#define KR_MIIMCMD_RD 0x01 78#define KR_MIIMCMD_SCN 0x02 79#define KR_MIIMADDR 0x0228 /* MII management address */ 80#define KR_MIIMWTD 0x022C /* MII management write data */ 81#define KR_MIIMRDD 0x0230 /* MII management read data */ 82#define KR_MIIMIND 0x0234 /* MII management indicators */ 83#define KR_MIIMIND_BSY 0x1 84#define KR_MIIMIND_SCN 0x2 85#define KR_MIIMIND_NV 0x4 86#define KR_ETHCFSA0 0x0240 /* Ethernet control frame station address 0 */ 87#define KR_ETHCFSA1 0x0244 /* Ethernet control frame station address 1 */ 88#define KR_ETHCFSA2 0x0248 /* Ethernet control frame station address 2 */ 89 90#define KR_ETHIPGT_HALF_DUPLEX 0x12 91#define KR_ETHIPGT_FULL_DUPLEX 0x15 92 93#define KR_TIMEOUT 0xf000 94#define KR_MII_TIMEOUT 0xf000 95 96#define KR_RX_IRQ 40 97#define KR_TX_IRQ 41 98#define KR_RX_UND_IRQ 42 99#define KR_TX_OVR_IRQ 43 100#define RC32434_DMA_BASE_ADDR MIPS_PHYS_TO_KSEG1(0x18040000) 101#define DMA_C 0x00 102#define DMA_C_R 0x01 103#define DMA_C_ABORT 0x10 104#define DMA_S 0x04 105#define DMA_S_F 0x01 106#define DMA_S_D 0x02 107#define DMA_S_C 0x04 108#define DMA_S_E 0x08 109#define DMA_S_H 0x10 110#define DMA_SM 0x08 111#define DMA_SM_F 0x01 112#define DMA_SM_D 0x02 113#define DMA_SM_C 0x04 114#define DMA_SM_E 0x08 115#define DMA_SM_H 0x10 116#define DMA_DPTR 0x0C 117#define DMA_NDPTR 0x10 118 119#define RC32434_DMA_CHAN_SIZE 0x14 120#define KR_DMA_RXCHAN 0 121#define KR_DMA_TXCHAN 1 122 123#define KR_DMA_READ_REG(chan, reg) \ 124 (*(volatile uint32_t *) \ 125 (RC32434_DMA_BASE_ADDR + chan * RC32434_DMA_CHAN_SIZE + reg)) 126 127#define KR_DMA_WRITE_REG(chan, reg, val) \ 128 ((*(volatile uint32_t *) \ 129 (RC32434_DMA_BASE_ADDR + chan * RC32434_DMA_CHAN_SIZE + reg)) = val) 130 131#define KR_DMA_SETBITS_REG(chan, reg, bits) \ 132 KR_DMA_WRITE_REG((chan), (reg), KR_DMA_READ_REG((chan), (reg)) | (bits)) 133 134#define KR_DMA_CLEARBITS_REG(chan, reg, bits) \ 135 KR_DMA_WRITE_REG((chan), (reg), \ 136 KR_DMA_READ_REG((chan), (reg)) & ~(bits)) 137 138struct kr_desc { 139 uint32_t kr_ctl; 140 uint32_t kr_ca; 141 uint32_t kr_devcs; 142 uint32_t kr_link; 143}; 144 145 146#define KR_DMASIZE(len) ((len) & ((1 << 18)-1)) 147#define KR_PKTSIZE(len) ((len & 0xffff0000) >> 16) 148 149#define KR_CTL_COF 0x02000000 150#define KR_CTL_COD 0x04000000 151#define KR_CTL_IOF 0x08000000 152#define KR_CTL_IOD 0x10000000 153#define KR_CTL_T 0x20000000 154#define KR_CTL_D 0x40000000 155#define KR_CTL_F 0x80000000 156 157#define KR_DMARX_DEVCS_RSV 0x00000001 158#define KR_DMARX_DEVCS_LD 0x00000002 159#define KR_DMARX_DEVCS_ROK 0x00000004 160#define KR_DMARX_DEVCS_FM 0x00000008 161#define KR_DMARX_DEVCS_MP 0x00000010 162#define KR_DMARX_DEVCS_BP 0x00000020 163#define KR_DMARX_DEVCS_VLT 0x00000040 164#define KR_DMARX_DEVCS_CF 0x00000080 165#define KR_DMARX_DEVCS_OVR 0x00000100 166#define KR_DMARX_DEVCS_CRC 0x00000200 167#define KR_DMARX_DEVCS_CV 0x00000400 168#define KR_DMARX_DEVCS_DB 0x00000800 169#define KR_DMARX_DEVCS_LE 0x00001000 170#define KR_DMARX_DEVCS_LOR 0x00002000 171#define KR_DMARX_DEVCS_CES 0x00004000 172 173#define KR_DMATX_DEVCS_FD 0x00000001 174#define KR_DMATX_DEVCS_LD 0x00000002 175#define KR_DMATX_DEVCS_OEN 0x00000004 176#define KR_DMATX_DEVCS_PEN 0x00000008 177#define KR_DMATX_DEVCS_CEN 0x00000010 178#define KR_DMATX_DEVCS_HEN 0x00000020 179#define KR_DMATX_DEVCS_TOK 0x00000040 180#define KR_DMATX_DEVCS_MP 0x00000080 181#define KR_DMATX_DEVCS_BP 0x00000100 182#define KR_DMATX_DEVCS_UND 0x00000200 183#define KR_DMATX_DEVCS_OF 0x00000400 184#define KR_DMATX_DEVCS_ED 0x00000800 185#define KR_DMATX_DEVCS_EC 0x00001000 186#define KR_DMATX_DEVCS_LC 0x00002000 187#define KR_DMATX_DEVCS_TD 0x00004000 188#define KR_DMATX_DEVCS_CRC 0x00008000 189#define KR_DMATX_DEVCS_LE 0x00010000 190 191#define KR_RX_RING_CNT 128 192#define KR_TX_RING_CNT 128 193#define KR_TX_RING_SIZE sizeof(struct kr_desc) * KR_TX_RING_CNT 194#define KR_RX_RING_SIZE sizeof(struct kr_desc) * KR_RX_RING_CNT 195#define KR_RING_ALIGN sizeof(struct kr_desc) 196#define KR_RX_ALIGN sizeof(uint32_t) 197#define KR_MAXFRAGS 8 198#define KR_TX_INTR_THRESH 8 199 200#define KR_TX_RING_ADDR(sc, i) \ 201 ((sc)->kr_rdata.kr_tx_ring_paddr + sizeof(struct kr_desc) * (i)) 202#define KR_RX_RING_ADDR(sc, i) \ 203 ((sc)->kr_rdata.kr_rx_ring_paddr + sizeof(struct kr_desc) * (i)) 204#define KR_INC(x,y) (x) = (((x) + 1) % y) 205 206struct kr_txdesc { 207 struct mbuf *tx_m; 208 bus_dmamap_t tx_dmamap; 209}; 210 211struct kr_rxdesc { 212 struct mbuf *rx_m; 213 bus_dmamap_t rx_dmamap; 214 struct kr_desc *desc; 215 /* Use this values on error instead of allocating new mbuf */ 216 uint32_t saved_ctl, saved_ca; 217}; 218 219struct kr_chain_data { 220 bus_dma_tag_t kr_parent_tag; 221 bus_dma_tag_t kr_tx_tag; 222 struct kr_txdesc kr_txdesc[KR_TX_RING_CNT]; 223 bus_dma_tag_t kr_rx_tag; 224 struct kr_rxdesc kr_rxdesc[KR_RX_RING_CNT]; 225 bus_dma_tag_t kr_tx_ring_tag; 226 bus_dma_tag_t kr_rx_ring_tag; 227 bus_dmamap_t kr_tx_ring_map; 228 bus_dmamap_t kr_rx_ring_map; 229 bus_dmamap_t kr_rx_sparemap; 230 int kr_tx_pkts; 231 int kr_tx_prod; 232 int kr_tx_cons; 233 int kr_tx_cnt; 234 int kr_rx_cons; 235}; 236 237struct kr_ring_data { 238 struct kr_desc *kr_rx_ring; 239 struct kr_desc *kr_tx_ring; 240 bus_addr_t kr_rx_ring_paddr; 241 bus_addr_t kr_tx_ring_paddr; 242}; 243 244struct kr_softc { 245 struct ifnet *kr_ifp; /* interface info */ 246 bus_space_handle_t kr_bhandle; /* bus space handle */ 247 bus_space_tag_t kr_btag; /* bus space tag */ 248 device_t kr_dev; 249 struct resource *kr_res; 250 int kr_rid; 251 struct resource *kr_rx_irq; 252 void *kr_rx_intrhand; 253 struct resource *kr_tx_irq; 254 void *kr_tx_intrhand; 255 struct resource *kr_rx_und_irq; 256 void *kr_rx_und_intrhand; 257 struct resource *kr_tx_ovr_irq; 258 void *kr_tx_ovr_intrhand; 259 device_t kr_miibus; 260 bus_dma_tag_t kr_parent_tag; 261 bus_dma_tag_t kr_tag; 262 struct mtx kr_mtx; 263 struct callout kr_stat_callout; 264 struct task kr_link_task; 265 struct kr_chain_data kr_cdata; 266 struct kr_ring_data kr_rdata; 267 int kr_link_status; 268 int kr_detach; 269}; 270 271#define KR_LOCK(_sc) mtx_lock(&(_sc)->kr_mtx) 272#define KR_UNLOCK(_sc) mtx_unlock(&(_sc)->kr_mtx) 273#define KR_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->kr_mtx, MA_OWNED) 274 275/* 276 * register space access macros 277 */ 278#define CSR_WRITE_4(sc, reg, val) \ 279 bus_space_write_4(sc->kr_btag, sc->kr_bhandle, reg, val) 280 281#define CSR_READ_4(sc, reg) \ 282 bus_space_read_4(sc->kr_btag, sc->kr_bhandle, reg) 283 284#endif /* __IF_KRREG_H__ */ 285