1270866Simp/* 2270866Simp * Copyright (c) 2014 MundoReader S.L. 3270866Simp * Author: Heiko Stuebner <heiko@sntech.de> 4270866Simp * 5270866Simp * This program is free software; you can redistribute it and/or modify 6270866Simp * it under the terms of the GNU General Public License as published by 7270866Simp * the Free Software Foundation; either version 2 of the License, or 8270866Simp * (at your option) any later version. 9270866Simp * 10270866Simp * This program is distributed in the hope that it will be useful, 11270866Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 12270866Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13270866Simp * GNU General Public License for more details. 14270866Simp */ 15270866Simp 16295436Sandrew#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H 17295436Sandrew#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H 18295436Sandrew 19270866Simp/* core clocks */ 20270866Simp#define PLL_APLL 1 21270866Simp#define PLL_DPLL 2 22270866Simp#define PLL_CPLL 3 23270866Simp#define PLL_GPLL 4 24270866Simp#define PLL_NPLL 5 25279385Simp#define ARMCLK 6 26270866Simp 27270866Simp/* sclk gates (special clocks) */ 28270866Simp#define SCLK_GPU 64 29270866Simp#define SCLK_SPI0 65 30270866Simp#define SCLK_SPI1 66 31270866Simp#define SCLK_SPI2 67 32270866Simp#define SCLK_SDMMC 68 33270866Simp#define SCLK_SDIO0 69 34270866Simp#define SCLK_SDIO1 70 35270866Simp#define SCLK_EMMC 71 36270866Simp#define SCLK_TSADC 72 37270866Simp#define SCLK_SARADC 73 38270866Simp#define SCLK_PS2C 74 39270866Simp#define SCLK_NANDC0 75 40270866Simp#define SCLK_NANDC1 76 41270866Simp#define SCLK_UART0 77 42270866Simp#define SCLK_UART1 78 43270866Simp#define SCLK_UART2 79 44270866Simp#define SCLK_UART3 80 45270866Simp#define SCLK_UART4 81 46270866Simp#define SCLK_I2S0 82 47270866Simp#define SCLK_SPDIF 83 48270866Simp#define SCLK_SPDIF8CH 84 49270866Simp#define SCLK_TIMER0 85 50270866Simp#define SCLK_TIMER1 86 51270866Simp#define SCLK_TIMER2 87 52270866Simp#define SCLK_TIMER3 88 53270866Simp#define SCLK_TIMER4 89 54270866Simp#define SCLK_TIMER5 90 55270866Simp#define SCLK_TIMER6 91 56270866Simp#define SCLK_HSADC 92 57270866Simp#define SCLK_OTGPHY0 93 58270866Simp#define SCLK_OTGPHY1 94 59270866Simp#define SCLK_OTGPHY2 95 60270866Simp#define SCLK_OTG_ADP 96 61270866Simp#define SCLK_HSICPHY480M 97 62270866Simp#define SCLK_HSICPHY12M 98 63270866Simp#define SCLK_MACREF 99 64270866Simp#define SCLK_LCDC_PWM0 100 65270866Simp#define SCLK_LCDC_PWM1 101 66270866Simp#define SCLK_MAC_RX 102 67270866Simp#define SCLK_MAC_TX 103 68279385Simp#define SCLK_EDP_24M 104 69279385Simp#define SCLK_EDP 105 70279385Simp#define SCLK_RGA 106 71279385Simp#define SCLK_ISP 107 72279385Simp#define SCLK_ISP_JPE 108 73279385Simp#define SCLK_HDMI_HDCP 109 74279385Simp#define SCLK_HDMI_CEC 110 75279385Simp#define SCLK_HEVC_CABAC 111 76279385Simp#define SCLK_HEVC_CORE 112 77279385Simp#define SCLK_I2S0_OUT 113 78279385Simp#define SCLK_SDMMC_DRV 114 79279385Simp#define SCLK_SDIO0_DRV 115 80279385Simp#define SCLK_SDIO1_DRV 116 81279385Simp#define SCLK_EMMC_DRV 117 82279385Simp#define SCLK_SDMMC_SAMPLE 118 83279385Simp#define SCLK_SDIO0_SAMPLE 119 84279385Simp#define SCLK_SDIO1_SAMPLE 120 85279385Simp#define SCLK_EMMC_SAMPLE 121 86279385Simp#define SCLK_USBPHY480M_SRC 122 87279385Simp#define SCLK_PVTM_CORE 123 88279385Simp#define SCLK_PVTM_GPU 124 89295436Sandrew#define SCLK_CRYPTO 125 90295436Sandrew#define SCLK_MIPIDSI_24M 126 91270866Simp 92279385Simp#define SCLK_MAC 151 93279385Simp#define SCLK_MACREF_OUT 152 94279385Simp 95270866Simp#define DCLK_VOP0 190 96270866Simp#define DCLK_VOP1 191 97270866Simp 98270866Simp/* aclk gates */ 99270866Simp#define ACLK_GPU 192 100270866Simp#define ACLK_DMAC1 193 101270866Simp#define ACLK_DMAC2 194 102270866Simp#define ACLK_MMU 195 103270866Simp#define ACLK_GMAC 196 104270866Simp#define ACLK_VOP0 197 105270866Simp#define ACLK_VOP1 198 106270866Simp#define ACLK_CRYPTO 199 107270866Simp#define ACLK_RGA 200 108279385Simp#define ACLK_RGA_NIU 201 109279385Simp#define ACLK_IEP 202 110279385Simp#define ACLK_VIO0_NIU 203 111279385Simp#define ACLK_VIP 204 112279385Simp#define ACLK_ISP 205 113279385Simp#define ACLK_VIO1_NIU 206 114279385Simp#define ACLK_HEVC 207 115279385Simp#define ACLK_VCODEC 208 116279385Simp#define ACLK_CPU 209 117279385Simp#define ACLK_PERI 210 118270866Simp 119270866Simp/* pclk gates */ 120270866Simp#define PCLK_GPIO0 320 121270866Simp#define PCLK_GPIO1 321 122270866Simp#define PCLK_GPIO2 322 123270866Simp#define PCLK_GPIO3 323 124270866Simp#define PCLK_GPIO4 324 125270866Simp#define PCLK_GPIO5 325 126270866Simp#define PCLK_GPIO6 326 127270866Simp#define PCLK_GPIO7 327 128270866Simp#define PCLK_GPIO8 328 129270866Simp#define PCLK_GRF 329 130270866Simp#define PCLK_SGRF 330 131270866Simp#define PCLK_PMU 331 132270866Simp#define PCLK_I2C0 332 133270866Simp#define PCLK_I2C1 333 134270866Simp#define PCLK_I2C2 334 135270866Simp#define PCLK_I2C3 335 136270866Simp#define PCLK_I2C4 336 137270866Simp#define PCLK_I2C5 337 138270866Simp#define PCLK_SPI0 338 139270866Simp#define PCLK_SPI1 339 140270866Simp#define PCLK_SPI2 340 141270866Simp#define PCLK_UART0 341 142270866Simp#define PCLK_UART1 342 143270866Simp#define PCLK_UART2 343 144270866Simp#define PCLK_UART3 344 145270866Simp#define PCLK_UART4 345 146270866Simp#define PCLK_TSADC 346 147270866Simp#define PCLK_SARADC 347 148270866Simp#define PCLK_SIM 348 149270866Simp#define PCLK_GMAC 349 150270866Simp#define PCLK_PWM 350 151270866Simp#define PCLK_RKPWM 351 152270866Simp#define PCLK_PS2C 352 153270866Simp#define PCLK_TIMER 353 154270866Simp#define PCLK_TZPC 354 155279385Simp#define PCLK_EDP_CTRL 355 156279385Simp#define PCLK_MIPI_DSI0 356 157279385Simp#define PCLK_MIPI_DSI1 357 158279385Simp#define PCLK_MIPI_CSI 358 159279385Simp#define PCLK_LVDS_PHY 359 160279385Simp#define PCLK_HDMI_CTRL 360 161279385Simp#define PCLK_VIO2_H2P 361 162279385Simp#define PCLK_CPU 362 163279385Simp#define PCLK_PERI 363 164279385Simp#define PCLK_DDRUPCTL0 364 165279385Simp#define PCLK_PUBL0 365 166279385Simp#define PCLK_DDRUPCTL1 366 167279385Simp#define PCLK_PUBL1 367 168279385Simp#define PCLK_WDT 368 169295436Sandrew#define PCLK_EFUSE256 369 170295436Sandrew#define PCLK_EFUSE1024 370 171270866Simp 172270866Simp/* hclk gates */ 173270866Simp#define HCLK_GPS 448 174270866Simp#define HCLK_OTG0 449 175270866Simp#define HCLK_USBHOST0 450 176270866Simp#define HCLK_USBHOST1 451 177270866Simp#define HCLK_HSIC 452 178270866Simp#define HCLK_NANDC0 453 179270866Simp#define HCLK_NANDC1 454 180270866Simp#define HCLK_TSP 455 181270866Simp#define HCLK_SDMMC 456 182270866Simp#define HCLK_SDIO0 457 183270866Simp#define HCLK_SDIO1 458 184270866Simp#define HCLK_EMMC 459 185270866Simp#define HCLK_HSADC 460 186270866Simp#define HCLK_CRYPTO 461 187270866Simp#define HCLK_I2S0 462 188270866Simp#define HCLK_SPDIF 463 189270866Simp#define HCLK_SPDIF8CH 464 190270866Simp#define HCLK_VOP0 465 191270866Simp#define HCLK_VOP1 466 192270866Simp#define HCLK_ROM 467 193270866Simp#define HCLK_IEP 468 194270866Simp#define HCLK_ISP 469 195270866Simp#define HCLK_RGA 470 196279385Simp#define HCLK_VIO_AHB_ARBI 471 197279385Simp#define HCLK_VIO_NIU 472 198279385Simp#define HCLK_VIP 473 199279385Simp#define HCLK_VIO2_H2P 474 200279385Simp#define HCLK_HEVC 475 201279385Simp#define HCLK_VCODEC 476 202279385Simp#define HCLK_CPU 477 203279385Simp#define HCLK_PERI 478 204270866Simp 205279385Simp#define CLK_NR_CLKS (HCLK_PERI + 1) 206270866Simp 207270866Simp/* soft-reset indices */ 208270866Simp#define SRST_CORE0 0 209270866Simp#define SRST_CORE1 1 210270866Simp#define SRST_CORE2 2 211270866Simp#define SRST_CORE3 3 212270866Simp#define SRST_CORE0_PO 4 213270866Simp#define SRST_CORE1_PO 5 214270866Simp#define SRST_CORE2_PO 6 215270866Simp#define SRST_CORE3_PO 7 216270866Simp#define SRST_PDCORE_STRSYS 8 217270866Simp#define SRST_PDBUS_STRSYS 9 218270866Simp#define SRST_L2C 10 219270866Simp#define SRST_TOPDBG 11 220270866Simp#define SRST_CORE0_DBG 12 221270866Simp#define SRST_CORE1_DBG 13 222270866Simp#define SRST_CORE2_DBG 14 223270866Simp#define SRST_CORE3_DBG 15 224270866Simp 225270866Simp#define SRST_PDBUG_AHB_ARBITOR 16 226270866Simp#define SRST_EFUSE256 17 227270866Simp#define SRST_DMAC1 18 228270866Simp#define SRST_INTMEM 19 229270866Simp#define SRST_ROM 20 230270866Simp#define SRST_SPDIF8CH 21 231270866Simp#define SRST_TIMER 22 232270866Simp#define SRST_I2S0 23 233270866Simp#define SRST_SPDIF 24 234270866Simp#define SRST_TIMER0 25 235270866Simp#define SRST_TIMER1 26 236270866Simp#define SRST_TIMER2 27 237270866Simp#define SRST_TIMER3 28 238270866Simp#define SRST_TIMER4 29 239270866Simp#define SRST_TIMER5 30 240270866Simp#define SRST_EFUSE 31 241270866Simp 242270866Simp#define SRST_GPIO0 32 243270866Simp#define SRST_GPIO1 33 244270866Simp#define SRST_GPIO2 34 245270866Simp#define SRST_GPIO3 35 246270866Simp#define SRST_GPIO4 36 247270866Simp#define SRST_GPIO5 37 248270866Simp#define SRST_GPIO6 38 249270866Simp#define SRST_GPIO7 39 250270866Simp#define SRST_GPIO8 40 251270866Simp#define SRST_I2C0 42 252270866Simp#define SRST_I2C1 43 253270866Simp#define SRST_I2C2 44 254270866Simp#define SRST_I2C3 45 255270866Simp#define SRST_I2C4 46 256270866Simp#define SRST_I2C5 47 257270866Simp 258270866Simp#define SRST_DWPWM 48 259270866Simp#define SRST_MMC_PERI 49 260270866Simp#define SRST_PERIPH_MMU 50 261270866Simp#define SRST_DAP 51 262270866Simp#define SRST_DAP_SYS 52 263270866Simp#define SRST_TPIU 53 264270866Simp#define SRST_PMU_APB 54 265270866Simp#define SRST_GRF 55 266270866Simp#define SRST_PMU 56 267270866Simp#define SRST_PERIPH_AXI 57 268270866Simp#define SRST_PERIPH_AHB 58 269270866Simp#define SRST_PERIPH_APB 59 270270866Simp#define SRST_PERIPH_NIU 60 271270866Simp#define SRST_PDPERI_AHB_ARBI 61 272270866Simp#define SRST_EMEM 62 273270866Simp#define SRST_USB_PERI 63 274270866Simp 275270866Simp#define SRST_DMAC2 64 276270866Simp#define SRST_MAC 66 277270866Simp#define SRST_GPS 67 278270866Simp#define SRST_RKPWM 69 279270866Simp#define SRST_CCP 71 280270866Simp#define SRST_USBHOST0 72 281270866Simp#define SRST_HSIC 73 282270866Simp#define SRST_HSIC_AUX 74 283270866Simp#define SRST_HSIC_PHY 75 284270866Simp#define SRST_HSADC 76 285270866Simp#define SRST_NANDC0 77 286270866Simp#define SRST_NANDC1 78 287270866Simp 288270866Simp#define SRST_TZPC 80 289270866Simp#define SRST_SPI0 83 290270866Simp#define SRST_SPI1 84 291270866Simp#define SRST_SPI2 85 292270866Simp#define SRST_SARADC 87 293270866Simp#define SRST_PDALIVE_NIU 88 294270866Simp#define SRST_PDPMU_INTMEM 89 295270866Simp#define SRST_PDPMU_NIU 90 296270866Simp#define SRST_SGRF 91 297270866Simp 298270866Simp#define SRST_VIO_ARBI 96 299270866Simp#define SRST_RGA_NIU 97 300270866Simp#define SRST_VIO0_NIU_AXI 98 301270866Simp#define SRST_VIO_NIU_AHB 99 302270866Simp#define SRST_LCDC0_AXI 100 303270866Simp#define SRST_LCDC0_AHB 101 304270866Simp#define SRST_LCDC0_DCLK 102 305270866Simp#define SRST_VIO1_NIU_AXI 103 306270866Simp#define SRST_VIP 104 307270866Simp#define SRST_RGA_CORE 105 308270866Simp#define SRST_IEP_AXI 106 309270866Simp#define SRST_IEP_AHB 107 310270866Simp#define SRST_RGA_AXI 108 311270866Simp#define SRST_RGA_AHB 109 312270866Simp#define SRST_ISP 110 313270866Simp#define SRST_EDP 111 314270866Simp 315270866Simp#define SRST_VCODEC_AXI 112 316270866Simp#define SRST_VCODEC_AHB 113 317270866Simp#define SRST_VIO_H2P 114 318270866Simp#define SRST_MIPIDSI0 115 319270866Simp#define SRST_MIPIDSI1 116 320270866Simp#define SRST_MIPICSI 117 321270866Simp#define SRST_LVDS_PHY 118 322270866Simp#define SRST_LVDS_CON 119 323270866Simp#define SRST_GPU 120 324270866Simp#define SRST_HDMI 121 325270866Simp#define SRST_CORE_PVTM 124 326270866Simp#define SRST_GPU_PVTM 125 327270866Simp 328270866Simp#define SRST_MMC0 128 329270866Simp#define SRST_SDIO0 129 330270866Simp#define SRST_SDIO1 130 331270866Simp#define SRST_EMMC 131 332270866Simp#define SRST_USBOTG_AHB 132 333270866Simp#define SRST_USBOTG_PHY 133 334270866Simp#define SRST_USBOTG_CON 134 335270866Simp#define SRST_USBHOST0_AHB 135 336270866Simp#define SRST_USBHOST0_PHY 136 337270866Simp#define SRST_USBHOST0_CON 137 338270866Simp#define SRST_USBHOST1_AHB 138 339270866Simp#define SRST_USBHOST1_PHY 139 340270866Simp#define SRST_USBHOST1_CON 140 341270866Simp#define SRST_USB_ADP 141 342270866Simp#define SRST_ACC_EFUSE 142 343279385Simp 344279385Simp#define SRST_CORESIGHT 144 345279385Simp#define SRST_PD_CORE_AHB_NOC 145 346279385Simp#define SRST_PD_CORE_APB_NOC 146 347279385Simp#define SRST_PD_CORE_MP_AXI 147 348279385Simp#define SRST_GIC 148 349279385Simp#define SRST_LCDC_PWM0 149 350279385Simp#define SRST_LCDC_PWM1 150 351279385Simp#define SRST_VIO0_H2P_BRG 151 352279385Simp#define SRST_VIO1_H2P_BRG 152 353279385Simp#define SRST_RGA_H2P_BRG 153 354279385Simp#define SRST_HEVC 154 355279385Simp#define SRST_TSADC 159 356279385Simp 357279385Simp#define SRST_DDRPHY0 160 358279385Simp#define SRST_DDRPHY0_APB 161 359279385Simp#define SRST_DDRCTRL0 162 360279385Simp#define SRST_DDRCTRL0_APB 163 361279385Simp#define SRST_DDRPHY0_CTRL 164 362279385Simp#define SRST_DDRPHY1 165 363279385Simp#define SRST_DDRPHY1_APB 166 364279385Simp#define SRST_DDRCTRL1 167 365279385Simp#define SRST_DDRCTRL1_APB 168 366279385Simp#define SRST_DDRPHY1_CTRL 169 367279385Simp#define SRST_DDRMSCH0 170 368279385Simp#define SRST_DDRMSCH1 171 369279385Simp#define SRST_CRYPTO 174 370279385Simp#define SRST_C2C_HOST 175 371279385Simp 372279385Simp#define SRST_LCDC1_AXI 176 373279385Simp#define SRST_LCDC1_AHB 177 374279385Simp#define SRST_LCDC1_DCLK 178 375279385Simp#define SRST_UART0 179 376279385Simp#define SRST_UART1 180 377279385Simp#define SRST_UART2 181 378279385Simp#define SRST_UART3 182 379279385Simp#define SRST_UART4 183 380279385Simp#define SRST_SIMC 186 381279385Simp#define SRST_PS2C 187 382279385Simp#define SRST_TSP 188 383279385Simp#define SRST_TSP_CLKIN0 189 384279385Simp#define SRST_TSP_CLKIN1 190 385279385Simp#define SRST_TSP_27M 191 386295436Sandrew 387295436Sandrew#endif 388