1/* 2 * Copyright (c) 2014 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H 17#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H 18 19/* core clocks */ 20#define PLL_APLL 1 21#define PLL_DPLL 2 22#define PLL_CPLL 3 23#define PLL_GPLL 4 24#define PLL_NPLL 5 25#define ARMCLK 6 26 27/* sclk gates (special clocks) */ 28#define SCLK_GPU 64 29#define SCLK_SPI0 65 30#define SCLK_SPI1 66 31#define SCLK_SPI2 67 32#define SCLK_SDMMC 68 33#define SCLK_SDIO0 69 34#define SCLK_SDIO1 70 35#define SCLK_EMMC 71 36#define SCLK_TSADC 72 37#define SCLK_SARADC 73 38#define SCLK_PS2C 74 39#define SCLK_NANDC0 75 40#define SCLK_NANDC1 76 41#define SCLK_UART0 77 42#define SCLK_UART1 78 43#define SCLK_UART2 79 44#define SCLK_UART3 80 45#define SCLK_UART4 81 46#define SCLK_I2S0 82 47#define SCLK_SPDIF 83 48#define SCLK_SPDIF8CH 84 49#define SCLK_TIMER0 85 50#define SCLK_TIMER1 86 51#define SCLK_TIMER2 87 52#define SCLK_TIMER3 88 53#define SCLK_TIMER4 89 54#define SCLK_TIMER5 90 55#define SCLK_TIMER6 91 56#define SCLK_HSADC 92 57#define SCLK_OTGPHY0 93 58#define SCLK_OTGPHY1 94 59#define SCLK_OTGPHY2 95 60#define SCLK_OTG_ADP 96 61#define SCLK_HSICPHY480M 97 62#define SCLK_HSICPHY12M 98 63#define SCLK_MACREF 99 64#define SCLK_LCDC_PWM0 100 65#define SCLK_LCDC_PWM1 101 66#define SCLK_MAC_RX 102 67#define SCLK_MAC_TX 103 68#define SCLK_EDP_24M 104 69#define SCLK_EDP 105 70#define SCLK_RGA 106 71#define SCLK_ISP 107 72#define SCLK_ISP_JPE 108 73#define SCLK_HDMI_HDCP 109 74#define SCLK_HDMI_CEC 110 75#define SCLK_HEVC_CABAC 111 76#define SCLK_HEVC_CORE 112 77#define SCLK_I2S0_OUT 113 78#define SCLK_SDMMC_DRV 114 79#define SCLK_SDIO0_DRV 115 80#define SCLK_SDIO1_DRV 116 81#define SCLK_EMMC_DRV 117 82#define SCLK_SDMMC_SAMPLE 118 83#define SCLK_SDIO0_SAMPLE 119 84#define SCLK_SDIO1_SAMPLE 120 85#define SCLK_EMMC_SAMPLE 121 86#define SCLK_USBPHY480M_SRC 122 87#define SCLK_PVTM_CORE 123 88#define SCLK_PVTM_GPU 124 89#define SCLK_CRYPTO 125 90#define SCLK_MIPIDSI_24M 126 91 92#define SCLK_MAC 151 93#define SCLK_MACREF_OUT 152 94 95#define DCLK_VOP0 190 96#define DCLK_VOP1 191 97 98/* aclk gates */ 99#define ACLK_GPU 192 100#define ACLK_DMAC1 193 101#define ACLK_DMAC2 194 102#define ACLK_MMU 195 103#define ACLK_GMAC 196 104#define ACLK_VOP0 197 105#define ACLK_VOP1 198 106#define ACLK_CRYPTO 199 107#define ACLK_RGA 200 108#define ACLK_RGA_NIU 201 109#define ACLK_IEP 202 110#define ACLK_VIO0_NIU 203 111#define ACLK_VIP 204 112#define ACLK_ISP 205 113#define ACLK_VIO1_NIU 206 114#define ACLK_HEVC 207 115#define ACLK_VCODEC 208 116#define ACLK_CPU 209 117#define ACLK_PERI 210 118 119/* pclk gates */ 120#define PCLK_GPIO0 320 121#define PCLK_GPIO1 321 122#define PCLK_GPIO2 322 123#define PCLK_GPIO3 323 124#define PCLK_GPIO4 324 125#define PCLK_GPIO5 325 126#define PCLK_GPIO6 326 127#define PCLK_GPIO7 327 128#define PCLK_GPIO8 328 129#define PCLK_GRF 329 130#define PCLK_SGRF 330 131#define PCLK_PMU 331 132#define PCLK_I2C0 332 133#define PCLK_I2C1 333 134#define PCLK_I2C2 334 135#define PCLK_I2C3 335 136#define PCLK_I2C4 336 137#define PCLK_I2C5 337 138#define PCLK_SPI0 338 139#define PCLK_SPI1 339 140#define PCLK_SPI2 340 141#define PCLK_UART0 341 142#define PCLK_UART1 342 143#define PCLK_UART2 343 144#define PCLK_UART3 344 145#define PCLK_UART4 345 146#define PCLK_TSADC 346 147#define PCLK_SARADC 347 148#define PCLK_SIM 348 149#define PCLK_GMAC 349 150#define PCLK_PWM 350 151#define PCLK_RKPWM 351 152#define PCLK_PS2C 352 153#define PCLK_TIMER 353 154#define PCLK_TZPC 354 155#define PCLK_EDP_CTRL 355 156#define PCLK_MIPI_DSI0 356 157#define PCLK_MIPI_DSI1 357 158#define PCLK_MIPI_CSI 358 159#define PCLK_LVDS_PHY 359 160#define PCLK_HDMI_CTRL 360 161#define PCLK_VIO2_H2P 361 162#define PCLK_CPU 362 163#define PCLK_PERI 363 164#define PCLK_DDRUPCTL0 364 165#define PCLK_PUBL0 365 166#define PCLK_DDRUPCTL1 366 167#define PCLK_PUBL1 367 168#define PCLK_WDT 368 169#define PCLK_EFUSE256 369 170#define PCLK_EFUSE1024 370 171 172/* hclk gates */ 173#define HCLK_GPS 448 174#define HCLK_OTG0 449 175#define HCLK_USBHOST0 450 176#define HCLK_USBHOST1 451 177#define HCLK_HSIC 452 178#define HCLK_NANDC0 453 179#define HCLK_NANDC1 454 180#define HCLK_TSP 455 181#define HCLK_SDMMC 456 182#define HCLK_SDIO0 457 183#define HCLK_SDIO1 458 184#define HCLK_EMMC 459 185#define HCLK_HSADC 460 186#define HCLK_CRYPTO 461 187#define HCLK_I2S0 462 188#define HCLK_SPDIF 463 189#define HCLK_SPDIF8CH 464 190#define HCLK_VOP0 465 191#define HCLK_VOP1 466 192#define HCLK_ROM 467 193#define HCLK_IEP 468 194#define HCLK_ISP 469 195#define HCLK_RGA 470 196#define HCLK_VIO_AHB_ARBI 471 197#define HCLK_VIO_NIU 472 198#define HCLK_VIP 473 199#define HCLK_VIO2_H2P 474 200#define HCLK_HEVC 475 201#define HCLK_VCODEC 476 202#define HCLK_CPU 477 203#define HCLK_PERI 478 204 205#define CLK_NR_CLKS (HCLK_PERI + 1) 206 207/* soft-reset indices */ 208#define SRST_CORE0 0 209#define SRST_CORE1 1 210#define SRST_CORE2 2 211#define SRST_CORE3 3 212#define SRST_CORE0_PO 4 213#define SRST_CORE1_PO 5 214#define SRST_CORE2_PO 6 215#define SRST_CORE3_PO 7 216#define SRST_PDCORE_STRSYS 8 217#define SRST_PDBUS_STRSYS 9 218#define SRST_L2C 10 219#define SRST_TOPDBG 11 220#define SRST_CORE0_DBG 12 221#define SRST_CORE1_DBG 13 222#define SRST_CORE2_DBG 14 223#define SRST_CORE3_DBG 15 224 225#define SRST_PDBUG_AHB_ARBITOR 16 226#define SRST_EFUSE256 17 227#define SRST_DMAC1 18 228#define SRST_INTMEM 19 229#define SRST_ROM 20 230#define SRST_SPDIF8CH 21 231#define SRST_TIMER 22 232#define SRST_I2S0 23 233#define SRST_SPDIF 24 234#define SRST_TIMER0 25 235#define SRST_TIMER1 26 236#define SRST_TIMER2 27 237#define SRST_TIMER3 28 238#define SRST_TIMER4 29 239#define SRST_TIMER5 30 240#define SRST_EFUSE 31 241 242#define SRST_GPIO0 32 243#define SRST_GPIO1 33 244#define SRST_GPIO2 34 245#define SRST_GPIO3 35 246#define SRST_GPIO4 36 247#define SRST_GPIO5 37 248#define SRST_GPIO6 38 249#define SRST_GPIO7 39 250#define SRST_GPIO8 40 251#define SRST_I2C0 42 252#define SRST_I2C1 43 253#define SRST_I2C2 44 254#define SRST_I2C3 45 255#define SRST_I2C4 46 256#define SRST_I2C5 47 257 258#define SRST_DWPWM 48 259#define SRST_MMC_PERI 49 260#define SRST_PERIPH_MMU 50 261#define SRST_DAP 51 262#define SRST_DAP_SYS 52 263#define SRST_TPIU 53 264#define SRST_PMU_APB 54 265#define SRST_GRF 55 266#define SRST_PMU 56 267#define SRST_PERIPH_AXI 57 268#define SRST_PERIPH_AHB 58 269#define SRST_PERIPH_APB 59 270#define SRST_PERIPH_NIU 60 271#define SRST_PDPERI_AHB_ARBI 61 272#define SRST_EMEM 62 273#define SRST_USB_PERI 63 274 275#define SRST_DMAC2 64 276#define SRST_MAC 66 277#define SRST_GPS 67 278#define SRST_RKPWM 69 279#define SRST_CCP 71 280#define SRST_USBHOST0 72 281#define SRST_HSIC 73 282#define SRST_HSIC_AUX 74 283#define SRST_HSIC_PHY 75 284#define SRST_HSADC 76 285#define SRST_NANDC0 77 286#define SRST_NANDC1 78 287 288#define SRST_TZPC 80 289#define SRST_SPI0 83 290#define SRST_SPI1 84 291#define SRST_SPI2 85 292#define SRST_SARADC 87 293#define SRST_PDALIVE_NIU 88 294#define SRST_PDPMU_INTMEM 89 295#define SRST_PDPMU_NIU 90 296#define SRST_SGRF 91 297 298#define SRST_VIO_ARBI 96 299#define SRST_RGA_NIU 97 300#define SRST_VIO0_NIU_AXI 98 301#define SRST_VIO_NIU_AHB 99 302#define SRST_LCDC0_AXI 100 303#define SRST_LCDC0_AHB 101 304#define SRST_LCDC0_DCLK 102 305#define SRST_VIO1_NIU_AXI 103 306#define SRST_VIP 104 307#define SRST_RGA_CORE 105 308#define SRST_IEP_AXI 106 309#define SRST_IEP_AHB 107 310#define SRST_RGA_AXI 108 311#define SRST_RGA_AHB 109 312#define SRST_ISP 110 313#define SRST_EDP 111 314 315#define SRST_VCODEC_AXI 112 316#define SRST_VCODEC_AHB 113 317#define SRST_VIO_H2P 114 318#define SRST_MIPIDSI0 115 319#define SRST_MIPIDSI1 116 320#define SRST_MIPICSI 117 321#define SRST_LVDS_PHY 118 322#define SRST_LVDS_CON 119 323#define SRST_GPU 120 324#define SRST_HDMI 121 325#define SRST_CORE_PVTM 124 326#define SRST_GPU_PVTM 125 327 328#define SRST_MMC0 128 329#define SRST_SDIO0 129 330#define SRST_SDIO1 130 331#define SRST_EMMC 131 332#define SRST_USBOTG_AHB 132 333#define SRST_USBOTG_PHY 133 334#define SRST_USBOTG_CON 134 335#define SRST_USBHOST0_AHB 135 336#define SRST_USBHOST0_PHY 136 337#define SRST_USBHOST0_CON 137 338#define SRST_USBHOST1_AHB 138 339#define SRST_USBHOST1_PHY 139 340#define SRST_USBHOST1_CON 140 341#define SRST_USB_ADP 141 342#define SRST_ACC_EFUSE 142 343 344#define SRST_CORESIGHT 144 345#define SRST_PD_CORE_AHB_NOC 145 346#define SRST_PD_CORE_APB_NOC 146 347#define SRST_PD_CORE_MP_AXI 147 348#define SRST_GIC 148 349#define SRST_LCDC_PWM0 149 350#define SRST_LCDC_PWM1 150 351#define SRST_VIO0_H2P_BRG 151 352#define SRST_VIO1_H2P_BRG 152 353#define SRST_RGA_H2P_BRG 153 354#define SRST_HEVC 154 355#define SRST_TSADC 159 356 357#define SRST_DDRPHY0 160 358#define SRST_DDRPHY0_APB 161 359#define SRST_DDRCTRL0 162 360#define SRST_DDRCTRL0_APB 163 361#define SRST_DDRPHY0_CTRL 164 362#define SRST_DDRPHY1 165 363#define SRST_DDRPHY1_APB 166 364#define SRST_DDRCTRL1 167 365#define SRST_DDRCTRL1_APB 168 366#define SRST_DDRPHY1_CTRL 169 367#define SRST_DDRMSCH0 170 368#define SRST_DDRMSCH1 171 369#define SRST_CRYPTO 174 370#define SRST_C2C_HOST 175 371 372#define SRST_LCDC1_AXI 176 373#define SRST_LCDC1_AHB 177 374#define SRST_LCDC1_DCLK 178 375#define SRST_UART0 179 376#define SRST_UART1 180 377#define SRST_UART2 181 378#define SRST_UART3 182 379#define SRST_UART4 183 380#define SRST_SIMC 186 381#define SRST_PS2C 187 382#define SRST_TSP 188 383#define SRST_TSP_CLKIN0 189 384#define SRST_TSP_CLKIN1 190 385#define SRST_TSP_27M 191 386 387#endif 388