1/* 2 * Device Tree Source for OMAP3 SoC 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/omap.h> 14 15#include "skeleton.dtsi" 16 17/ { 18 compatible = "ti,omap3430", "ti,omap3"; 19 interrupt-parent = <&intc>; 20 21 aliases { 22 i2c0 = &i2c1; 23 i2c1 = &i2c2; 24 i2c2 = &i2c3; 25 serial0 = &uart1; 26 serial1 = &uart2; 27 serial2 = &uart3; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu@0 { 35 compatible = "arm,cortex-a8"; 36 device_type = "cpu"; 37 reg = <0x0>; 38 39 clocks = <&dpll1_ck>; 40 clock-names = "cpu"; 41 42 clock-latency = <300000>; /* From omap-cpufreq driver */ 43 }; 44 }; 45 46 pmu { 47 compatible = "arm,cortex-a8-pmu"; 48 reg = <0x54000000 0x800000>; 49 interrupts = <3>; 50 ti,hwmods = "debugss"; 51 }; 52 53 /* 54 * The soc node represents the soc top level view. It is used for IPs 55 * that are not memory mapped in the MPU view or for the MPU itself. 56 */ 57 soc { 58 compatible = "ti,omap-infra"; 59 mpu { 60 compatible = "ti,omap3-mpu"; 61 ti,hwmods = "mpu"; 62 }; 63 64 iva: iva { 65 compatible = "ti,iva2.2"; 66 ti,hwmods = "iva"; 67 68 dsp { 69 compatible = "ti,omap3-c64"; 70 }; 71 }; 72 }; 73 74 /* 75 * XXX: Use a flat representation of the OMAP3 interconnect. 76 * The real OMAP interconnect network is quite complex. 77 * Since it will not bring real advantage to represent that in DT for 78 * the moment, just use a fake OCP bus entry to represent the whole bus 79 * hierarchy. 80 */ 81 ocp { 82 compatible = "ti,omap3-l3-smx", "simple-bus"; 83 reg = <0x68000000 0x10000>; 84 interrupts = <9 10>; 85 #address-cells = <1>; 86 #size-cells = <1>; 87 ranges; 88 ti,hwmods = "l3_main"; 89 90 l4_core: l4@48000000 { 91 compatible = "ti,omap3-l4-core", "simple-bus"; 92 #address-cells = <1>; 93 #size-cells = <1>; 94 ranges = <0 0x48000000 0x1000000>; 95 96 scm: scm@2000 { 97 compatible = "ti,omap3-scm", "simple-bus"; 98 reg = <0x2000 0x2000>; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 ranges = <0 0x2000 0x2000>; 102 103 omap3_pmx_core: pinmux@30 { 104 compatible = "ti,omap3-padconf", 105 "pinctrl-single"; 106 reg = <0x30 0x238>; 107 #address-cells = <1>; 108 #size-cells = <0>; 109 #interrupt-cells = <1>; 110 interrupt-controller; 111 pinctrl-single,register-width = <16>; 112 pinctrl-single,function-mask = <0xff1f>; 113 }; 114 115 scm_conf: scm_conf@270 { 116 compatible = "syscon", "simple-bus"; 117 reg = <0x270 0x330>; 118 #address-cells = <1>; 119 #size-cells = <1>; 120 ranges = <0 0x270 0x330>; 121 122 pbias_regulator: pbias_regulator { 123 compatible = "ti,pbias-omap3", "ti,pbias-omap"; 124 reg = <0x2b0 0x4>; 125 syscon = <&scm_conf>; 126 pbias_mmc_reg: pbias_mmc_omap2430 { 127 regulator-name = "pbias_mmc_omap2430"; 128 regulator-min-microvolt = <1800000>; 129 regulator-max-microvolt = <3000000>; 130 }; 131 }; 132 133 scm_clocks: clocks { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 }; 138 139 scm_clockdomains: clockdomains { 140 }; 141 142 omap3_pmx_wkup: pinmux@a00 { 143 compatible = "ti,omap3-padconf", 144 "pinctrl-single"; 145 reg = <0xa00 0x5c>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 #interrupt-cells = <1>; 149 interrupt-controller; 150 pinctrl-single,register-width = <16>; 151 pinctrl-single,function-mask = <0xff1f>; 152 }; 153 }; 154 }; 155 156 aes: aes@480c5000 { 157 compatible = "ti,omap3-aes"; 158 ti,hwmods = "aes"; 159 reg = <0x480c5000 0x50>; 160 interrupts = <0>; 161 dmas = <&sdma 65 &sdma 66>; 162 dma-names = "tx", "rx"; 163 }; 164 165 prm: prm@48306000 { 166 compatible = "ti,omap3-prm"; 167 reg = <0x48306000 0x4000>; 168 interrupts = <11>; 169 170 prm_clocks: clocks { 171 #address-cells = <1>; 172 #size-cells = <0>; 173 }; 174 175 prm_clockdomains: clockdomains { 176 }; 177 }; 178 179 cm: cm@48004000 { 180 compatible = "ti,omap3-cm"; 181 reg = <0x48004000 0x4000>; 182 183 cm_clocks: clocks { 184 #address-cells = <1>; 185 #size-cells = <0>; 186 }; 187 188 cm_clockdomains: clockdomains { 189 }; 190 }; 191 192 counter32k: counter@48320000 { 193 compatible = "ti,omap-counter32k"; 194 reg = <0x48320000 0x20>; 195 ti,hwmods = "counter_32k"; 196 }; 197 198 intc: interrupt-controller@48200000 { 199 compatible = "ti,omap3-intc"; 200 interrupt-controller; 201 #interrupt-cells = <1>; 202 reg = <0x48200000 0x1000>; 203 }; 204 205 sdma: dma-controller@48056000 { 206 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; 207 reg = <0x48056000 0x1000>; 208 interrupts = <12>, 209 <13>, 210 <14>, 211 <15>; 212 #dma-cells = <1>; 213 dma-channels = <32>; 214 dma-requests = <96>; 215 }; 216 217 gpio1: gpio@48310000 { 218 compatible = "ti,omap3-gpio"; 219 reg = <0x48310000 0x200>; 220 interrupts = <29>; 221 ti,hwmods = "gpio1"; 222 ti,gpio-always-on; 223 gpio-controller; 224 #gpio-cells = <2>; 225 interrupt-controller; 226 #interrupt-cells = <2>; 227 }; 228 229 gpio2: gpio@49050000 { 230 compatible = "ti,omap3-gpio"; 231 reg = <0x49050000 0x200>; 232 interrupts = <30>; 233 ti,hwmods = "gpio2"; 234 gpio-controller; 235 #gpio-cells = <2>; 236 interrupt-controller; 237 #interrupt-cells = <2>; 238 }; 239 240 gpio3: gpio@49052000 { 241 compatible = "ti,omap3-gpio"; 242 reg = <0x49052000 0x200>; 243 interrupts = <31>; 244 ti,hwmods = "gpio3"; 245 gpio-controller; 246 #gpio-cells = <2>; 247 interrupt-controller; 248 #interrupt-cells = <2>; 249 }; 250 251 gpio4: gpio@49054000 { 252 compatible = "ti,omap3-gpio"; 253 reg = <0x49054000 0x200>; 254 interrupts = <32>; 255 ti,hwmods = "gpio4"; 256 gpio-controller; 257 #gpio-cells = <2>; 258 interrupt-controller; 259 #interrupt-cells = <2>; 260 }; 261 262 gpio5: gpio@49056000 { 263 compatible = "ti,omap3-gpio"; 264 reg = <0x49056000 0x200>; 265 interrupts = <33>; 266 ti,hwmods = "gpio5"; 267 gpio-controller; 268 #gpio-cells = <2>; 269 interrupt-controller; 270 #interrupt-cells = <2>; 271 }; 272 273 gpio6: gpio@49058000 { 274 compatible = "ti,omap3-gpio"; 275 reg = <0x49058000 0x200>; 276 interrupts = <34>; 277 ti,hwmods = "gpio6"; 278 gpio-controller; 279 #gpio-cells = <2>; 280 interrupt-controller; 281 #interrupt-cells = <2>; 282 }; 283 284 uart1: serial@4806a000 { 285 compatible = "ti,omap3-uart"; 286 reg = <0x4806a000 0x2000>; 287 interrupts-extended = <&intc 72>; 288 dmas = <&sdma 49 &sdma 50>; 289 dma-names = "tx", "rx"; 290 ti,hwmods = "uart1"; 291 clock-frequency = <48000000>; 292 }; 293 294 uart2: serial@4806c000 { 295 compatible = "ti,omap3-uart"; 296 reg = <0x4806c000 0x400>; 297 interrupts-extended = <&intc 73>; 298 dmas = <&sdma 51 &sdma 52>; 299 dma-names = "tx", "rx"; 300 ti,hwmods = "uart2"; 301 clock-frequency = <48000000>; 302 }; 303 304 uart3: serial@49020000 { 305 compatible = "ti,omap3-uart"; 306 reg = <0x49020000 0x400>; 307 interrupts-extended = <&intc 74>; 308 dmas = <&sdma 53 &sdma 54>; 309 dma-names = "tx", "rx"; 310 ti,hwmods = "uart3"; 311 clock-frequency = <48000000>; 312 }; 313 314 i2c1: i2c@48070000 { 315 compatible = "ti,omap3-i2c"; 316 reg = <0x48070000 0x80>; 317 interrupts = <56>; 318 dmas = <&sdma 27 &sdma 28>; 319 dma-names = "tx", "rx"; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 ti,hwmods = "i2c1"; 323 }; 324 325 i2c2: i2c@48072000 { 326 compatible = "ti,omap3-i2c"; 327 reg = <0x48072000 0x80>; 328 interrupts = <57>; 329 dmas = <&sdma 29 &sdma 30>; 330 dma-names = "tx", "rx"; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 ti,hwmods = "i2c2"; 334 }; 335 336 i2c3: i2c@48060000 { 337 compatible = "ti,omap3-i2c"; 338 reg = <0x48060000 0x80>; 339 interrupts = <61>; 340 dmas = <&sdma 25 &sdma 26>; 341 dma-names = "tx", "rx"; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 ti,hwmods = "i2c3"; 345 }; 346 347 mailbox: mailbox@48094000 { 348 compatible = "ti,omap3-mailbox"; 349 ti,hwmods = "mailbox"; 350 reg = <0x48094000 0x200>; 351 interrupts = <26>; 352 #mbox-cells = <1>; 353 ti,mbox-num-users = <2>; 354 ti,mbox-num-fifos = <2>; 355 mbox_dsp: dsp { 356 ti,mbox-tx = <0 0 0>; 357 ti,mbox-rx = <1 0 0>; 358 }; 359 }; 360 361 mcspi1: spi@48098000 { 362 compatible = "ti,omap2-mcspi"; 363 reg = <0x48098000 0x100>; 364 interrupts = <65>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 ti,hwmods = "mcspi1"; 368 ti,spi-num-cs = <4>; 369 dmas = <&sdma 35>, 370 <&sdma 36>, 371 <&sdma 37>, 372 <&sdma 38>, 373 <&sdma 39>, 374 <&sdma 40>, 375 <&sdma 41>, 376 <&sdma 42>; 377 dma-names = "tx0", "rx0", "tx1", "rx1", 378 "tx2", "rx2", "tx3", "rx3"; 379 }; 380 381 mcspi2: spi@4809a000 { 382 compatible = "ti,omap2-mcspi"; 383 reg = <0x4809a000 0x100>; 384 interrupts = <66>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 ti,hwmods = "mcspi2"; 388 ti,spi-num-cs = <2>; 389 dmas = <&sdma 43>, 390 <&sdma 44>, 391 <&sdma 45>, 392 <&sdma 46>; 393 dma-names = "tx0", "rx0", "tx1", "rx1"; 394 }; 395 396 mcspi3: spi@480b8000 { 397 compatible = "ti,omap2-mcspi"; 398 reg = <0x480b8000 0x100>; 399 interrupts = <91>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 ti,hwmods = "mcspi3"; 403 ti,spi-num-cs = <2>; 404 dmas = <&sdma 15>, 405 <&sdma 16>, 406 <&sdma 23>, 407 <&sdma 24>; 408 dma-names = "tx0", "rx0", "tx1", "rx1"; 409 }; 410 411 mcspi4: spi@480ba000 { 412 compatible = "ti,omap2-mcspi"; 413 reg = <0x480ba000 0x100>; 414 interrupts = <48>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 ti,hwmods = "mcspi4"; 418 ti,spi-num-cs = <1>; 419 dmas = <&sdma 70>, <&sdma 71>; 420 dma-names = "tx0", "rx0"; 421 }; 422 423 hdqw1w: 1w@480b2000 { 424 compatible = "ti,omap3-1w"; 425 reg = <0x480b2000 0x1000>; 426 interrupts = <58>; 427 ti,hwmods = "hdq1w"; 428 }; 429 430 mmc1: mmc@4809c000 { 431 compatible = "ti,omap3-hsmmc"; 432 reg = <0x4809c000 0x200>; 433 interrupts = <83>; 434 ti,hwmods = "mmc1"; 435 ti,dual-volt; 436 dmas = <&sdma 61>, <&sdma 62>; 437 dma-names = "tx", "rx"; 438 pbias-supply = <&pbias_mmc_reg>; 439 }; 440 441 mmc2: mmc@480b4000 { 442 compatible = "ti,omap3-hsmmc"; 443 reg = <0x480b4000 0x200>; 444 interrupts = <86>; 445 ti,hwmods = "mmc2"; 446 dmas = <&sdma 47>, <&sdma 48>; 447 dma-names = "tx", "rx"; 448 }; 449 450 mmc3: mmc@480ad000 { 451 compatible = "ti,omap3-hsmmc"; 452 reg = <0x480ad000 0x200>; 453 interrupts = <94>; 454 ti,hwmods = "mmc3"; 455 dmas = <&sdma 77>, <&sdma 78>; 456 dma-names = "tx", "rx"; 457 }; 458 459 mmu_isp: mmu@480bd400 { 460 #iommu-cells = <0>; 461 compatible = "ti,omap2-iommu"; 462 reg = <0x480bd400 0x80>; 463 interrupts = <24>; 464 ti,hwmods = "mmu_isp"; 465 ti,#tlb-entries = <8>; 466 }; 467 468 mmu_iva: mmu@5d000000 { 469 #iommu-cells = <0>; 470 compatible = "ti,omap2-iommu"; 471 reg = <0x5d000000 0x80>; 472 interrupts = <28>; 473 ti,hwmods = "mmu_iva"; 474 status = "disabled"; 475 }; 476 477 wdt2: wdt@48314000 { 478 compatible = "ti,omap3-wdt"; 479 reg = <0x48314000 0x80>; 480 ti,hwmods = "wd_timer2"; 481 }; 482 483 mcbsp1: mcbsp@48074000 { 484 compatible = "ti,omap3-mcbsp"; 485 reg = <0x48074000 0xff>; 486 reg-names = "mpu"; 487 interrupts = <16>, /* OCP compliant interrupt */ 488 <59>, /* TX interrupt */ 489 <60>; /* RX interrupt */ 490 interrupt-names = "common", "tx", "rx"; 491 ti,buffer-size = <128>; 492 ti,hwmods = "mcbsp1"; 493 dmas = <&sdma 31>, 494 <&sdma 32>; 495 dma-names = "tx", "rx"; 496 status = "disabled"; 497 }; 498 499 mcbsp2: mcbsp@49022000 { 500 compatible = "ti,omap3-mcbsp"; 501 reg = <0x49022000 0xff>, 502 <0x49028000 0xff>; 503 reg-names = "mpu", "sidetone"; 504 interrupts = <17>, /* OCP compliant interrupt */ 505 <62>, /* TX interrupt */ 506 <63>, /* RX interrupt */ 507 <4>; /* Sidetone */ 508 interrupt-names = "common", "tx", "rx", "sidetone"; 509 ti,buffer-size = <1280>; 510 ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; 511 dmas = <&sdma 33>, 512 <&sdma 34>; 513 dma-names = "tx", "rx"; 514 status = "disabled"; 515 }; 516 517 mcbsp3: mcbsp@49024000 { 518 compatible = "ti,omap3-mcbsp"; 519 reg = <0x49024000 0xff>, 520 <0x4902a000 0xff>; 521 reg-names = "mpu", "sidetone"; 522 interrupts = <22>, /* OCP compliant interrupt */ 523 <89>, /* TX interrupt */ 524 <90>, /* RX interrupt */ 525 <5>; /* Sidetone */ 526 interrupt-names = "common", "tx", "rx", "sidetone"; 527 ti,buffer-size = <128>; 528 ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; 529 dmas = <&sdma 17>, 530 <&sdma 18>; 531 dma-names = "tx", "rx"; 532 status = "disabled"; 533 }; 534 535 mcbsp4: mcbsp@49026000 { 536 compatible = "ti,omap3-mcbsp"; 537 reg = <0x49026000 0xff>; 538 reg-names = "mpu"; 539 interrupts = <23>, /* OCP compliant interrupt */ 540 <54>, /* TX interrupt */ 541 <55>; /* RX interrupt */ 542 interrupt-names = "common", "tx", "rx"; 543 ti,buffer-size = <128>; 544 ti,hwmods = "mcbsp4"; 545 dmas = <&sdma 19>, 546 <&sdma 20>; 547 dma-names = "tx", "rx"; 548 status = "disabled"; 549 }; 550 551 mcbsp5: mcbsp@48096000 { 552 compatible = "ti,omap3-mcbsp"; 553 reg = <0x48096000 0xff>; 554 reg-names = "mpu"; 555 interrupts = <27>, /* OCP compliant interrupt */ 556 <81>, /* TX interrupt */ 557 <82>; /* RX interrupt */ 558 interrupt-names = "common", "tx", "rx"; 559 ti,buffer-size = <128>; 560 ti,hwmods = "mcbsp5"; 561 dmas = <&sdma 21>, 562 <&sdma 22>; 563 dma-names = "tx", "rx"; 564 status = "disabled"; 565 }; 566 567 sham: sham@480c3000 { 568 compatible = "ti,omap3-sham"; 569 ti,hwmods = "sham"; 570 reg = <0x480c3000 0x64>; 571 interrupts = <49>; 572 dmas = <&sdma 69>; 573 dma-names = "rx"; 574 }; 575 576 smartreflex_core: smartreflex@480cb000 { 577 compatible = "ti,omap3-smartreflex-core"; 578 ti,hwmods = "smartreflex_core"; 579 reg = <0x480cb000 0x400>; 580 interrupts = <19>; 581 }; 582 583 smartreflex_mpu_iva: smartreflex@480c9000 { 584 compatible = "ti,omap3-smartreflex-iva"; 585 ti,hwmods = "smartreflex_mpu_iva"; 586 reg = <0x480c9000 0x400>; 587 interrupts = <18>; 588 }; 589 590 timer1: timer@48318000 { 591 compatible = "ti,omap3430-timer"; 592 reg = <0x48318000 0x400>; 593 interrupts = <37>; 594 ti,hwmods = "timer1"; 595 ti,timer-alwon; 596 }; 597 598 timer2: timer@49032000 { 599 compatible = "ti,omap3430-timer"; 600 reg = <0x49032000 0x400>; 601 interrupts = <38>; 602 ti,hwmods = "timer2"; 603 }; 604 605 timer3: timer@49034000 { 606 compatible = "ti,omap3430-timer"; 607 reg = <0x49034000 0x400>; 608 interrupts = <39>; 609 ti,hwmods = "timer3"; 610 }; 611 612 timer4: timer@49036000 { 613 compatible = "ti,omap3430-timer"; 614 reg = <0x49036000 0x400>; 615 interrupts = <40>; 616 ti,hwmods = "timer4"; 617 }; 618 619 timer5: timer@49038000 { 620 compatible = "ti,omap3430-timer"; 621 reg = <0x49038000 0x400>; 622 interrupts = <41>; 623 ti,hwmods = "timer5"; 624 ti,timer-dsp; 625 }; 626 627 timer6: timer@4903a000 { 628 compatible = "ti,omap3430-timer"; 629 reg = <0x4903a000 0x400>; 630 interrupts = <42>; 631 ti,hwmods = "timer6"; 632 ti,timer-dsp; 633 }; 634 635 timer7: timer@4903c000 { 636 compatible = "ti,omap3430-timer"; 637 reg = <0x4903c000 0x400>; 638 interrupts = <43>; 639 ti,hwmods = "timer7"; 640 ti,timer-dsp; 641 }; 642 643 timer8: timer@4903e000 { 644 compatible = "ti,omap3430-timer"; 645 reg = <0x4903e000 0x400>; 646 interrupts = <44>; 647 ti,hwmods = "timer8"; 648 ti,timer-pwm; 649 ti,timer-dsp; 650 }; 651 652 timer9: timer@49040000 { 653 compatible = "ti,omap3430-timer"; 654 reg = <0x49040000 0x400>; 655 interrupts = <45>; 656 ti,hwmods = "timer9"; 657 ti,timer-pwm; 658 }; 659 660 timer10: timer@48086000 { 661 compatible = "ti,omap3430-timer"; 662 reg = <0x48086000 0x400>; 663 interrupts = <46>; 664 ti,hwmods = "timer10"; 665 ti,timer-pwm; 666 }; 667 668 timer11: timer@48088000 { 669 compatible = "ti,omap3430-timer"; 670 reg = <0x48088000 0x400>; 671 interrupts = <47>; 672 ti,hwmods = "timer11"; 673 ti,timer-pwm; 674 }; 675 676 timer12: timer@48304000 { 677 compatible = "ti,omap3430-timer"; 678 reg = <0x48304000 0x400>; 679 interrupts = <95>; 680 ti,hwmods = "timer12"; 681 ti,timer-alwon; 682 ti,timer-secure; 683 }; 684 685 usbhstll: usbhstll@48062000 { 686 compatible = "ti,usbhs-tll"; 687 reg = <0x48062000 0x1000>; 688 interrupts = <78>; 689 ti,hwmods = "usb_tll_hs"; 690 }; 691 692 usbhshost: usbhshost@48064000 { 693 compatible = "ti,usbhs-host"; 694 reg = <0x48064000 0x400>; 695 ti,hwmods = "usb_host_hs"; 696 #address-cells = <1>; 697 #size-cells = <1>; 698 ranges; 699 700 usbhsohci: ohci@48064400 { 701 compatible = "ti,ohci-omap3"; 702 reg = <0x48064400 0x400>; 703 interrupt-parent = <&intc>; 704 interrupts = <76>; 705 }; 706 707 usbhsehci: ehci@48064800 { 708 compatible = "ti,ehci-omap"; 709 reg = <0x48064800 0x400>; 710 interrupt-parent = <&intc>; 711 interrupts = <77>; 712 }; 713 }; 714 715 gpmc: gpmc@6e000000 { 716 compatible = "ti,omap3430-gpmc"; 717 ti,hwmods = "gpmc"; 718 reg = <0x6e000000 0x02d0>; 719 interrupts = <20>; 720 dmas = <&sdma 4>; 721 dma-names = "rxtx"; 722 gpmc,num-cs = <8>; 723 gpmc,num-waitpins = <4>; 724 #address-cells = <2>; 725 #size-cells = <1>; 726 }; 727 728 usb_otg_hs: usb_otg_hs@480ab000 { 729 compatible = "ti,omap3-musb"; 730 reg = <0x480ab000 0x1000>; 731 interrupts = <92>, <93>; 732 interrupt-names = "mc", "dma"; 733 ti,hwmods = "usb_otg_hs"; 734 multipoint = <1>; 735 num-eps = <16>; 736 ram-bits = <12>; 737 }; 738 739 dss: dss@48050000 { 740 compatible = "ti,omap3-dss"; 741 reg = <0x48050000 0x200>; 742 status = "disabled"; 743 ti,hwmods = "dss_core"; 744 clocks = <&dss1_alwon_fck>; 745 clock-names = "fck"; 746 #address-cells = <1>; 747 #size-cells = <1>; 748 ranges; 749 750 dispc@48050400 { 751 compatible = "ti,omap3-dispc"; 752 reg = <0x48050400 0x400>; 753 interrupts = <25>; 754 ti,hwmods = "dss_dispc"; 755 clocks = <&dss1_alwon_fck>; 756 clock-names = "fck"; 757 }; 758 759 dsi: encoder@4804fc00 { 760 compatible = "ti,omap3-dsi"; 761 reg = <0x4804fc00 0x200>, 762 <0x4804fe00 0x40>, 763 <0x4804ff00 0x20>; 764 reg-names = "proto", "phy", "pll"; 765 interrupts = <25>; 766 status = "disabled"; 767 ti,hwmods = "dss_dsi1"; 768 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; 769 clock-names = "fck", "sys_clk"; 770 }; 771 772 rfbi: encoder@48050800 { 773 compatible = "ti,omap3-rfbi"; 774 reg = <0x48050800 0x100>; 775 status = "disabled"; 776 ti,hwmods = "dss_rfbi"; 777 clocks = <&dss1_alwon_fck>, <&dss_ick>; 778 clock-names = "fck", "ick"; 779 }; 780 781 venc: encoder@48050c00 { 782 compatible = "ti,omap3-venc"; 783 reg = <0x48050c00 0x100>; 784 status = "disabled"; 785 ti,hwmods = "dss_venc"; 786 clocks = <&dss_tv_fck>; 787 clock-names = "fck"; 788 }; 789 }; 790 791 ssi: ssi-controller@48058000 { 792 compatible = "ti,omap3-ssi"; 793 ti,hwmods = "ssi"; 794 795 status = "disabled"; 796 797 reg = <0x48058000 0x1000>, 798 <0x48059000 0x1000>; 799 reg-names = "sys", 800 "gdd"; 801 802 interrupts = <71>; 803 interrupt-names = "gdd_mpu"; 804 805 #address-cells = <1>; 806 #size-cells = <1>; 807 ranges; 808 809 ssi_port1: ssi-port@4805a000 { 810 compatible = "ti,omap3-ssi-port"; 811 812 reg = <0x4805a000 0x800>, 813 <0x4805a800 0x800>; 814 reg-names = "tx", 815 "rx"; 816 817 interrupt-parent = <&intc>; 818 interrupts = <67>, 819 <68>; 820 }; 821 822 ssi_port2: ssi-port@4805b000 { 823 compatible = "ti,omap3-ssi-port"; 824 825 reg = <0x4805b000 0x800>, 826 <0x4805b800 0x800>; 827 reg-names = "tx", 828 "rx"; 829 830 interrupt-parent = <&intc>; 831 interrupts = <69>, 832 <70>; 833 }; 834 }; 835 }; 836}; 837 838/include/ "omap3xxx-clocks.dtsi" 839