1/* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include "skeleton64.dtsi" 49#include <dt-bindings/interrupt-controller/arm-gic.h> 50 51/ { 52 compatible = "fsl,ls1021a"; 53 interrupt-parent = <&gic>; 54 55 aliases { 56 crypto = &crypto; 57 ethernet0 = &enet0; 58 ethernet1 = &enet1; 59 ethernet2 = &enet2; 60 serial0 = &lpuart0; 61 serial1 = &lpuart1; 62 serial2 = &lpuart2; 63 serial3 = &lpuart3; 64 serial4 = &lpuart4; 65 serial5 = &lpuart5; 66 sysclk = &sysclk; 67 }; 68 69 cpus { 70 #address-cells = <1>; 71 #size-cells = <0>; 72 73 cpu@f00 { 74 compatible = "arm,cortex-a7"; 75 device_type = "cpu"; 76 reg = <0xf00>; 77 clocks = <&cluster1_clk>; 78 }; 79 80 cpu@f01 { 81 compatible = "arm,cortex-a7"; 82 device_type = "cpu"; 83 reg = <0xf01>; 84 clocks = <&cluster1_clk>; 85 }; 86 }; 87 88 timer { 89 compatible = "arm,armv7-timer"; 90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 91 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 92 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 93 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 94 }; 95 96 pmu { 97 compatible = "arm,cortex-a7-pmu"; 98 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 100 }; 101 102 soc { 103 compatible = "simple-bus"; 104 #address-cells = <2>; 105 #size-cells = <2>; 106 device_type = "soc"; 107 interrupt-parent = <&gic>; 108 ranges; 109 110 gic: interrupt-controller@1400000 { 111 compatible = "arm,cortex-a7-gic"; 112 #interrupt-cells = <3>; 113 interrupt-controller; 114 reg = <0x0 0x1401000 0x0 0x1000>, 115 <0x0 0x1402000 0x0 0x1000>, 116 <0x0 0x1404000 0x0 0x2000>, 117 <0x0 0x1406000 0x0 0x2000>; 118 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 119 120 }; 121 122 ifc: ifc@1530000 { 123 compatible = "fsl,ifc", "simple-bus"; 124 reg = <0x0 0x1530000 0x0 0x10000>; 125 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 126 }; 127 128 dcfg: dcfg@1ee0000 { 129 compatible = "fsl,ls1021a-dcfg", "syscon"; 130 reg = <0x0 0x1ee0000 0x0 0x10000>; 131 big-endian; 132 }; 133 134 esdhc: esdhc@1560000 { 135 compatible = "fsl,esdhc"; 136 reg = <0x0 0x1560000 0x0 0x10000>; 137 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 138 clock-frequency = <0>; 139 voltage-ranges = <1800 1800 3300 3300>; 140 sdhci,auto-cmd12; 141 big-endian; 142 bus-width = <4>; 143 status = "disabled"; 144 }; 145 146 sata: sata@3200000 { 147 compatible = "fsl,ls1021a-ahci"; 148 reg = <0x0 0x3200000 0x0 0x10000>, 149 <0x0 0x20220520 0x0 0x4>; 150 reg-names = "ahci", "sata-ecc"; 151 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 152 clocks = <&platform_clk 1>; 153 dma-coherent; 154 status = "disabled"; 155 }; 156 157 scfg: scfg@1570000 { 158 compatible = "fsl,ls1021a-scfg", "syscon"; 159 reg = <0x0 0x1570000 0x0 0x10000>; 160 big-endian; 161 }; 162 163 crypto: crypto@1700000 { 164 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 165 fsl,sec-era = <7>; 166 #address-cells = <1>; 167 #size-cells = <1>; 168 reg = <0x0 0x1700000 0x0 0x100000>; 169 ranges = <0x0 0x0 0x1700000 0x100000>; 170 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 171 172 sec_jr0: jr@10000 { 173 compatible = "fsl,sec-v5.0-job-ring", 174 "fsl,sec-v4.0-job-ring"; 175 reg = <0x10000 0x10000>; 176 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 177 }; 178 179 sec_jr1: jr@20000 { 180 compatible = "fsl,sec-v5.0-job-ring", 181 "fsl,sec-v4.0-job-ring"; 182 reg = <0x20000 0x10000>; 183 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 184 }; 185 186 sec_jr2: jr@30000 { 187 compatible = "fsl,sec-v5.0-job-ring", 188 "fsl,sec-v4.0-job-ring"; 189 reg = <0x30000 0x10000>; 190 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 191 }; 192 193 sec_jr3: jr@40000 { 194 compatible = "fsl,sec-v5.0-job-ring", 195 "fsl,sec-v4.0-job-ring"; 196 reg = <0x40000 0x10000>; 197 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 198 }; 199 200 }; 201 202 clockgen: clocking@1ee1000 { 203 #address-cells = <1>; 204 #size-cells = <1>; 205 ranges = <0x0 0x0 0x1ee1000 0x10000>; 206 207 sysclk: sysclk { 208 compatible = "fixed-clock"; 209 #clock-cells = <0>; 210 clock-output-names = "sysclk"; 211 }; 212 213 cga_pll1: pll@800 { 214 compatible = "fsl,qoriq-core-pll-2.0"; 215 #clock-cells = <1>; 216 reg = <0x800 0x10>; 217 clocks = <&sysclk>; 218 clock-output-names = "cga-pll1", "cga-pll1-div2", 219 "cga-pll1-div4"; 220 }; 221 222 platform_clk: pll@c00 { 223 compatible = "fsl,qoriq-core-pll-2.0"; 224 #clock-cells = <1>; 225 reg = <0xc00 0x10>; 226 clocks = <&sysclk>; 227 clock-output-names = "platform-clk", "platform-clk-div2"; 228 }; 229 230 cluster1_clk: clk0c0@0 { 231 compatible = "fsl,qoriq-core-mux-2.0"; 232 #clock-cells = <0>; 233 reg = <0x0 0x10>; 234 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4"; 235 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>; 236 clock-output-names = "cluster1-clk"; 237 }; 238 }; 239 240 dspi0: dspi@2100000 { 241 compatible = "fsl,ls1021a-v1.0-dspi"; 242 #address-cells = <1>; 243 #size-cells = <0>; 244 reg = <0x0 0x2100000 0x0 0x10000>; 245 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 246 clock-names = "dspi"; 247 clocks = <&platform_clk 1>; 248 spi-num-chipselects = <5>; 249 big-endian; 250 status = "disabled"; 251 }; 252 253 dspi1: dspi@2110000 { 254 compatible = "fsl,ls1021a-v1.0-dspi"; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 reg = <0x0 0x2110000 0x0 0x10000>; 258 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 259 clock-names = "dspi"; 260 clocks = <&platform_clk 1>; 261 spi-num-chipselects = <5>; 262 big-endian; 263 status = "disabled"; 264 }; 265 266 i2c0: i2c@2180000 { 267 compatible = "fsl,vf610-i2c"; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 reg = <0x0 0x2180000 0x0 0x10000>; 271 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 272 clock-names = "i2c"; 273 clocks = <&platform_clk 1>; 274 status = "disabled"; 275 }; 276 277 i2c1: i2c@2190000 { 278 compatible = "fsl,vf610-i2c"; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 reg = <0x0 0x2190000 0x0 0x10000>; 282 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 283 clock-names = "i2c"; 284 clocks = <&platform_clk 1>; 285 status = "disabled"; 286 }; 287 288 i2c2: i2c@21a0000 { 289 compatible = "fsl,vf610-i2c"; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 reg = <0x0 0x21a0000 0x0 0x10000>; 293 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 294 clock-names = "i2c"; 295 clocks = <&platform_clk 1>; 296 status = "disabled"; 297 }; 298 299 uart0: serial@21c0500 { 300 compatible = "fsl,16550-FIFO64", "ns16550a"; 301 reg = <0x0 0x21c0500 0x0 0x100>; 302 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 303 clock-frequency = <0>; 304 fifo-size = <15>; 305 status = "disabled"; 306 }; 307 308 uart1: serial@21c0600 { 309 compatible = "fsl,16550-FIFO64", "ns16550a"; 310 reg = <0x0 0x21c0600 0x0 0x100>; 311 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 312 clock-frequency = <0>; 313 fifo-size = <15>; 314 status = "disabled"; 315 }; 316 317 uart2: serial@21d0500 { 318 compatible = "fsl,16550-FIFO64", "ns16550a"; 319 reg = <0x0 0x21d0500 0x0 0x100>; 320 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 321 clock-frequency = <0>; 322 fifo-size = <15>; 323 status = "disabled"; 324 }; 325 326 uart3: serial@21d0600 { 327 compatible = "fsl,16550-FIFO64", "ns16550a"; 328 reg = <0x0 0x21d0600 0x0 0x100>; 329 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 330 clock-frequency = <0>; 331 fifo-size = <15>; 332 status = "disabled"; 333 }; 334 335 lpuart0: serial@2950000 { 336 compatible = "fsl,ls1021a-lpuart"; 337 reg = <0x0 0x2950000 0x0 0x1000>; 338 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&sysclk>; 340 clock-names = "ipg"; 341 status = "disabled"; 342 }; 343 344 lpuart1: serial@2960000 { 345 compatible = "fsl,ls1021a-lpuart"; 346 reg = <0x0 0x2960000 0x0 0x1000>; 347 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&platform_clk 1>; 349 clock-names = "ipg"; 350 status = "disabled"; 351 }; 352 353 lpuart2: serial@2970000 { 354 compatible = "fsl,ls1021a-lpuart"; 355 reg = <0x0 0x2970000 0x0 0x1000>; 356 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&platform_clk 1>; 358 clock-names = "ipg"; 359 status = "disabled"; 360 }; 361 362 lpuart3: serial@2980000 { 363 compatible = "fsl,ls1021a-lpuart"; 364 reg = <0x0 0x2980000 0x0 0x1000>; 365 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&platform_clk 1>; 367 clock-names = "ipg"; 368 status = "disabled"; 369 }; 370 371 lpuart4: serial@2990000 { 372 compatible = "fsl,ls1021a-lpuart"; 373 reg = <0x0 0x2990000 0x0 0x1000>; 374 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&platform_clk 1>; 376 clock-names = "ipg"; 377 status = "disabled"; 378 }; 379 380 lpuart5: serial@29a0000 { 381 compatible = "fsl,ls1021a-lpuart"; 382 reg = <0x0 0x29a0000 0x0 0x1000>; 383 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&platform_clk 1>; 385 clock-names = "ipg"; 386 status = "disabled"; 387 }; 388 389 wdog0: watchdog@2ad0000 { 390 compatible = "fsl,imx21-wdt"; 391 reg = <0x0 0x2ad0000 0x0 0x10000>; 392 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&platform_clk 1>; 394 clock-names = "wdog-en"; 395 big-endian; 396 }; 397 398 sai1: sai@2b50000 { 399 #sound-dai-cells = <0>; 400 compatible = "fsl,vf610-sai"; 401 reg = <0x0 0x2b50000 0x0 0x10000>; 402 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&platform_clk 1>, <&platform_clk 1>, 404 <&platform_clk 1>, <&platform_clk 1>; 405 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 406 dma-names = "tx", "rx"; 407 dmas = <&edma0 1 47>, 408 <&edma0 1 46>; 409 status = "disabled"; 410 }; 411 412 sai2: sai@2b60000 { 413 #sound-dai-cells = <0>; 414 compatible = "fsl,vf610-sai"; 415 reg = <0x0 0x2b60000 0x0 0x10000>; 416 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&platform_clk 1>, <&platform_clk 1>, 418 <&platform_clk 1>, <&platform_clk 1>; 419 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 420 dma-names = "tx", "rx"; 421 dmas = <&edma0 1 45>, 422 <&edma0 1 44>; 423 status = "disabled"; 424 }; 425 426 edma0: edma@2c00000 { 427 #dma-cells = <2>; 428 compatible = "fsl,vf610-edma"; 429 reg = <0x0 0x2c00000 0x0 0x10000>, 430 <0x0 0x2c10000 0x0 0x10000>, 431 <0x0 0x2c20000 0x0 0x10000>; 432 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 434 interrupt-names = "edma-tx", "edma-err"; 435 dma-channels = <32>; 436 big-endian; 437 clock-names = "dmamux0", "dmamux1"; 438 clocks = <&platform_clk 1>, 439 <&platform_clk 1>; 440 }; 441 442 dcu: dcu@2ce0000 { 443 compatible = "fsl,ls1021a-dcu"; 444 reg = <0x0 0x2ce0000 0x0 0x10000>; 445 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&platform_clk 0>; 447 clock-names = "dcu"; 448 big-endian; 449 status = "disabled"; 450 }; 451 452 mdio0: mdio@2d24000 { 453 compatible = "gianfar"; 454 device_type = "mdio"; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 reg = <0x0 0x2d24000 0x0 0x4000>; 458 }; 459 460 enet0: ethernet@2d10000 { 461 compatible = "fsl,etsec2"; 462 device_type = "network"; 463 #address-cells = <2>; 464 #size-cells = <2>; 465 interrupt-parent = <&gic>; 466 model = "eTSEC"; 467 fsl,magic-packet; 468 ranges; 469 dma-coherent; 470 471 queue-group@2d10000 { 472 #address-cells = <2>; 473 #size-cells = <2>; 474 reg = <0x0 0x2d10000 0x0 0x1000>; 475 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 478 }; 479 480 queue-group@2d14000 { 481 #address-cells = <2>; 482 #size-cells = <2>; 483 reg = <0x0 0x2d14000 0x0 0x1000>; 484 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 487 }; 488 }; 489 490 enet1: ethernet@2d50000 { 491 compatible = "fsl,etsec2"; 492 device_type = "network"; 493 #address-cells = <2>; 494 #size-cells = <2>; 495 interrupt-parent = <&gic>; 496 model = "eTSEC"; 497 ranges; 498 dma-coherent; 499 500 queue-group@2d50000 { 501 #address-cells = <2>; 502 #size-cells = <2>; 503 reg = <0x0 0x2d50000 0x0 0x1000>; 504 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 507 }; 508 509 queue-group@2d54000 { 510 #address-cells = <2>; 511 #size-cells = <2>; 512 reg = <0x0 0x2d54000 0x0 0x1000>; 513 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 516 }; 517 }; 518 519 enet2: ethernet@2d90000 { 520 compatible = "fsl,etsec2"; 521 device_type = "network"; 522 #address-cells = <2>; 523 #size-cells = <2>; 524 interrupt-parent = <&gic>; 525 model = "eTSEC"; 526 ranges; 527 dma-coherent; 528 529 queue-group@2d90000 { 530 #address-cells = <2>; 531 #size-cells = <2>; 532 reg = <0x0 0x2d90000 0x0 0x1000>; 533 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 536 }; 537 538 queue-group@2d94000 { 539 #address-cells = <2>; 540 #size-cells = <2>; 541 reg = <0x0 0x2d94000 0x0 0x1000>; 542 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 545 }; 546 }; 547 548 usb@8600000 { 549 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 550 reg = <0x0 0x8600000 0x0 0x1000>; 551 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 552 dr_mode = "host"; 553 phy_type = "ulpi"; 554 }; 555 556 usb3@3100000 { 557 compatible = "snps,dwc3"; 558 reg = <0x0 0x3100000 0x0 0x10000>; 559 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 560 dr_mode = "host"; 561 snps,quirk-frame-length-adjustment = <0x20>; 562 }; 563 }; 564}; 565