1/* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48/dts-v1/; 49#include "ls1021a.dtsi" 50 51/ { 52 model = "LS1021A QDS Board"; 53 54 aliases { 55 enet0_rgmii_phy = &rgmii_phy1; 56 enet1_rgmii_phy = &rgmii_phy2; 57 enet2_rgmii_phy = &rgmii_phy3; 58 enet0_sgmii_phy = &sgmii_phy1c; 59 enet1_sgmii_phy = &sgmii_phy1d; 60 }; 61 62 sys_mclk: clock-mclk { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <24576000>; 66 }; 67 68 regulators { 69 compatible = "simple-bus"; 70 #address-cells = <1>; 71 #size-cells = <0>; 72 73 reg_3p3v: regulator@0 { 74 compatible = "regulator-fixed"; 75 reg = <0>; 76 regulator-name = "3P3V"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 regulator-always-on; 80 }; 81 }; 82 83 sound { 84 compatible = "simple-audio-card"; 85 simple-audio-card,format = "i2s"; 86 simple-audio-card,widgets = 87 "Microphone", "Microphone Jack", 88 "Headphone", "Headphone Jack", 89 "Speaker", "Speaker Ext", 90 "Line", "Line In Jack"; 91 simple-audio-card,routing = 92 "MIC_IN", "Microphone Jack", 93 "Microphone Jack", "Mic Bias", 94 "LINE_IN", "Line In Jack", 95 "Headphone Jack", "HP_OUT", 96 "Speaker Ext", "LINE_OUT"; 97 98 simple-audio-card,cpu { 99 sound-dai = <&sai2>; 100 frame-master; 101 bitclock-master; 102 }; 103 104 simple-audio-card,codec { 105 sound-dai = <&codec>; 106 frame-master; 107 bitclock-master; 108 }; 109 }; 110}; 111 112&dspi0 { 113 bus-num = <0>; 114 status = "okay"; 115 116 dspiflash: at45db021d@0 { 117 #address-cells = <1>; 118 #size-cells = <1>; 119 compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash"; 120 spi-max-frequency = <16000000>; 121 spi-cpol; 122 spi-cpha; 123 reg = <0>; 124 }; 125}; 126 127&enet0 { 128 tbi-handle = <&tbi0>; 129 phy-handle = <&sgmii_phy1c>; 130 phy-connection-type = "sgmii"; 131 status = "okay"; 132}; 133 134&enet1 { 135 tbi-handle = <&tbi0>; 136 phy-handle = <&sgmii_phy1d>; 137 phy-connection-type = "sgmii"; 138 status = "okay"; 139}; 140 141&enet2 { 142 phy-handle = <&rgmii_phy3>; 143 phy-connection-type = "rgmii-id"; 144 status = "okay"; 145}; 146 147&i2c0 { 148 status = "okay"; 149 150 pca9547: mux@77 { 151 compatible = "nxp,pca9547"; 152 reg = <0x77>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 156 i2c@0 { 157 #address-cells = <1>; 158 #size-cells = <0>; 159 reg = <0x0>; 160 161 ds3232: rtc@68 { 162 compatible = "dallas,ds3232"; 163 reg = <0x68>; 164 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 165 }; 166 }; 167 168 i2c@2 { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 reg = <0x2>; 172 173 ina220@40 { 174 compatible = "ti,ina220"; 175 reg = <0x40>; 176 shunt-resistor = <1000>; 177 }; 178 179 ina220@41 { 180 compatible = "ti,ina220"; 181 reg = <0x41>; 182 shunt-resistor = <1000>; 183 }; 184 }; 185 186 i2c@3 { 187 #address-cells = <1>; 188 #size-cells = <0>; 189 reg = <0x3>; 190 191 eeprom@56 { 192 compatible = "atmel,24c512"; 193 reg = <0x56>; 194 }; 195 196 eeprom@57 { 197 compatible = "atmel,24c512"; 198 reg = <0x57>; 199 }; 200 201 adt7461a@4c { 202 compatible = "adi,adt7461a"; 203 reg = <0x4c>; 204 }; 205 }; 206 207 i2c@4 { 208 #address-cells = <1>; 209 #size-cells = <0>; 210 reg = <0x4>; 211 212 codec: sgtl5000@2a { 213 #sound-dai-cells = <0>; 214 compatible = "fsl,sgtl5000"; 215 reg = <0x2a>; 216 VDDA-supply = <®_3p3v>; 217 VDDIO-supply = <®_3p3v>; 218 clocks = <&sys_mclk 1>; 219 }; 220 }; 221 }; 222}; 223 224&ifc { 225 #address-cells = <2>; 226 #size-cells = <1>; 227 /* NOR, NAND Flashes and FPGA on board */ 228 ranges = <0x0 0x0 0x0 0x60000000 0x08000000 229 0x2 0x0 0x0 0x7e800000 0x00010000 230 0x3 0x0 0x0 0x7fb00000 0x00000100>; 231 status = "okay"; 232 233 nor@0,0 { 234 #address-cells = <1>; 235 #size-cells = <1>; 236 compatible = "cfi-flash"; 237 reg = <0x0 0x0 0x8000000>; 238 bank-width = <2>; 239 device-width = <1>; 240 }; 241 242 fpga: board-control@3,0 { 243 #address-cells = <1>; 244 #size-cells = <1>; 245 compatible = "simple-bus"; 246 reg = <0x3 0x0 0x0000100>; 247 bank-width = <1>; 248 device-width = <1>; 249 ranges = <0 3 0 0x100>; 250 251 mdio-mux-emi1 { 252 compatible = "mdio-mux-mmioreg"; 253 mdio-parent-bus = <&mdio0>; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 reg = <0x54 1>; /* BRDCFG4 */ 257 mux-mask = <0xe0>; /* EMI1[2:0] */ 258 259 /* Onboard PHYs */ 260 ls1021amdio0: mdio@0 { 261 reg = <0>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 rgmii_phy1: ethernet-phy@1 { 265 reg = <0x1>; 266 }; 267 }; 268 269 ls1021amdio1: mdio@20 { 270 reg = <0x20>; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 rgmii_phy2: ethernet-phy@2 { 274 reg = <0x2>; 275 }; 276 }; 277 278 ls1021amdio2: mdio@40 { 279 reg = <0x40>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 rgmii_phy3: ethernet-phy@3 { 283 reg = <0x3>; 284 }; 285 }; 286 287 ls1021amdio3: mdio@60 { 288 reg = <0x60>; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 sgmii_phy1c: ethernet-phy@1c { 292 reg = <0x1c>; 293 }; 294 }; 295 296 ls1021amdio4: mdio@80 { 297 reg = <0x80>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 sgmii_phy1d: ethernet-phy@1d { 301 reg = <0x1d>; 302 }; 303 }; 304 }; 305 }; 306}; 307 308&lpuart0 { 309 status = "okay"; 310}; 311 312&mdio0 { 313 tbi0: tbi-phy@8 { 314 reg = <0x8>; 315 device_type = "tbi-phy"; 316 }; 317}; 318 319&sai2 { 320 status = "okay"; 321}; 322 323&sata { 324 status = "okay"; 325}; 326 327&uart0 { 328 status = "okay"; 329}; 330 331&uart1 { 332 status = "okay"; 333}; 334