1295011Sandrew/* 2295011Sandrew * Common base for NXP LPC18xx and LPC43xx devices. 3295011Sandrew * 4295011Sandrew * Copyright 2015 Joachim Eastwood <manabian@gmail.com> 5295011Sandrew * 6295011Sandrew * This code is released using a dual license strategy: BSD/GPL 7295011Sandrew * You can choose the licence that better fits your requirements. 8295011Sandrew * 9295011Sandrew * Released under the terms of 3-clause BSD License 10295011Sandrew * Released under the terms of GNU General Public License Version 2.0 11295011Sandrew * 12295011Sandrew */ 13295011Sandrew 14295011Sandrew#include "armv7-m.dtsi" 15295011Sandrew 16295011Sandrew#include "dt-bindings/clock/lpc18xx-cgu.h" 17295011Sandrew#include "dt-bindings/clock/lpc18xx-ccu.h" 18295011Sandrew 19295011Sandrew#define LPC_PIN(port, pin) (0x##port * 32 + pin) 20295011Sandrew#define LPC_GPIO(port, pin) (port * 32 + pin) 21295011Sandrew 22295011Sandrew/ { 23295011Sandrew cpus { 24295011Sandrew #address-cells = <1>; 25295011Sandrew #size-cells = <0>; 26295011Sandrew 27295011Sandrew cpu@0 { 28295011Sandrew compatible = "arm,cortex-m3"; 29295011Sandrew device_type = "cpu"; 30295011Sandrew reg = <0x0>; 31295011Sandrew clocks = <&ccu1 CLK_CPU_CORE>; 32295011Sandrew }; 33295011Sandrew }; 34295011Sandrew 35295011Sandrew clocks { 36295011Sandrew xtal: xtal { 37295011Sandrew compatible = "fixed-clock"; 38295011Sandrew #clock-cells = <0>; 39295011Sandrew clock-frequency = <12000000>; 40295011Sandrew }; 41295011Sandrew 42295011Sandrew xtal32: xtal32 { 43295011Sandrew compatible = "fixed-clock"; 44295011Sandrew #clock-cells = <0>; 45295011Sandrew clock-frequency = <32768>; 46295011Sandrew }; 47295011Sandrew 48295011Sandrew enet_rx_clk: enet_rx_clk { 49295011Sandrew compatible = "fixed-clock"; 50295011Sandrew #clock-cells = <0>; 51295011Sandrew clock-frequency = <0>; 52295011Sandrew clock-output-names = "enet_rx_clk"; 53295011Sandrew }; 54295011Sandrew 55295011Sandrew enet_tx_clk: enet_tx_clk { 56295011Sandrew compatible = "fixed-clock"; 57295011Sandrew #clock-cells = <0>; 58295011Sandrew clock-frequency = <0>; 59295011Sandrew clock-output-names = "enet_tx_clk"; 60295011Sandrew }; 61295011Sandrew 62295011Sandrew gp_clkin: gp_clkin { 63295011Sandrew compatible = "fixed-clock"; 64295011Sandrew #clock-cells = <0>; 65295011Sandrew clock-frequency = <0>; 66295011Sandrew clock-output-names = "gp_clkin"; 67295011Sandrew }; 68295011Sandrew }; 69295011Sandrew 70295011Sandrew soc { 71295011Sandrew sct_pwm: pwm@40000000 { 72295011Sandrew compatible = "nxp,lpc1850-sct-pwm"; 73295011Sandrew reg = <0x40000000 0x1000>; 74295011Sandrew clocks =<&ccu1 CLK_CPU_SCT>; 75295011Sandrew clock-names = "pwm"; 76295011Sandrew resets = <&rgu 37>; 77295011Sandrew #pwm-cells = <3>; 78295011Sandrew status = "disabled"; 79295011Sandrew }; 80295011Sandrew 81295011Sandrew dmac: dma-controller@40002000 { 82295011Sandrew compatible = "arm,pl080", "arm,primecell"; 83295011Sandrew arm,primecell-periphid = <0x00041080>; 84295011Sandrew reg = <0x40002000 0x1000>; 85295011Sandrew interrupts = <2>; 86295011Sandrew clocks = <&ccu1 CLK_CPU_DMA>; 87295011Sandrew clock-names = "apb_pclk"; 88295011Sandrew resets = <&rgu 19>; 89295011Sandrew #dma-cells = <2>; 90295011Sandrew dma-channels = <8>; 91295011Sandrew dma-requests = <16>; 92295011Sandrew lli-bus-interface-ahb1; 93295011Sandrew lli-bus-interface-ahb2; 94295011Sandrew mem-bus-interface-ahb1; 95295011Sandrew mem-bus-interface-ahb2; 96295011Sandrew memcpy-burst-size = <256>; 97295011Sandrew memcpy-bus-width = <32>; 98295011Sandrew }; 99295011Sandrew 100295011Sandrew spifi: flash-controller@40003000 { 101295011Sandrew compatible = "nxp,lpc1773-spifi"; 102295011Sandrew reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; 103295011Sandrew reg-names = "spifi", "flash"; 104295011Sandrew interrupts = <30>; 105295011Sandrew clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; 106295011Sandrew clock-names = "spifi", "reg"; 107295011Sandrew resets = <&rgu 53>; 108295011Sandrew status = "disabled"; 109295011Sandrew }; 110295011Sandrew 111295011Sandrew mmcsd: mmcsd@40004000 { 112295011Sandrew compatible = "snps,dw-mshc"; 113295011Sandrew reg = <0x40004000 0x1000>; 114295011Sandrew interrupts = <6>; 115295011Sandrew num-slots = <1>; 116295011Sandrew clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; 117295011Sandrew clock-names = "ciu", "biu"; 118295011Sandrew resets = <&rgu 20>; 119295011Sandrew status = "disabled"; 120295011Sandrew }; 121295011Sandrew 122295011Sandrew usb0: ehci@40006100 { 123295011Sandrew compatible = "nxp,lpc1850-ehci", "generic-ehci"; 124295011Sandrew reg = <0x40006100 0x100>; 125295011Sandrew interrupts = <8>; 126295011Sandrew clocks = <&ccu1 CLK_CPU_USB0>; 127295011Sandrew resets = <&rgu 17>; 128295011Sandrew phys = <&usb0_otg_phy>; 129295011Sandrew phy-names = "usb"; 130295011Sandrew has-transaction-translator; 131295011Sandrew status = "disabled"; 132295011Sandrew }; 133295011Sandrew 134295011Sandrew usb1: ehci@40007100 { 135295011Sandrew compatible = "nxp,lpc1850-ehci", "generic-ehci"; 136295011Sandrew reg = <0x40007100 0x100>; 137295011Sandrew interrupts = <9>; 138295011Sandrew clocks = <&ccu1 CLK_CPU_USB1>; 139295011Sandrew resets = <&rgu 18>; 140295011Sandrew status = "disabled"; 141295011Sandrew }; 142295011Sandrew 143295011Sandrew emc: memory-controller@40005000 { 144295011Sandrew compatible = "arm,pl172", "arm,primecell"; 145295011Sandrew reg = <0x40005000 0x1000>; 146295011Sandrew clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; 147295011Sandrew clock-names = "mpmcclk", "apb_pclk"; 148295011Sandrew resets = <&rgu 21>; 149295011Sandrew #address-cells = <2>; 150295011Sandrew #size-cells = <1>; 151295011Sandrew ranges = <0 0 0x1c000000 0x1000000 152295011Sandrew 1 0 0x1d000000 0x1000000 153295011Sandrew 2 0 0x1e000000 0x1000000 154295011Sandrew 3 0 0x1f000000 0x1000000>; 155295011Sandrew status = "disabled"; 156295011Sandrew }; 157295011Sandrew 158295011Sandrew lcdc: lcd-controller@40008000 { 159295011Sandrew compatible = "arm,pl111", "arm,primecell"; 160295011Sandrew reg = <0x40008000 0x1000>; 161295011Sandrew interrupts = <7>; 162295011Sandrew interrupt-names = "combined"; 163295011Sandrew clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; 164295011Sandrew clock-names = "clcdclk", "apb_pclk"; 165295011Sandrew resets = <&rgu 16>; 166295011Sandrew status = "disabled"; 167295011Sandrew }; 168295011Sandrew 169295011Sandrew eeprom: eeprom@4000e000 { 170295011Sandrew compatible = "nxp,lpc1857-eeprom"; 171295011Sandrew reg = <0x4000e000 0x1000>, <0x20040000 0x4000>; 172295011Sandrew reg-names = "reg", "mem"; 173295011Sandrew clocks = <&ccu1 CLK_CPU_EEPROM>; 174295011Sandrew clock-names = "eeprom"; 175295011Sandrew resets = <&rgu 27>; 176295011Sandrew interrupts = <4>; 177295011Sandrew status = "disabled"; 178295011Sandrew }; 179295011Sandrew 180295011Sandrew mac: ethernet@40010000 { 181295011Sandrew compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; 182295011Sandrew reg = <0x40010000 0x2000>; 183295011Sandrew interrupts = <5>; 184295011Sandrew interrupt-names = "macirq"; 185295011Sandrew clocks = <&ccu1 CLK_CPU_ETHERNET>; 186295011Sandrew clock-names = "stmmaceth"; 187295011Sandrew resets = <&rgu 22>; 188295011Sandrew reset-names = "stmmaceth"; 189295011Sandrew status = "disabled"; 190295011Sandrew }; 191295011Sandrew 192295011Sandrew creg: syscon@40043000 { 193295011Sandrew compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; 194295011Sandrew reg = <0x40043000 0x1000>; 195295011Sandrew clocks = <&ccu1 CLK_CPU_CREG>; 196295011Sandrew resets = <&rgu 5>; 197295011Sandrew 198295011Sandrew usb0_otg_phy: phy@004 { 199295011Sandrew compatible = "nxp,lpc1850-usb-otg-phy"; 200295011Sandrew clocks = <&ccu1 CLK_USB0>; 201295011Sandrew #phy-cells = <0>; 202295011Sandrew }; 203295011Sandrew 204295011Sandrew dmamux: dma-mux@11c { 205295011Sandrew compatible = "nxp,lpc1850-dmamux"; 206295011Sandrew #dma-cells = <3>; 207295011Sandrew dma-requests = <64>; 208295011Sandrew dma-masters = <&dmac>; 209295011Sandrew }; 210295011Sandrew }; 211295011Sandrew 212295011Sandrew cgu: clock-controller@40050000 { 213295011Sandrew compatible = "nxp,lpc1850-cgu"; 214295011Sandrew reg = <0x40050000 0x1000>; 215295011Sandrew #clock-cells = <1>; 216295011Sandrew clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; 217295011Sandrew }; 218295011Sandrew 219295011Sandrew ccu1: clock-controller@40051000 { 220295011Sandrew compatible = "nxp,lpc1850-ccu"; 221295011Sandrew reg = <0x40051000 0x1000>; 222295011Sandrew #clock-cells = <1>; 223295011Sandrew clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, 224295011Sandrew <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, 225295011Sandrew <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, 226295011Sandrew <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; 227295011Sandrew clock-names = "base_apb3_clk", "base_apb1_clk", 228295011Sandrew "base_spifi_clk", "base_cpu_clk", 229295011Sandrew "base_periph_clk", "base_usb0_clk", 230295011Sandrew "base_usb1_clk", "base_spi_clk"; 231295011Sandrew }; 232295011Sandrew 233295011Sandrew ccu2: clock-controller@40052000 { 234295011Sandrew compatible = "nxp,lpc1850-ccu"; 235295011Sandrew reg = <0x40052000 0x1000>; 236295011Sandrew #clock-cells = <1>; 237295011Sandrew clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, 238295011Sandrew <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, 239295011Sandrew <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, 240295011Sandrew <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; 241295011Sandrew clock-names = "base_audio_clk", "base_uart3_clk", 242295011Sandrew "base_uart2_clk", "base_uart1_clk", 243295011Sandrew "base_uart0_clk", "base_ssp1_clk", 244295011Sandrew "base_ssp0_clk", "base_sdio_clk"; 245295011Sandrew }; 246295011Sandrew 247295011Sandrew rgu: reset-controller@40053000 { 248295011Sandrew compatible = "nxp,lpc1850-rgu"; 249295011Sandrew reg = <0x40053000 0x1000>; 250295011Sandrew clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; 251295011Sandrew clock-names = "delay", "reg"; 252295011Sandrew #reset-cells = <1>; 253295011Sandrew }; 254295011Sandrew 255295011Sandrew watchdog@40080000 { 256295011Sandrew compatible = "nxp,lpc1850-wwdt"; 257295011Sandrew reg = <0x40080000 0x24>; 258295011Sandrew interrupts = <49>; 259295011Sandrew clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>; 260295011Sandrew clock-names = "wdtclk", "reg"; 261295011Sandrew }; 262295011Sandrew 263295011Sandrew uart0: serial@40081000 { 264295011Sandrew compatible = "nxp,lpc1850-uart", "ns16550a"; 265295011Sandrew reg = <0x40081000 0x1000>; 266295011Sandrew reg-shift = <2>; 267295011Sandrew interrupts = <24>; 268295011Sandrew clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; 269295011Sandrew clock-names = "uartclk", "reg"; 270295011Sandrew resets = <&rgu 44>; 271295011Sandrew dmas = <&dmamux 1 1 2 272295011Sandrew &dmamux 2 1 2 273295011Sandrew &dmamux 11 2 2 274295011Sandrew &dmamux 12 2 2>; 275295011Sandrew dma-names = "tx", "rx", "tx", "rx"; 276295011Sandrew status = "disabled"; 277295011Sandrew }; 278295011Sandrew 279295011Sandrew uart1: serial@40082000 { 280295011Sandrew compatible = "nxp,lpc1850-uart", "ns16550a"; 281295011Sandrew reg = <0x40082000 0x1000>; 282295011Sandrew reg-shift = <2>; 283295011Sandrew interrupts = <25>; 284295011Sandrew clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; 285295011Sandrew clock-names = "uartclk", "reg"; 286295011Sandrew resets = <&rgu 45>; 287295011Sandrew dmas = <&dmamux 3 1 2 288295011Sandrew &dmamux 4 1 2>; 289295011Sandrew dma-names = "tx", "rx"; 290295011Sandrew status = "disabled"; 291295011Sandrew }; 292295011Sandrew 293295011Sandrew ssp0: spi@40083000 { 294295011Sandrew compatible = "arm,pl022", "arm,primecell"; 295295011Sandrew reg = <0x40083000 0x1000>; 296295011Sandrew interrupts = <22>; 297295011Sandrew clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; 298295011Sandrew clock-names = "sspclk", "apb_pclk"; 299295011Sandrew resets = <&rgu 50>; 300295011Sandrew dmas = <&dmamux 9 0 2 301295011Sandrew &dmamux 10 0 2>; 302295011Sandrew dma-names = "rx", "tx"; 303295011Sandrew #address-cells = <1>; 304295011Sandrew #size-cells = <0>; 305295011Sandrew status = "disabled"; 306295011Sandrew }; 307295011Sandrew 308295011Sandrew timer0: timer@40084000 { 309295011Sandrew compatible = "nxp,lpc3220-timer"; 310295011Sandrew reg = <0x40084000 0x1000>; 311295011Sandrew interrupts = <12>; 312295011Sandrew clocks = <&ccu1 CLK_CPU_TIMER0>; 313295011Sandrew clock-names = "timerclk"; 314295011Sandrew resets = <&rgu 32>; 315295011Sandrew }; 316295011Sandrew 317295011Sandrew timer1: timer@40085000 { 318295011Sandrew compatible = "nxp,lpc3220-timer"; 319295011Sandrew reg = <0x40085000 0x1000>; 320295011Sandrew interrupts = <13>; 321295011Sandrew clocks = <&ccu1 CLK_CPU_TIMER1>; 322295011Sandrew clock-names = "timerclk"; 323295011Sandrew resets = <&rgu 33>; 324295011Sandrew }; 325295011Sandrew 326295011Sandrew pinctrl: pinctrl@40086000 { 327295011Sandrew compatible = "nxp,lpc1850-scu"; 328295011Sandrew reg = <0x40086000 0x1000>; 329295011Sandrew clocks = <&ccu1 CLK_CPU_SCU>; 330295011Sandrew }; 331295011Sandrew 332295011Sandrew i2c0: i2c@400a1000 { 333295011Sandrew compatible = "nxp,lpc1788-i2c"; 334295011Sandrew reg = <0x400a1000 0x1000>; 335295011Sandrew interrupts = <18>; 336295011Sandrew clocks = <&ccu1 CLK_APB1_I2C0>; 337295011Sandrew resets = <&rgu 48>; 338295011Sandrew #address-cells = <1>; 339295011Sandrew #size-cells = <0>; 340295011Sandrew status = "disabled"; 341295011Sandrew }; 342295011Sandrew 343295011Sandrew can1: can@400a4000 { 344295011Sandrew compatible = "bosch,c_can"; 345295011Sandrew reg = <0x400a4000 0x1000>; 346295011Sandrew interrupts = <43>; 347295011Sandrew clocks = <&ccu1 CLK_APB1_CAN1>; 348295011Sandrew resets = <&rgu 54>; 349295011Sandrew status = "disabled"; 350295011Sandrew }; 351295011Sandrew 352295011Sandrew uart2: serial@400c1000 { 353295011Sandrew compatible = "nxp,lpc1850-uart", "ns16550a"; 354295011Sandrew reg = <0x400c1000 0x1000>; 355295011Sandrew reg-shift = <2>; 356295011Sandrew interrupts = <26>; 357295011Sandrew clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; 358295011Sandrew clock-names = "uartclk", "reg"; 359295011Sandrew resets = <&rgu 46>; 360295011Sandrew dmas = <&dmamux 5 1 2 361295011Sandrew &dmamux 6 1 2>; 362295011Sandrew dma-names = "tx", "rx"; 363295011Sandrew status = "disabled"; 364295011Sandrew }; 365295011Sandrew 366295011Sandrew uart3: serial@400c2000 { 367295011Sandrew compatible = "nxp,lpc1850-uart", "ns16550a"; 368295011Sandrew reg = <0x400c2000 0x1000>; 369295011Sandrew reg-shift = <2>; 370295011Sandrew interrupts = <27>; 371295011Sandrew clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; 372295011Sandrew clock-names = "uartclk", "reg"; 373295011Sandrew resets = <&rgu 47>; 374295011Sandrew dmas = <&dmamux 7 1 2 375295011Sandrew &dmamux 8 1 2 376295011Sandrew &dmamux 13 3 2 377295011Sandrew &dmamux 14 3 2>; 378295011Sandrew dma-names = "tx", "rx", "rx", "tx"; 379295011Sandrew status = "disabled"; 380295011Sandrew }; 381295011Sandrew 382295011Sandrew timer2: timer@400c3000 { 383295011Sandrew compatible = "nxp,lpc3220-timer"; 384295011Sandrew reg = <0x400c3000 0x1000>; 385295011Sandrew interrupts = <14>; 386295011Sandrew clocks = <&ccu1 CLK_CPU_TIMER2>; 387295011Sandrew clock-names = "timerclk"; 388295011Sandrew resets = <&rgu 34>; 389295011Sandrew }; 390295011Sandrew 391295011Sandrew timer3: timer@400c4000 { 392295011Sandrew compatible = "nxp,lpc3220-timer"; 393295011Sandrew reg = <0x400c4000 0x1000>; 394295011Sandrew interrupts = <15>; 395295011Sandrew clocks = <&ccu1 CLK_CPU_TIMER3>; 396295011Sandrew clock-names = "timerclk"; 397295011Sandrew resets = <&rgu 35>; 398295011Sandrew }; 399295011Sandrew 400295011Sandrew ssp1: spi@400c5000 { 401295011Sandrew compatible = "arm,pl022", "arm,primecell"; 402295011Sandrew reg = <0x400c5000 0x1000>; 403295011Sandrew interrupts = <23>; 404295011Sandrew clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; 405295011Sandrew clock-names = "sspclk", "apb_pclk"; 406295011Sandrew resets = <&rgu 51>; 407295011Sandrew dmas = <&dmamux 11 2 2 408295011Sandrew &dmamux 12 2 2 409295011Sandrew &dmamux 3 3 2 410295011Sandrew &dmamux 4 3 2 411295011Sandrew &dmamux 5 2 2 412295011Sandrew &dmamux 6 2 2 413295011Sandrew &dmamux 13 2 2 414295011Sandrew &dmamux 14 2 2>; 415295011Sandrew dma-names = "rx", "tx", "tx", "rx", 416295011Sandrew "tx", "rx", "rx", "tx"; 417295011Sandrew #address-cells = <1>; 418295011Sandrew #size-cells = <0>; 419295011Sandrew status = "disabled"; 420295011Sandrew }; 421295011Sandrew 422295011Sandrew i2c1: i2c@400e0000 { 423295011Sandrew compatible = "nxp,lpc1788-i2c"; 424295011Sandrew reg = <0x400e0000 0x1000>; 425295011Sandrew interrupts = <19>; 426295011Sandrew clocks = <&ccu1 CLK_APB3_I2C1>; 427295011Sandrew resets = <&rgu 49>; 428295011Sandrew #address-cells = <1>; 429295011Sandrew #size-cells = <0>; 430295011Sandrew status = "disabled"; 431295011Sandrew }; 432295011Sandrew 433295011Sandrew can0: can@400e2000 { 434295011Sandrew compatible = "bosch,c_can"; 435295011Sandrew reg = <0x400e2000 0x1000>; 436295011Sandrew interrupts = <51>; 437295011Sandrew clocks = <&ccu1 CLK_APB3_CAN0>; 438295011Sandrew resets = <&rgu 55>; 439295011Sandrew status = "disabled"; 440295011Sandrew }; 441295011Sandrew 442295011Sandrew gpio: gpio@400f4000 { 443295011Sandrew compatible = "nxp,lpc1850-gpio"; 444295011Sandrew reg = <0x400f4000 0x4000>; 445295011Sandrew clocks = <&ccu1 CLK_CPU_GPIO>; 446295011Sandrew gpio-controller; 447295011Sandrew #gpio-cells = <2>; 448295011Sandrew gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, 449295011Sandrew <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, 450295011Sandrew <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, 451295011Sandrew <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, 452295011Sandrew <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, 453295011Sandrew <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, 454295011Sandrew <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, 455295011Sandrew <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, 456295011Sandrew <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, 457295011Sandrew <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, 458295011Sandrew <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, 459295011Sandrew <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, 460295011Sandrew <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, 461295011Sandrew <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, 462295011Sandrew <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, 463295011Sandrew <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, 464295011Sandrew <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, 465295011Sandrew <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, 466295011Sandrew <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, 467295011Sandrew <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, 468295011Sandrew <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, 469295011Sandrew <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, 470295011Sandrew <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, 471295011Sandrew <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, 472295011Sandrew <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, 473295011Sandrew <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, 474295011Sandrew <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, 475295011Sandrew <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, 476295011Sandrew <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, 477295011Sandrew <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, 478295011Sandrew <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, 479295011Sandrew <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, 480295011Sandrew <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, 481295011Sandrew <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, 482295011Sandrew <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, 483295011Sandrew <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, 484295011Sandrew <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, 485295011Sandrew <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, 486295011Sandrew <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, 487295011Sandrew <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; 488295011Sandrew }; 489295011Sandrew }; 490295011Sandrew}; 491