1/* 2 * Common base for NXP LPC18xx and LPC43xx devices. 3 * 4 * Copyright 2015 Joachim Eastwood <manabian@gmail.com> 5 * 6 * This code is released using a dual license strategy: BSD/GPL 7 * You can choose the licence that better fits your requirements. 8 * 9 * Released under the terms of 3-clause BSD License 10 * Released under the terms of GNU General Public License Version 2.0 11 * 12 */ 13 14#include "armv7-m.dtsi" 15 16#include "dt-bindings/clock/lpc18xx-cgu.h" 17#include "dt-bindings/clock/lpc18xx-ccu.h" 18 19#define LPC_PIN(port, pin) (0x##port * 32 + pin) 20#define LPC_GPIO(port, pin) (port * 32 + pin) 21 22/ { 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu@0 { 28 compatible = "arm,cortex-m3"; 29 device_type = "cpu"; 30 reg = <0x0>; 31 clocks = <&ccu1 CLK_CPU_CORE>; 32 }; 33 }; 34 35 clocks { 36 xtal: xtal { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <12000000>; 40 }; 41 42 xtal32: xtal32 { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <32768>; 46 }; 47 48 enet_rx_clk: enet_rx_clk { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <0>; 52 clock-output-names = "enet_rx_clk"; 53 }; 54 55 enet_tx_clk: enet_tx_clk { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 59 clock-output-names = "enet_tx_clk"; 60 }; 61 62 gp_clkin: gp_clkin { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <0>; 66 clock-output-names = "gp_clkin"; 67 }; 68 }; 69 70 soc { 71 sct_pwm: pwm@40000000 { 72 compatible = "nxp,lpc1850-sct-pwm"; 73 reg = <0x40000000 0x1000>; 74 clocks =<&ccu1 CLK_CPU_SCT>; 75 clock-names = "pwm"; 76 resets = <&rgu 37>; 77 #pwm-cells = <3>; 78 status = "disabled"; 79 }; 80 81 dmac: dma-controller@40002000 { 82 compatible = "arm,pl080", "arm,primecell"; 83 arm,primecell-periphid = <0x00041080>; 84 reg = <0x40002000 0x1000>; 85 interrupts = <2>; 86 clocks = <&ccu1 CLK_CPU_DMA>; 87 clock-names = "apb_pclk"; 88 resets = <&rgu 19>; 89 #dma-cells = <2>; 90 dma-channels = <8>; 91 dma-requests = <16>; 92 lli-bus-interface-ahb1; 93 lli-bus-interface-ahb2; 94 mem-bus-interface-ahb1; 95 mem-bus-interface-ahb2; 96 memcpy-burst-size = <256>; 97 memcpy-bus-width = <32>; 98 }; 99 100 spifi: flash-controller@40003000 { 101 compatible = "nxp,lpc1773-spifi"; 102 reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; 103 reg-names = "spifi", "flash"; 104 interrupts = <30>; 105 clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; 106 clock-names = "spifi", "reg"; 107 resets = <&rgu 53>; 108 status = "disabled"; 109 }; 110 111 mmcsd: mmcsd@40004000 { 112 compatible = "snps,dw-mshc"; 113 reg = <0x40004000 0x1000>; 114 interrupts = <6>; 115 num-slots = <1>; 116 clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; 117 clock-names = "ciu", "biu"; 118 resets = <&rgu 20>; 119 status = "disabled"; 120 }; 121 122 usb0: ehci@40006100 { 123 compatible = "nxp,lpc1850-ehci", "generic-ehci"; 124 reg = <0x40006100 0x100>; 125 interrupts = <8>; 126 clocks = <&ccu1 CLK_CPU_USB0>; 127 resets = <&rgu 17>; 128 phys = <&usb0_otg_phy>; 129 phy-names = "usb"; 130 has-transaction-translator; 131 status = "disabled"; 132 }; 133 134 usb1: ehci@40007100 { 135 compatible = "nxp,lpc1850-ehci", "generic-ehci"; 136 reg = <0x40007100 0x100>; 137 interrupts = <9>; 138 clocks = <&ccu1 CLK_CPU_USB1>; 139 resets = <&rgu 18>; 140 status = "disabled"; 141 }; 142 143 emc: memory-controller@40005000 { 144 compatible = "arm,pl172", "arm,primecell"; 145 reg = <0x40005000 0x1000>; 146 clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; 147 clock-names = "mpmcclk", "apb_pclk"; 148 resets = <&rgu 21>; 149 #address-cells = <2>; 150 #size-cells = <1>; 151 ranges = <0 0 0x1c000000 0x1000000 152 1 0 0x1d000000 0x1000000 153 2 0 0x1e000000 0x1000000 154 3 0 0x1f000000 0x1000000>; 155 status = "disabled"; 156 }; 157 158 lcdc: lcd-controller@40008000 { 159 compatible = "arm,pl111", "arm,primecell"; 160 reg = <0x40008000 0x1000>; 161 interrupts = <7>; 162 interrupt-names = "combined"; 163 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; 164 clock-names = "clcdclk", "apb_pclk"; 165 resets = <&rgu 16>; 166 status = "disabled"; 167 }; 168 169 eeprom: eeprom@4000e000 { 170 compatible = "nxp,lpc1857-eeprom"; 171 reg = <0x4000e000 0x1000>, <0x20040000 0x4000>; 172 reg-names = "reg", "mem"; 173 clocks = <&ccu1 CLK_CPU_EEPROM>; 174 clock-names = "eeprom"; 175 resets = <&rgu 27>; 176 interrupts = <4>; 177 status = "disabled"; 178 }; 179 180 mac: ethernet@40010000 { 181 compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; 182 reg = <0x40010000 0x2000>; 183 interrupts = <5>; 184 interrupt-names = "macirq"; 185 clocks = <&ccu1 CLK_CPU_ETHERNET>; 186 clock-names = "stmmaceth"; 187 resets = <&rgu 22>; 188 reset-names = "stmmaceth"; 189 status = "disabled"; 190 }; 191 192 creg: syscon@40043000 { 193 compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; 194 reg = <0x40043000 0x1000>; 195 clocks = <&ccu1 CLK_CPU_CREG>; 196 resets = <&rgu 5>; 197 198 usb0_otg_phy: phy@004 { 199 compatible = "nxp,lpc1850-usb-otg-phy"; 200 clocks = <&ccu1 CLK_USB0>; 201 #phy-cells = <0>; 202 }; 203 204 dmamux: dma-mux@11c { 205 compatible = "nxp,lpc1850-dmamux"; 206 #dma-cells = <3>; 207 dma-requests = <64>; 208 dma-masters = <&dmac>; 209 }; 210 }; 211 212 cgu: clock-controller@40050000 { 213 compatible = "nxp,lpc1850-cgu"; 214 reg = <0x40050000 0x1000>; 215 #clock-cells = <1>; 216 clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; 217 }; 218 219 ccu1: clock-controller@40051000 { 220 compatible = "nxp,lpc1850-ccu"; 221 reg = <0x40051000 0x1000>; 222 #clock-cells = <1>; 223 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, 224 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, 225 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, 226 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; 227 clock-names = "base_apb3_clk", "base_apb1_clk", 228 "base_spifi_clk", "base_cpu_clk", 229 "base_periph_clk", "base_usb0_clk", 230 "base_usb1_clk", "base_spi_clk"; 231 }; 232 233 ccu2: clock-controller@40052000 { 234 compatible = "nxp,lpc1850-ccu"; 235 reg = <0x40052000 0x1000>; 236 #clock-cells = <1>; 237 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, 238 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, 239 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, 240 <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; 241 clock-names = "base_audio_clk", "base_uart3_clk", 242 "base_uart2_clk", "base_uart1_clk", 243 "base_uart0_clk", "base_ssp1_clk", 244 "base_ssp0_clk", "base_sdio_clk"; 245 }; 246 247 rgu: reset-controller@40053000 { 248 compatible = "nxp,lpc1850-rgu"; 249 reg = <0x40053000 0x1000>; 250 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; 251 clock-names = "delay", "reg"; 252 #reset-cells = <1>; 253 }; 254 255 watchdog@40080000 { 256 compatible = "nxp,lpc1850-wwdt"; 257 reg = <0x40080000 0x24>; 258 interrupts = <49>; 259 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>; 260 clock-names = "wdtclk", "reg"; 261 }; 262 263 uart0: serial@40081000 { 264 compatible = "nxp,lpc1850-uart", "ns16550a"; 265 reg = <0x40081000 0x1000>; 266 reg-shift = <2>; 267 interrupts = <24>; 268 clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; 269 clock-names = "uartclk", "reg"; 270 resets = <&rgu 44>; 271 dmas = <&dmamux 1 1 2 272 &dmamux 2 1 2 273 &dmamux 11 2 2 274 &dmamux 12 2 2>; 275 dma-names = "tx", "rx", "tx", "rx"; 276 status = "disabled"; 277 }; 278 279 uart1: serial@40082000 { 280 compatible = "nxp,lpc1850-uart", "ns16550a"; 281 reg = <0x40082000 0x1000>; 282 reg-shift = <2>; 283 interrupts = <25>; 284 clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; 285 clock-names = "uartclk", "reg"; 286 resets = <&rgu 45>; 287 dmas = <&dmamux 3 1 2 288 &dmamux 4 1 2>; 289 dma-names = "tx", "rx"; 290 status = "disabled"; 291 }; 292 293 ssp0: spi@40083000 { 294 compatible = "arm,pl022", "arm,primecell"; 295 reg = <0x40083000 0x1000>; 296 interrupts = <22>; 297 clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; 298 clock-names = "sspclk", "apb_pclk"; 299 resets = <&rgu 50>; 300 dmas = <&dmamux 9 0 2 301 &dmamux 10 0 2>; 302 dma-names = "rx", "tx"; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 status = "disabled"; 306 }; 307 308 timer0: timer@40084000 { 309 compatible = "nxp,lpc3220-timer"; 310 reg = <0x40084000 0x1000>; 311 interrupts = <12>; 312 clocks = <&ccu1 CLK_CPU_TIMER0>; 313 clock-names = "timerclk"; 314 resets = <&rgu 32>; 315 }; 316 317 timer1: timer@40085000 { 318 compatible = "nxp,lpc3220-timer"; 319 reg = <0x40085000 0x1000>; 320 interrupts = <13>; 321 clocks = <&ccu1 CLK_CPU_TIMER1>; 322 clock-names = "timerclk"; 323 resets = <&rgu 33>; 324 }; 325 326 pinctrl: pinctrl@40086000 { 327 compatible = "nxp,lpc1850-scu"; 328 reg = <0x40086000 0x1000>; 329 clocks = <&ccu1 CLK_CPU_SCU>; 330 }; 331 332 i2c0: i2c@400a1000 { 333 compatible = "nxp,lpc1788-i2c"; 334 reg = <0x400a1000 0x1000>; 335 interrupts = <18>; 336 clocks = <&ccu1 CLK_APB1_I2C0>; 337 resets = <&rgu 48>; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 status = "disabled"; 341 }; 342 343 can1: can@400a4000 { 344 compatible = "bosch,c_can"; 345 reg = <0x400a4000 0x1000>; 346 interrupts = <43>; 347 clocks = <&ccu1 CLK_APB1_CAN1>; 348 resets = <&rgu 54>; 349 status = "disabled"; 350 }; 351 352 uart2: serial@400c1000 { 353 compatible = "nxp,lpc1850-uart", "ns16550a"; 354 reg = <0x400c1000 0x1000>; 355 reg-shift = <2>; 356 interrupts = <26>; 357 clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; 358 clock-names = "uartclk", "reg"; 359 resets = <&rgu 46>; 360 dmas = <&dmamux 5 1 2 361 &dmamux 6 1 2>; 362 dma-names = "tx", "rx"; 363 status = "disabled"; 364 }; 365 366 uart3: serial@400c2000 { 367 compatible = "nxp,lpc1850-uart", "ns16550a"; 368 reg = <0x400c2000 0x1000>; 369 reg-shift = <2>; 370 interrupts = <27>; 371 clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; 372 clock-names = "uartclk", "reg"; 373 resets = <&rgu 47>; 374 dmas = <&dmamux 7 1 2 375 &dmamux 8 1 2 376 &dmamux 13 3 2 377 &dmamux 14 3 2>; 378 dma-names = "tx", "rx", "rx", "tx"; 379 status = "disabled"; 380 }; 381 382 timer2: timer@400c3000 { 383 compatible = "nxp,lpc3220-timer"; 384 reg = <0x400c3000 0x1000>; 385 interrupts = <14>; 386 clocks = <&ccu1 CLK_CPU_TIMER2>; 387 clock-names = "timerclk"; 388 resets = <&rgu 34>; 389 }; 390 391 timer3: timer@400c4000 { 392 compatible = "nxp,lpc3220-timer"; 393 reg = <0x400c4000 0x1000>; 394 interrupts = <15>; 395 clocks = <&ccu1 CLK_CPU_TIMER3>; 396 clock-names = "timerclk"; 397 resets = <&rgu 35>; 398 }; 399 400 ssp1: spi@400c5000 { 401 compatible = "arm,pl022", "arm,primecell"; 402 reg = <0x400c5000 0x1000>; 403 interrupts = <23>; 404 clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; 405 clock-names = "sspclk", "apb_pclk"; 406 resets = <&rgu 51>; 407 dmas = <&dmamux 11 2 2 408 &dmamux 12 2 2 409 &dmamux 3 3 2 410 &dmamux 4 3 2 411 &dmamux 5 2 2 412 &dmamux 6 2 2 413 &dmamux 13 2 2 414 &dmamux 14 2 2>; 415 dma-names = "rx", "tx", "tx", "rx", 416 "tx", "rx", "rx", "tx"; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 status = "disabled"; 420 }; 421 422 i2c1: i2c@400e0000 { 423 compatible = "nxp,lpc1788-i2c"; 424 reg = <0x400e0000 0x1000>; 425 interrupts = <19>; 426 clocks = <&ccu1 CLK_APB3_I2C1>; 427 resets = <&rgu 49>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 status = "disabled"; 431 }; 432 433 can0: can@400e2000 { 434 compatible = "bosch,c_can"; 435 reg = <0x400e2000 0x1000>; 436 interrupts = <51>; 437 clocks = <&ccu1 CLK_APB3_CAN0>; 438 resets = <&rgu 55>; 439 status = "disabled"; 440 }; 441 442 gpio: gpio@400f4000 { 443 compatible = "nxp,lpc1850-gpio"; 444 reg = <0x400f4000 0x4000>; 445 clocks = <&ccu1 CLK_CPU_GPIO>; 446 gpio-controller; 447 #gpio-cells = <2>; 448 gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, 449 <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, 450 <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, 451 <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, 452 <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, 453 <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, 454 <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, 455 <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, 456 <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, 457 <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, 458 <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, 459 <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, 460 <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, 461 <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, 462 <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, 463 <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, 464 <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, 465 <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, 466 <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, 467 <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, 468 <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, 469 <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, 470 <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, 471 <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, 472 <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, 473 <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, 474 <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, 475 <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, 476 <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, 477 <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, 478 <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, 479 <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, 480 <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, 481 <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, 482 <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, 483 <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, 484 <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, 485 <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, 486 <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, 487 <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; 488 }; 489 }; 490}; 491