1270866Simp/* 2270866Simp * Copyright 2014 FEDEVEL, Inc. 3270866Simp * 4270866Simp * Author: Robert Nelson <robertcnelson@gmail.com> 5270866Simp * 6270866Simp * This program is free software; you can redistribute it and/or modify 7270866Simp * it under the terms of the GNU General Public License version 2 as 8270866Simp * published by the Free Software Foundation. 9270866Simp * 10270866Simp */ 11270866Simp 12270866Simp#include <dt-bindings/gpio/gpio.h> 13270866Simp#include <dt-bindings/input/input.h> 14270866Simp 15270866Simp/ { 16270866Simp chosen { 17270866Simp stdout-path = &uart1; 18270866Simp }; 19270866Simp 20270866Simp regulators { 21270866Simp compatible = "simple-bus"; 22270866Simp #address-cells = <1>; 23270866Simp #size-cells = <0>; 24270866Simp 25270866Simp reg_3p3v: regulator@0 { 26270866Simp compatible = "regulator-fixed"; 27270866Simp reg = <0>; 28270866Simp regulator-name = "3P3V"; 29270866Simp regulator-min-microvolt = <3300000>; 30270866Simp regulator-max-microvolt = <3300000>; 31270866Simp regulator-always-on; 32270866Simp }; 33270866Simp 34270866Simp reg_usbh1_vbus: regulator@1 { 35270866Simp compatible = "regulator-fixed"; 36270866Simp reg = <1>; 37270866Simp pinctrl-names = "default"; 38270866Simp regulator-name = "usbh1_vbus"; 39270866Simp regulator-min-microvolt = <5000000>; 40270866Simp regulator-max-microvolt = <5000000>; 41270866Simp gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; 42270866Simp enable-active-high; 43270866Simp }; 44270866Simp 45270866Simp reg_usb_otg_vbus: regulator@2 { 46270866Simp compatible = "regulator-fixed"; 47270866Simp reg = <2>; 48270866Simp pinctrl-names = "default"; 49270866Simp regulator-name = "usb_otg_vbus"; 50270866Simp regulator-min-microvolt = <5000000>; 51270866Simp regulator-max-microvolt = <5000000>; 52270866Simp gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 53270866Simp enable-active-high; 54270866Simp }; 55270866Simp }; 56270866Simp 57270866Simp leds { 58270866Simp compatible = "gpio-leds"; 59270866Simp pinctrl-names = "default"; 60270866Simp pinctrl-0 = <&pinctrl_led>; 61270866Simp 62270866Simp led0: usr { 63270866Simp label = "usr"; 64270866Simp gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; 65270866Simp default-state = "off"; 66270866Simp linux,default-trigger = "heartbeat"; 67270866Simp }; 68270866Simp }; 69270866Simp 70270866Simp sound { 71270866Simp compatible = "fsl,imx6-rex-sgtl5000", 72270866Simp "fsl,imx-audio-sgtl5000"; 73270866Simp model = "imx6-rex-sgtl5000"; 74270866Simp ssi-controller = <&ssi1>; 75270866Simp audio-codec = <&codec>; 76270866Simp audio-routing = 77270866Simp "MIC_IN", "Mic Jack", 78270866Simp "Mic Jack", "Mic Bias", 79270866Simp "Headphone Jack", "HP_OUT"; 80270866Simp mux-int-port = <1>; 81270866Simp mux-ext-port = <3>; 82270866Simp }; 83270866Simp}; 84270866Simp 85270866Simp&audmux { 86270866Simp pinctrl-names = "default"; 87270866Simp pinctrl-0 = <&pinctrl_audmux>; 88270866Simp status = "okay"; 89270866Simp}; 90270866Simp 91270866Simp&ecspi2 { 92270866Simp fsl,spi-num-chipselects = <1>; 93270866Simp cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; 94270866Simp pinctrl-names = "default"; 95270866Simp pinctrl-0 = <&pinctrl_ecspi2>; 96270866Simp status = "okay"; 97270866Simp}; 98270866Simp 99270866Simp&ecspi3 { 100270866Simp fsl,spi-num-chipselects = <1>; 101270866Simp cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; 102270866Simp pinctrl-names = "default"; 103270866Simp pinctrl-0 = <&pinctrl_ecspi3>; 104270866Simp status = "okay"; 105270866Simp}; 106270866Simp 107270866Simp&fec { 108270866Simp pinctrl-names = "default"; 109270866Simp pinctrl-0 = <&pinctrl_enet>; 110270866Simp phy-mode = "rgmii"; 111270866Simp phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 112270866Simp status = "okay"; 113270866Simp}; 114270866Simp 115270866Simp&hdmi { 116270866Simp ddc-i2c-bus = <&i2c2>; 117270866Simp status = "okay"; 118270866Simp}; 119270866Simp 120270866Simp&i2c1 { 121270866Simp clock-frequency = <100000>; 122270866Simp pinctrl-names = "default"; 123270866Simp pinctrl-0 = <&pinctrl_i2c1>; 124270866Simp status = "okay"; 125270866Simp 126270866Simp codec: sgtl5000@0a { 127270866Simp compatible = "fsl,sgtl5000"; 128270866Simp reg = <0x0a>; 129270866Simp clocks = <&clks 201>; 130270866Simp VDDA-supply = <®_3p3v>; 131270866Simp VDDIO-supply = <®_3p3v>; 132270866Simp }; 133270866Simp}; 134270866Simp 135270866Simp&i2c2 { 136270866Simp clock-frequency = <100000>; 137270866Simp pinctrl-names = "default"; 138270866Simp pinctrl-0 = <&pinctrl_i2c2>; 139270866Simp status = "okay"; 140270866Simp 141270866Simp eeprom@57 { 142270866Simp compatible = "at,24c02"; 143270866Simp reg = <0x57>; 144270866Simp }; 145270866Simp}; 146270866Simp 147270866Simp&i2c3 { 148270866Simp clock-frequency = <100000>; 149270866Simp pinctrl-names = "default"; 150270866Simp pinctrl-0 = <&pinctrl_i2c3>; 151270866Simp status = "okay"; 152270866Simp}; 153270866Simp 154270866Simp&iomuxc { 155270866Simp pinctrl-names = "default"; 156270866Simp pinctrl-0 = <&pinctrl_hog>; 157270866Simp 158270866Simp imx6qdl-rex { 159270866Simp pinctrl_hog: hoggrp { 160270866Simp fsl,pins = < 161270866Simp /* SGTL5000 sys_mclk */ 162270866Simp MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 163270866Simp >; 164270866Simp }; 165270866Simp 166270866Simp pinctrl_audmux: audmuxgrp { 167270866Simp fsl,pins = < 168270866Simp MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 169270866Simp MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 170270866Simp MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 171270866Simp MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 172270866Simp >; 173270866Simp }; 174270866Simp 175270866Simp pinctrl_ecspi2: ecspi2grp { 176270866Simp fsl,pins = < 177270866Simp MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 178270866Simp MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 179270866Simp MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 180270866Simp /* CS */ 181270866Simp MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1 182270866Simp >; 183270866Simp }; 184270866Simp 185270866Simp pinctrl_ecspi3: ecspi3grp { 186270866Simp fsl,pins = < 187270866Simp MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 188270866Simp MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 189270866Simp MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 190270866Simp /* CS */ 191270866Simp MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 192270866Simp >; 193270866Simp }; 194270866Simp 195270866Simp pinctrl_enet: enetgrp { 196270866Simp fsl,pins = < 197270866Simp MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 198270866Simp MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 199270866Simp MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 200270866Simp MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 201270866Simp MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 202270866Simp MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 203270866Simp MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 204270866Simp MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 205270866Simp MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 206270866Simp MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 207270866Simp MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 208270866Simp MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 209270866Simp MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 210270866Simp MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 211270866Simp MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 212270866Simp MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 213270866Simp /* Phy reset */ 214270866Simp MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 215270866Simp >; 216270866Simp }; 217270866Simp 218270866Simp pinctrl_i2c1: i2c1grp { 219270866Simp fsl,pins = < 220270866Simp MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 221270866Simp MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 222270866Simp >; 223270866Simp }; 224270866Simp 225270866Simp pinctrl_i2c2: i2c2grp { 226270866Simp fsl,pins = < 227270866Simp MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 228270866Simp MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 229270866Simp >; 230270866Simp }; 231270866Simp 232270866Simp pinctrl_i2c3: i2c3grp { 233270866Simp fsl,pins = < 234270866Simp MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 235270866Simp MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 236270866Simp >; 237270866Simp }; 238270866Simp 239270866Simp pinctrl_led: ledgrp { 240270866Simp fsl,pins = < 241270866Simp /* user led */ 242270866Simp MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 243270866Simp >; 244270866Simp }; 245270866Simp 246270866Simp pinctrl_uart1: uart1grp { 247270866Simp fsl,pins = < 248270866Simp MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 249270866Simp MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 250270866Simp >; 251270866Simp }; 252270866Simp 253270866Simp pinctrl_uart2: uart2grp { 254270866Simp fsl,pins = < 255270866Simp MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 256270866Simp MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 257270866Simp >; 258270866Simp }; 259270866Simp 260270866Simp pinctrl_usbh1: usbh1grp { 261270866Simp fsl,pins = < 262270866Simp /* power enable, high active */ 263270866Simp MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0 264270866Simp >; 265270866Simp }; 266270866Simp 267270866Simp pinctrl_usbotg: usbotggrp { 268270866Simp fsl,pins = < 269270866Simp MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 270270866Simp MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 271270866Simp /* power enable, high active */ 272270866Simp MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0 273270866Simp >; 274270866Simp }; 275270866Simp 276270866Simp pinctrl_usdhc2: usdhc2grp { 277270866Simp fsl,pins = < 278270866Simp MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 279270866Simp MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 280270866Simp MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 281270866Simp MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 282270866Simp MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 283270866Simp MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 284270866Simp /* CD */ 285270866Simp MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 286270866Simp /* WP */ 287270866Simp MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0 288270866Simp >; 289270866Simp }; 290270866Simp 291270866Simp pinctrl_usdhc3: usdhc3grp { 292270866Simp fsl,pins = < 293270866Simp MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 294270866Simp MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 295270866Simp MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 296270866Simp MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 297270866Simp MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 298270866Simp MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 299270866Simp /* CD */ 300270866Simp MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 301270866Simp /* WP */ 302270866Simp MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0 303270866Simp >; 304270866Simp }; 305270866Simp }; 306270866Simp}; 307270866Simp 308270866Simp&ssi1 { 309270866Simp status = "okay"; 310270866Simp}; 311270866Simp 312270866Simp&uart1 { 313270866Simp pinctrl-names = "default"; 314270866Simp pinctrl-0 = <&pinctrl_uart1>; 315270866Simp status = "okay"; 316270866Simp}; 317270866Simp 318270866Simp&uart2 { 319270866Simp pinctrl-names = "default"; 320270866Simp pinctrl-0 = <&pinctrl_uart2>; 321270866Simp status = "okay"; 322270866Simp}; 323270866Simp 324270866Simp&usbh1 { 325270866Simp vbus-supply = <®_usbh1_vbus>; 326270866Simp pinctrl-names = "default"; 327270866Simp pinctrl-0 = <&pinctrl_usbh1>; 328270866Simp status = "okay"; 329270866Simp}; 330270866Simp 331270866Simp&usbotg { 332270866Simp vbus-supply = <®_usb_otg_vbus>; 333270866Simp pinctrl-names = "default"; 334270866Simp pinctrl-0 = <&pinctrl_usbotg>; 335270866Simp status = "okay"; 336270866Simp}; 337270866Simp 338270866Simp&usdhc2 { 339270866Simp pinctrl-names = "default"; 340270866Simp pinctrl-0 = <&pinctrl_usdhc2>; 341270866Simp bus-width = <4>; 342270866Simp cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 343295436Sandrew wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; 344270866Simp status = "okay"; 345270866Simp}; 346270866Simp 347270866Simp&usdhc3 { 348270866Simp pinctrl-names = "default"; 349270866Simp pinctrl-0 = <&pinctrl_usdhc3>; 350270866Simp bus-width = <4>; 351270866Simp cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 352295436Sandrew wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 353270866Simp status = "okay"; 354270866Simp}; 355