1/*
2 * Copyright 2014 FEDEVEL, Inc.
3 *
4 * Author: Robert Nelson <robertcnelson@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14
15/ {
16	chosen {
17		stdout-path = &uart1;
18	};
19
20	regulators {
21		compatible = "simple-bus";
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		reg_3p3v: regulator@0 {
26			compatible = "regulator-fixed";
27			reg = <0>;
28			regulator-name = "3P3V";
29			regulator-min-microvolt = <3300000>;
30			regulator-max-microvolt = <3300000>;
31			regulator-always-on;
32		};
33
34		reg_usbh1_vbus: regulator@1 {
35			compatible = "regulator-fixed";
36			reg = <1>;
37			pinctrl-names = "default";
38			regulator-name = "usbh1_vbus";
39			regulator-min-microvolt = <5000000>;
40			regulator-max-microvolt = <5000000>;
41			gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
42			enable-active-high;
43		};
44
45		reg_usb_otg_vbus: regulator@2 {
46			compatible = "regulator-fixed";
47			reg = <2>;
48			pinctrl-names = "default";
49			regulator-name = "usb_otg_vbus";
50			regulator-min-microvolt = <5000000>;
51			regulator-max-microvolt = <5000000>;
52			gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
53			enable-active-high;
54		};
55	};
56
57	leds {
58		compatible = "gpio-leds";
59		pinctrl-names = "default";
60		pinctrl-0 = <&pinctrl_led>;
61
62		led0: usr {
63			label = "usr";
64			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
65			default-state = "off";
66			linux,default-trigger = "heartbeat";
67		};
68	};
69
70	sound {
71		compatible = "fsl,imx6-rex-sgtl5000",
72			     "fsl,imx-audio-sgtl5000";
73		model = "imx6-rex-sgtl5000";
74		ssi-controller = <&ssi1>;
75		audio-codec = <&codec>;
76		audio-routing =
77			"MIC_IN", "Mic Jack",
78			"Mic Jack", "Mic Bias",
79			"Headphone Jack", "HP_OUT";
80		mux-int-port = <1>;
81		mux-ext-port = <3>;
82	};
83};
84
85&audmux {
86	pinctrl-names = "default";
87	pinctrl-0 = <&pinctrl_audmux>;
88	status = "okay";
89};
90
91&ecspi2 {
92	fsl,spi-num-chipselects = <1>;
93	cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
94	pinctrl-names = "default";
95	pinctrl-0 = <&pinctrl_ecspi2>;
96	status = "okay";
97};
98
99&ecspi3 {
100	fsl,spi-num-chipselects = <1>;
101	cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
102	pinctrl-names = "default";
103	pinctrl-0 = <&pinctrl_ecspi3>;
104	status = "okay";
105};
106
107&fec {
108	pinctrl-names = "default";
109	pinctrl-0 = <&pinctrl_enet>;
110	phy-mode = "rgmii";
111	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
112	status = "okay";
113};
114
115&hdmi {
116	ddc-i2c-bus = <&i2c2>;
117	status = "okay";
118};
119
120&i2c1 {
121	clock-frequency = <100000>;
122	pinctrl-names = "default";
123	pinctrl-0 = <&pinctrl_i2c1>;
124	status = "okay";
125
126	codec: sgtl5000@0a {
127		compatible = "fsl,sgtl5000";
128		reg = <0x0a>;
129		clocks = <&clks 201>;
130		VDDA-supply = <&reg_3p3v>;
131		VDDIO-supply = <&reg_3p3v>;
132	};
133};
134
135&i2c2 {
136	clock-frequency = <100000>;
137	pinctrl-names = "default";
138	pinctrl-0 = <&pinctrl_i2c2>;
139	status = "okay";
140
141	eeprom@57 {
142		compatible = "at,24c02";
143		reg = <0x57>;
144	};
145};
146
147&i2c3 {
148	clock-frequency = <100000>;
149	pinctrl-names = "default";
150	pinctrl-0 = <&pinctrl_i2c3>;
151	status = "okay";
152};
153
154&iomuxc {
155	pinctrl-names = "default";
156	pinctrl-0 = <&pinctrl_hog>;
157
158	imx6qdl-rex {
159		pinctrl_hog: hoggrp {
160			fsl,pins = <
161				/* SGTL5000 sys_mclk */
162				MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x030b0
163			>;
164		};
165
166		pinctrl_audmux: audmuxgrp {
167			fsl,pins = <
168				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
169				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
170				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
171				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
172			>;
173		};
174
175		pinctrl_ecspi2: ecspi2grp {
176			fsl,pins = <
177				MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
178				MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
179				MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
180				/* CS */
181				MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26	0x000b1
182			>;
183		};
184
185		pinctrl_ecspi3: ecspi3grp {
186			fsl,pins = <
187				MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO	0x100b1
188				MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI	0x100b1
189				MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK	0x100b1
190				/* CS */
191				MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12	0x000b1
192			>;
193		};
194
195		pinctrl_enet: enetgrp {
196			fsl,pins = <
197				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
198				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
199				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
200				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
201				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
202				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
203				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
204				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
205				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
206				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
207				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
208				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
209				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
210				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
211				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
212				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
213				/* Phy reset */
214				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x000b0
215			>;
216		};
217
218		pinctrl_i2c1: i2c1grp {
219			fsl,pins = <
220				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b8b1
221				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
222			>;
223		};
224
225		pinctrl_i2c2: i2c2grp {
226			fsl,pins = <
227				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
228				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
229			>;
230		};
231
232		pinctrl_i2c3: i2c3grp {
233			fsl,pins = <
234				MX6QDL_PAD_EIM_D17__I2C3_SCL		0x4001b8b1
235				MX6QDL_PAD_EIM_D18__I2C3_SDA		0x4001b8b1
236			>;
237		};
238
239		pinctrl_led: ledgrp {
240			fsl,pins = <
241				/* user led */
242				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x80000000
243			>;
244		};
245
246		pinctrl_uart1: uart1grp {
247			fsl,pins = <
248				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
249				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
250			>;
251		};
252
253		pinctrl_uart2: uart2grp {
254			fsl,pins = <
255				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
256				MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
257			>;
258		};
259
260		pinctrl_usbh1: usbh1grp {
261			fsl,pins = <
262				/* power enable, high active */
263				MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x10b0
264			>;
265		};
266
267		pinctrl_usbotg: usbotggrp {
268			fsl,pins = <
269				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
270				MX6QDL_PAD_EIM_D21__USB_OTG_OC		0x1b0b0
271				/* power enable, high active */
272				MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x10b0
273			>;
274		};
275
276		pinctrl_usdhc2: usdhc2grp {
277			fsl,pins = <
278				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
279				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
280				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
281				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
282				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
283				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
284				/* CD */
285				MX6QDL_PAD_NANDF_D2__GPIO2_IO02		0x1b0b0
286				/* WP */
287				MX6QDL_PAD_NANDF_D3__GPIO2_IO03		0x1f0b0
288			>;
289		};
290
291		pinctrl_usdhc3: usdhc3grp {
292			fsl,pins = <
293				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
294				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
295				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
296				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
297				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
298				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
299				/* CD */
300				MX6QDL_PAD_NANDF_D0__GPIO2_IO00		0x1b0b0
301				/* WP */
302				MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x1f0b0
303			>;
304		};
305	};
306};
307
308&ssi1 {
309	status = "okay";
310};
311
312&uart1 {
313	pinctrl-names = "default";
314	pinctrl-0 = <&pinctrl_uart1>;
315	status = "okay";
316};
317
318&uart2 {
319	pinctrl-names = "default";
320	pinctrl-0 = <&pinctrl_uart2>;
321	status = "okay";
322};
323
324&usbh1 {
325	vbus-supply = <&reg_usbh1_vbus>;
326	pinctrl-names = "default";
327	pinctrl-0 = <&pinctrl_usbh1>;
328	status = "okay";
329};
330
331&usbotg {
332	vbus-supply = <&reg_usb_otg_vbus>;
333	pinctrl-names = "default";
334	pinctrl-0 = <&pinctrl_usbotg>;
335	status = "okay";
336};
337
338&usdhc2 {
339	pinctrl-names = "default";
340	pinctrl-0 = <&pinctrl_usdhc2>;
341	bus-width = <4>;
342	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
343	wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
344	status = "okay";
345};
346
347&usdhc3 {
348	pinctrl-names = "default";
349	pinctrl-0 = <&pinctrl_usdhc3>;
350	bus-width = <4>;
351	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
352	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
353	status = "okay";
354};
355