1 2/* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 */ 10 11#include <dt-bindings/interrupt-controller/irq.h> 12#include "imx6q-pinfunc.h" 13#include "imx6qdl.dtsi" 14 15/ { 16 aliases { 17 ipu1 = &ipu2; 18 spi4 = &ecspi5; 19 }; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu@0 { 26 compatible = "arm,cortex-a9"; 27 device_type = "cpu"; 28 reg = <0>; 29 next-level-cache = <&L2>; 30 operating-points = < 31 /* kHz uV */ 32 1200000 1275000 33 996000 1250000 34 852000 1250000 35 792000 1175000 36 396000 975000 37 >; 38 fsl,soc-operating-points = < 39 /* ARM kHz SOC-PU uV */ 40 1200000 1275000 41 996000 1250000 42 852000 1250000 43 792000 1175000 44 396000 1175000 45 >; 46 clock-latency = <61036>; /* two CLK32 periods */ 47 clocks = <&clks IMX6QDL_CLK_ARM>, 48 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, 49 <&clks IMX6QDL_CLK_STEP>, 50 <&clks IMX6QDL_CLK_PLL1_SW>, 51 <&clks IMX6QDL_CLK_PLL1_SYS>; 52 clock-names = "arm", "pll2_pfd2_396m", "step", 53 "pll1_sw", "pll1_sys"; 54 arm-supply = <®_arm>; 55 pu-supply = <®_pu>; 56 soc-supply = <®_soc>; 57 }; 58 59 cpu@1 { 60 compatible = "arm,cortex-a9"; 61 device_type = "cpu"; 62 reg = <1>; 63 next-level-cache = <&L2>; 64 }; 65 66 cpu@2 { 67 compatible = "arm,cortex-a9"; 68 device_type = "cpu"; 69 reg = <2>; 70 next-level-cache = <&L2>; 71 }; 72 73 cpu@3 { 74 compatible = "arm,cortex-a9"; 75 device_type = "cpu"; 76 reg = <3>; 77 next-level-cache = <&L2>; 78 }; 79 }; 80 81 soc { 82 ocram: sram@00900000 { 83 compatible = "mmio-sram"; 84 reg = <0x00900000 0x40000>; 85 clocks = <&clks IMX6QDL_CLK_OCRAM>; 86 }; 87 88 aips-bus@02000000 { /* AIPS1 */ 89 spba-bus@02000000 { 90 ecspi5: ecspi@02018000 { 91 #address-cells = <1>; 92 #size-cells = <0>; 93 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 94 reg = <0x02018000 0x4000>; 95 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 96 clocks = <&clks IMX6Q_CLK_ECSPI5>, 97 <&clks IMX6Q_CLK_ECSPI5>; 98 clock-names = "ipg", "per"; 99 dmas = <&sdma 11 7 1>, <&sdma 12 7 2>; 100 dma-names = "rx", "tx"; 101 status = "disabled"; 102 }; 103 }; 104 105 iomuxc: iomuxc@020e0000 { 106 compatible = "fsl,imx6q-iomuxc"; 107 }; 108 }; 109 110 sata: sata@02200000 { 111 compatible = "fsl,imx6q-ahci"; 112 reg = <0x02200000 0x4000>; 113 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; 114 clocks = <&clks IMX6QDL_CLK_SATA>, 115 <&clks IMX6QDL_CLK_SATA_REF_100M>, 116 <&clks IMX6QDL_CLK_AHB>; 117 clock-names = "sata", "sata_ref", "ahb"; 118 status = "disabled"; 119 }; 120 121 gpu_vg: gpu@02204000 { 122 compatible = "vivante,gc"; 123 reg = <0x02204000 0x4000>; 124 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, 126 <&clks IMX6QDL_CLK_GPU2D_CORE>; 127 clock-names = "bus", "core"; 128 power-domains = <&gpc 1>; 129 }; 130 131 ipu2: ipu@02800000 { 132 #address-cells = <1>; 133 #size-cells = <0>; 134 compatible = "fsl,imx6q-ipu"; 135 reg = <0x02800000 0x400000>; 136 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, 137 <0 7 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&clks IMX6QDL_CLK_IPU2>, 139 <&clks IMX6QDL_CLK_IPU2_DI0>, 140 <&clks IMX6QDL_CLK_IPU2_DI1>; 141 clock-names = "bus", "di0", "di1"; 142 resets = <&src 4>; 143 144 ipu2_csi0: port@0 { 145 reg = <0>; 146 }; 147 148 ipu2_csi1: port@1 { 149 reg = <1>; 150 }; 151 152 ipu2_di0: port@2 { 153 #address-cells = <1>; 154 #size-cells = <0>; 155 reg = <2>; 156 157 ipu2_di0_disp0: endpoint@0 { 158 }; 159 160 ipu2_di0_hdmi: endpoint@1 { 161 remote-endpoint = <&hdmi_mux_2>; 162 }; 163 164 ipu2_di0_mipi: endpoint@2 { 165 }; 166 167 ipu2_di0_lvds0: endpoint@3 { 168 remote-endpoint = <&lvds0_mux_2>; 169 }; 170 171 ipu2_di0_lvds1: endpoint@4 { 172 remote-endpoint = <&lvds1_mux_2>; 173 }; 174 }; 175 176 ipu2_di1: port@3 { 177 #address-cells = <1>; 178 #size-cells = <0>; 179 reg = <3>; 180 181 ipu2_di1_hdmi: endpoint@1 { 182 remote-endpoint = <&hdmi_mux_3>; 183 }; 184 185 ipu2_di1_mipi: endpoint@2 { 186 }; 187 188 ipu2_di1_lvds0: endpoint@3 { 189 remote-endpoint = <&lvds0_mux_3>; 190 }; 191 192 ipu2_di1_lvds1: endpoint@4 { 193 remote-endpoint = <&lvds1_mux_3>; 194 }; 195 }; 196 }; 197 }; 198 199 display-subsystem { 200 compatible = "fsl,imx-display-subsystem"; 201 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; 202 }; 203 204 gpu-subsystem { 205 compatible = "fsl,imx-gpu-subsystem"; 206 cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>; 207 }; 208}; 209 210&hdmi { 211 compatible = "fsl,imx6q-hdmi"; 212 213 port@2 { 214 reg = <2>; 215 216 hdmi_mux_2: endpoint { 217 remote-endpoint = <&ipu2_di0_hdmi>; 218 }; 219 }; 220 221 port@3 { 222 reg = <3>; 223 224 hdmi_mux_3: endpoint { 225 remote-endpoint = <&ipu2_di1_hdmi>; 226 }; 227 }; 228}; 229 230&ldb { 231 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, 232 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, 233 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, 234 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; 235 clock-names = "di0_pll", "di1_pll", 236 "di0_sel", "di1_sel", "di2_sel", "di3_sel", 237 "di0", "di1"; 238 239 lvds-channel@0 { 240 port@2 { 241 reg = <2>; 242 243 lvds0_mux_2: endpoint { 244 remote-endpoint = <&ipu2_di0_lvds0>; 245 }; 246 }; 247 248 port@3 { 249 reg = <3>; 250 251 lvds0_mux_3: endpoint { 252 remote-endpoint = <&ipu2_di1_lvds0>; 253 }; 254 }; 255 }; 256 257 lvds-channel@1 { 258 port@2 { 259 reg = <2>; 260 261 lvds1_mux_2: endpoint { 262 remote-endpoint = <&ipu2_di0_lvds1>; 263 }; 264 }; 265 266 port@3 { 267 reg = <3>; 268 269 lvds1_mux_3: endpoint { 270 remote-endpoint = <&ipu2_di1_lvds1>; 271 }; 272 }; 273 }; 274}; 275 276&mipi_dsi { 277 ports { 278 port@2 { 279 reg = <2>; 280 281 mipi_mux_2: endpoint { 282 remote-endpoint = <&ipu2_di0_mipi>; 283 }; 284 }; 285 286 port@3 { 287 reg = <3>; 288 289 mipi_mux_3: endpoint { 290 remote-endpoint = <&ipu2_di1_mipi>; 291 }; 292 }; 293 }; 294}; 295 296&vpu { 297 compatible = "fsl,imx6q-vpu", "cnm,coda960"; 298}; 299