exynos4412.dtsi revision 295436
1279377Simp/* 2279377Simp * Samsung's Exynos4412 SoC device tree source 3279377Simp * 4279377Simp * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5279377Simp * http://www.samsung.com 6279377Simp * 7279377Simp * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 8279377Simp * based board files can include this file and provide values for board specfic 9279377Simp * bindings. 10279377Simp * 11279377Simp * Note: This file does not include device nodes for all the controllers in 12279377Simp * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional 13279377Simp * nodes can be added to this file. 14279377Simp * 15279377Simp * This program is free software; you can redistribute it and/or modify 16279377Simp * it under the terms of the GNU General Public License version 2 as 17279377Simp * published by the Free Software Foundation. 18279377Simp*/ 19279377Simp 20279377Simp#include "exynos4x12.dtsi" 21279377Simp 22279377Simp/ { 23279377Simp compatible = "samsung,exynos4412", "samsung,exynos4"; 24279377Simp 25279377Simp cpus { 26279377Simp #address-cells = <1>; 27279377Simp #size-cells = <0>; 28279377Simp 29295436Sandrew cpu0: cpu@A00 { 30279377Simp device_type = "cpu"; 31279377Simp compatible = "arm,cortex-a9"; 32279377Simp reg = <0xA00>; 33295436Sandrew clocks = <&clock CLK_ARM_CLK>; 34295436Sandrew clock-names = "cpu"; 35295436Sandrew operating-points-v2 = <&cpu0_opp_table>; 36295436Sandrew cooling-min-level = <13>; 37295436Sandrew cooling-max-level = <7>; 38295436Sandrew #cooling-cells = <2>; /* min followed by max */ 39279377Simp }; 40279377Simp 41279377Simp cpu@A01 { 42279377Simp device_type = "cpu"; 43279377Simp compatible = "arm,cortex-a9"; 44279377Simp reg = <0xA01>; 45295436Sandrew operating-points-v2 = <&cpu0_opp_table>; 46279377Simp }; 47279377Simp 48279377Simp cpu@A02 { 49279377Simp device_type = "cpu"; 50279377Simp compatible = "arm,cortex-a9"; 51279377Simp reg = <0xA02>; 52295436Sandrew operating-points-v2 = <&cpu0_opp_table>; 53279377Simp }; 54279377Simp 55279377Simp cpu@A03 { 56279377Simp device_type = "cpu"; 57279377Simp compatible = "arm,cortex-a9"; 58279377Simp reg = <0xA03>; 59295436Sandrew operating-points-v2 = <&cpu0_opp_table>; 60279377Simp }; 61279377Simp }; 62279377Simp 63295436Sandrew cpu0_opp_table: opp_table0 { 64295436Sandrew compatible = "operating-points-v2"; 65295436Sandrew opp-shared; 66295436Sandrew 67295436Sandrew opp@200000000 { 68295436Sandrew opp-hz = /bits/ 64 <200000000>; 69295436Sandrew opp-microvolt = <900000>; 70295436Sandrew clock-latency-ns = <200000>; 71295436Sandrew }; 72295436Sandrew opp@300000000 { 73295436Sandrew opp-hz = /bits/ 64 <300000000>; 74295436Sandrew opp-microvolt = <900000>; 75295436Sandrew clock-latency-ns = <200000>; 76295436Sandrew }; 77295436Sandrew opp@400000000 { 78295436Sandrew opp-hz = /bits/ 64 <400000000>; 79295436Sandrew opp-microvolt = <925000>; 80295436Sandrew clock-latency-ns = <200000>; 81295436Sandrew }; 82295436Sandrew opp@500000000 { 83295436Sandrew opp-hz = /bits/ 64 <500000000>; 84295436Sandrew opp-microvolt = <950000>; 85295436Sandrew clock-latency-ns = <200000>; 86295436Sandrew }; 87295436Sandrew opp@600000000 { 88295436Sandrew opp-hz = /bits/ 64 <600000000>; 89295436Sandrew opp-microvolt = <975000>; 90295436Sandrew clock-latency-ns = <200000>; 91295436Sandrew }; 92295436Sandrew opp@700000000 { 93295436Sandrew opp-hz = /bits/ 64 <700000000>; 94295436Sandrew opp-microvolt = <987500>; 95295436Sandrew clock-latency-ns = <200000>; 96295436Sandrew }; 97295436Sandrew opp@800000000 { 98295436Sandrew opp-hz = /bits/ 64 <800000000>; 99295436Sandrew opp-microvolt = <1000000>; 100295436Sandrew clock-latency-ns = <200000>; 101295436Sandrew opp-suspend; 102295436Sandrew }; 103295436Sandrew opp@900000000 { 104295436Sandrew opp-hz = /bits/ 64 <900000000>; 105295436Sandrew opp-microvolt = <1037500>; 106295436Sandrew clock-latency-ns = <200000>; 107295436Sandrew }; 108295436Sandrew opp@1000000000 { 109295436Sandrew opp-hz = /bits/ 64 <1000000000>; 110295436Sandrew opp-microvolt = <1087500>; 111295436Sandrew clock-latency-ns = <200000>; 112295436Sandrew }; 113295436Sandrew opp@1100000000 { 114295436Sandrew opp-hz = /bits/ 64 <1100000000>; 115295436Sandrew opp-microvolt = <1137500>; 116295436Sandrew clock-latency-ns = <200000>; 117295436Sandrew }; 118295436Sandrew opp@1200000000 { 119295436Sandrew opp-hz = /bits/ 64 <1200000000>; 120295436Sandrew opp-microvolt = <1187500>; 121295436Sandrew clock-latency-ns = <200000>; 122295436Sandrew }; 123295436Sandrew opp@1300000000 { 124295436Sandrew opp-hz = /bits/ 64 <1300000000>; 125295436Sandrew opp-microvolt = <1250000>; 126295436Sandrew clock-latency-ns = <200000>; 127295436Sandrew }; 128295436Sandrew opp@1400000000 { 129295436Sandrew opp-hz = /bits/ 64 <1400000000>; 130295436Sandrew opp-microvolt = <1287500>; 131295436Sandrew clock-latency-ns = <200000>; 132295436Sandrew }; 133295436Sandrew opp@1500000000 { 134295436Sandrew opp-hz = /bits/ 64 <1500000000>; 135295436Sandrew opp-microvolt = <1350000>; 136295436Sandrew clock-latency-ns = <200000>; 137295436Sandrew turbo-mode; 138295436Sandrew }; 139279377Simp }; 140279377Simp 141279377Simp pmu { 142279377Simp interrupts = <2 2>, <3 2>, <18 2>, <19 2>; 143279377Simp }; 144295436Sandrew}; 145279377Simp 146295436Sandrew&pmu_system_controller { 147295436Sandrew compatible = "samsung,exynos4412-pmu", "syscon"; 148295436Sandrew}; 149279377Simp 150295436Sandrew&combiner { 151295436Sandrew samsung,combiner-nr = <20>; 152279377Simp}; 153295436Sandrew 154295436Sandrew&gic { 155295436Sandrew cpu-offset = <0x4000>; 156295436Sandrew}; 157