exynos4412.dtsi revision 295436
1272343Sngie/* 2272343Sngie * Samsung's Exynos4412 SoC device tree source 3272343Sngie * 4272343Sngie * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5272343Sngie * http://www.samsung.com 6272343Sngie * 7272343Sngie * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 8272343Sngie * based board files can include this file and provide values for board specfic 9272343Sngie * bindings. 10272343Sngie * 11272343Sngie * Note: This file does not include device nodes for all the controllers in 12272343Sngie * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional 13272343Sngie * nodes can be added to this file. 14272343Sngie * 15272343Sngie * This program is free software; you can redistribute it and/or modify 16272343Sngie * it under the terms of the GNU General Public License version 2 as 17272343Sngie * published by the Free Software Foundation. 18272343Sngie*/ 19272343Sngie 20272343Sngie#include "exynos4x12.dtsi" 21272343Sngie 22272343Sngie/ { 23272343Sngie compatible = "samsung,exynos4412", "samsung,exynos4"; 24272343Sngie 25272343Sngie cpus { 26272343Sngie #address-cells = <1>; 27272343Sngie #size-cells = <0>; 28272343Sngie 29272343Sngie cpu0: cpu@A00 { 30272343Sngie device_type = "cpu"; 31272343Sngie compatible = "arm,cortex-a9"; 32272343Sngie reg = <0xA00>; 33272343Sngie clocks = <&clock CLK_ARM_CLK>; 34272343Sngie clock-names = "cpu"; 35272343Sngie operating-points-v2 = <&cpu0_opp_table>; 36272343Sngie cooling-min-level = <13>; 37272343Sngie cooling-max-level = <7>; 38272343Sngie #cooling-cells = <2>; /* min followed by max */ 39272343Sngie }; 40272343Sngie 41272343Sngie cpu@A01 { 42272343Sngie device_type = "cpu"; 43272343Sngie compatible = "arm,cortex-a9"; 44272343Sngie reg = <0xA01>; 45272343Sngie operating-points-v2 = <&cpu0_opp_table>; 46272343Sngie }; 47272343Sngie 48272343Sngie cpu@A02 { 49272343Sngie device_type = "cpu"; 50272343Sngie compatible = "arm,cortex-a9"; 51272343Sngie reg = <0xA02>; 52272343Sngie operating-points-v2 = <&cpu0_opp_table>; 53272343Sngie }; 54272343Sngie 55272343Sngie cpu@A03 { 56272343Sngie device_type = "cpu"; 57272343Sngie compatible = "arm,cortex-a9"; 58272343Sngie reg = <0xA03>; 59272343Sngie operating-points-v2 = <&cpu0_opp_table>; 60272343Sngie }; 61272343Sngie }; 62272343Sngie 63272343Sngie cpu0_opp_table: opp_table0 { 64272343Sngie compatible = "operating-points-v2"; 65272343Sngie opp-shared; 66272343Sngie 67272343Sngie opp@200000000 { 68272343Sngie opp-hz = /bits/ 64 <200000000>; 69272343Sngie opp-microvolt = <900000>; 70272343Sngie clock-latency-ns = <200000>; 71272343Sngie }; 72272343Sngie opp@300000000 { 73272343Sngie opp-hz = /bits/ 64 <300000000>; 74272343Sngie opp-microvolt = <900000>; 75272343Sngie clock-latency-ns = <200000>; 76272343Sngie }; 77272343Sngie opp@400000000 { 78272343Sngie opp-hz = /bits/ 64 <400000000>; 79272343Sngie opp-microvolt = <925000>; 80272343Sngie clock-latency-ns = <200000>; 81272343Sngie }; 82272343Sngie opp@500000000 { 83272343Sngie opp-hz = /bits/ 64 <500000000>; 84 opp-microvolt = <950000>; 85 clock-latency-ns = <200000>; 86 }; 87 opp@600000000 { 88 opp-hz = /bits/ 64 <600000000>; 89 opp-microvolt = <975000>; 90 clock-latency-ns = <200000>; 91 }; 92 opp@700000000 { 93 opp-hz = /bits/ 64 <700000000>; 94 opp-microvolt = <987500>; 95 clock-latency-ns = <200000>; 96 }; 97 opp@800000000 { 98 opp-hz = /bits/ 64 <800000000>; 99 opp-microvolt = <1000000>; 100 clock-latency-ns = <200000>; 101 opp-suspend; 102 }; 103 opp@900000000 { 104 opp-hz = /bits/ 64 <900000000>; 105 opp-microvolt = <1037500>; 106 clock-latency-ns = <200000>; 107 }; 108 opp@1000000000 { 109 opp-hz = /bits/ 64 <1000000000>; 110 opp-microvolt = <1087500>; 111 clock-latency-ns = <200000>; 112 }; 113 opp@1100000000 { 114 opp-hz = /bits/ 64 <1100000000>; 115 opp-microvolt = <1137500>; 116 clock-latency-ns = <200000>; 117 }; 118 opp@1200000000 { 119 opp-hz = /bits/ 64 <1200000000>; 120 opp-microvolt = <1187500>; 121 clock-latency-ns = <200000>; 122 }; 123 opp@1300000000 { 124 opp-hz = /bits/ 64 <1300000000>; 125 opp-microvolt = <1250000>; 126 clock-latency-ns = <200000>; 127 }; 128 opp@1400000000 { 129 opp-hz = /bits/ 64 <1400000000>; 130 opp-microvolt = <1287500>; 131 clock-latency-ns = <200000>; 132 }; 133 opp@1500000000 { 134 opp-hz = /bits/ 64 <1500000000>; 135 opp-microvolt = <1350000>; 136 clock-latency-ns = <200000>; 137 turbo-mode; 138 }; 139 }; 140 141 pmu { 142 interrupts = <2 2>, <3 2>, <18 2>, <19 2>; 143 }; 144}; 145 146&pmu_system_controller { 147 compatible = "samsung,exynos4412-pmu", "syscon"; 148}; 149 150&combiner { 151 samsung,combiner-nr = <20>; 152}; 153 154&gic { 155 cpu-offset = <0x4000>; 156}; 157