exynos4210.dtsi revision 279377
1279377Simp/* 2279377Simp * Samsung's Exynos4210 SoC device tree source 3279377Simp * 4279377Simp * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 5279377Simp * http://www.samsung.com 6279377Simp * Copyright (c) 2010-2011 Linaro Ltd. 7279377Simp * www.linaro.org 8279377Simp * 9279377Simp * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 10279377Simp * based board files can include this file and provide values for board specfic 11279377Simp * bindings. 12279377Simp * 13279377Simp * Note: This file does not include device nodes for all the controllers in 14279377Simp * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional 15279377Simp * nodes can be added to this file. 16279377Simp * 17279377Simp * This program is free software; you can redistribute it and/or modify 18279377Simp * it under the terms of the GNU General Public License version 2 as 19279377Simp * published by the Free Software Foundation. 20279377Simp*/ 21279377Simp 22279377Simp#include "exynos4.dtsi" 23279377Simp#include "exynos4210-pinctrl.dtsi" 24279377Simp 25279377Simp/ { 26279377Simp compatible = "samsung,exynos4210", "samsung,exynos4"; 27279377Simp 28279377Simp aliases { 29279377Simp pinctrl0 = &pinctrl_0; 30279377Simp pinctrl1 = &pinctrl_1; 31279377Simp pinctrl2 = &pinctrl_2; 32279377Simp }; 33279377Simp 34279377Simp cpus { 35279377Simp #address-cells = <1>; 36279377Simp #size-cells = <0>; 37279377Simp 38279377Simp cpu@900 { 39279377Simp device_type = "cpu"; 40279377Simp compatible = "arm,cortex-a9"; 41279377Simp reg = <0x900>; 42279377Simp }; 43279377Simp 44279377Simp cpu@901 { 45279377Simp device_type = "cpu"; 46279377Simp compatible = "arm,cortex-a9"; 47279377Simp reg = <0x901>; 48279377Simp }; 49279377Simp }; 50279377Simp 51279377Simp pmu_system_controller: system-controller@10020000 { 52279377Simp clock-names = "clkout0", "clkout1", "clkout2", "clkout3", 53279377Simp "clkout4", "clkout8", "clkout9"; 54279377Simp clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, 55279377Simp <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, 56279377Simp <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, 57279377Simp <&clock CLK_XUSBXTI>; 58279377Simp #clock-cells = <1>; 59279377Simp }; 60279377Simp 61279377Simp sysram@02020000 { 62279377Simp compatible = "mmio-sram"; 63279377Simp reg = <0x02020000 0x20000>; 64279377Simp #address-cells = <1>; 65279377Simp #size-cells = <1>; 66279377Simp ranges = <0 0x02020000 0x20000>; 67279377Simp 68279377Simp smp-sysram@0 { 69279377Simp compatible = "samsung,exynos4210-sysram"; 70279377Simp reg = <0x0 0x1000>; 71279377Simp }; 72279377Simp 73279377Simp smp-sysram@1f000 { 74279377Simp compatible = "samsung,exynos4210-sysram-ns"; 75279377Simp reg = <0x1f000 0x1000>; 76279377Simp }; 77279377Simp }; 78279377Simp 79279377Simp pd_lcd1: lcd1-power-domain@10023CA0 { 80279377Simp compatible = "samsung,exynos4210-pd"; 81279377Simp reg = <0x10023CA0 0x20>; 82279377Simp #power-domain-cells = <0>; 83279377Simp }; 84279377Simp 85279377Simp l2c: l2-cache-controller@10502000 { 86279377Simp compatible = "arm,pl310-cache"; 87279377Simp reg = <0x10502000 0x1000>; 88279377Simp cache-unified; 89279377Simp cache-level = <2>; 90279377Simp arm,tag-latency = <2 2 1>; 91279377Simp arm,data-latency = <2 2 1>; 92279377Simp }; 93279377Simp 94279377Simp gic: interrupt-controller@10490000 { 95279377Simp cpu-offset = <0x8000>; 96279377Simp }; 97279377Simp 98279377Simp combiner: interrupt-controller@10440000 { 99279377Simp samsung,combiner-nr = <16>; 100279377Simp interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, 101279377Simp <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, 102279377Simp <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, 103279377Simp <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; 104279377Simp }; 105279377Simp 106279377Simp mct@10050000 { 107279377Simp compatible = "samsung,exynos4210-mct"; 108279377Simp reg = <0x10050000 0x800>; 109279377Simp interrupt-parent = <&mct_map>; 110279377Simp interrupts = <0>, <1>, <2>, <3>, <4>, <5>; 111279377Simp clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 112279377Simp clock-names = "fin_pll", "mct"; 113279377Simp 114279377Simp mct_map: mct-map { 115279377Simp #interrupt-cells = <1>; 116279377Simp #address-cells = <0>; 117279377Simp #size-cells = <0>; 118279377Simp interrupt-map = <0 &gic 0 57 0>, 119279377Simp <1 &gic 0 69 0>, 120279377Simp <2 &combiner 12 6>, 121279377Simp <3 &combiner 12 7>, 122279377Simp <4 &gic 0 42 0>, 123279377Simp <5 &gic 0 48 0>; 124279377Simp }; 125279377Simp }; 126279377Simp 127279377Simp clock: clock-controller@10030000 { 128279377Simp compatible = "samsung,exynos4210-clock"; 129279377Simp reg = <0x10030000 0x20000>; 130279377Simp #clock-cells = <1>; 131279377Simp }; 132279377Simp 133279377Simp pinctrl_0: pinctrl@11400000 { 134279377Simp compatible = "samsung,exynos4210-pinctrl"; 135279377Simp reg = <0x11400000 0x1000>; 136279377Simp interrupts = <0 47 0>; 137279377Simp }; 138279377Simp 139279377Simp pinctrl_1: pinctrl@11000000 { 140279377Simp compatible = "samsung,exynos4210-pinctrl"; 141279377Simp reg = <0x11000000 0x1000>; 142279377Simp interrupts = <0 46 0>; 143279377Simp 144279377Simp wakup_eint: wakeup-interrupt-controller { 145279377Simp compatible = "samsung,exynos4210-wakeup-eint"; 146279377Simp interrupt-parent = <&gic>; 147279377Simp interrupts = <0 32 0>; 148279377Simp }; 149279377Simp }; 150279377Simp 151279377Simp pinctrl_2: pinctrl@03860000 { 152279377Simp compatible = "samsung,exynos4210-pinctrl"; 153279377Simp reg = <0x03860000 0x1000>; 154279377Simp }; 155279377Simp 156279377Simp tmu@100C0000 { 157279377Simp compatible = "samsung,exynos4210-tmu"; 158279377Simp interrupt-parent = <&combiner>; 159279377Simp reg = <0x100C0000 0x100>; 160279377Simp interrupts = <2 4>; 161279377Simp clocks = <&clock CLK_TMU_APBIF>; 162279377Simp clock-names = "tmu_apbif"; 163279377Simp status = "disabled"; 164279377Simp }; 165279377Simp 166279377Simp g2d@12800000 { 167279377Simp compatible = "samsung,s5pv210-g2d"; 168279377Simp reg = <0x12800000 0x1000>; 169279377Simp interrupts = <0 89 0>; 170279377Simp clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; 171279377Simp clock-names = "sclk_fimg2d", "fimg2d"; 172279377Simp status = "disabled"; 173279377Simp }; 174279377Simp 175279377Simp camera { 176279377Simp clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, 177279377Simp <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; 178279377Simp clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 179279377Simp 180279377Simp fimc_0: fimc@11800000 { 181279377Simp samsung,pix-limits = <4224 8192 1920 4224>; 182279377Simp samsung,mainscaler-ext; 183279377Simp samsung,cam-if; 184279377Simp }; 185279377Simp 186279377Simp fimc_1: fimc@11810000 { 187279377Simp samsung,pix-limits = <4224 8192 1920 4224>; 188279377Simp samsung,mainscaler-ext; 189279377Simp samsung,cam-if; 190279377Simp }; 191279377Simp 192279377Simp fimc_2: fimc@11820000 { 193279377Simp samsung,pix-limits = <4224 8192 1920 4224>; 194279377Simp samsung,mainscaler-ext; 195279377Simp samsung,lcd-wb; 196279377Simp }; 197279377Simp 198279377Simp fimc_3: fimc@11830000 { 199279377Simp samsung,pix-limits = <1920 8192 1366 1920>; 200279377Simp samsung,rotators = <0>; 201279377Simp samsung,mainscaler-ext; 202279377Simp samsung,lcd-wb; 203279377Simp }; 204279377Simp }; 205279377Simp 206279377Simp ppmu_lcd1: ppmu_lcd1@12240000 { 207279377Simp compatible = "samsung,exynos-ppmu"; 208279377Simp reg = <0x12240000 0x2000>; 209279377Simp clocks = <&clock CLK_PPMULCD1>; 210279377Simp clock-names = "ppmu"; 211279377Simp status = "disabled"; 212279377Simp }; 213279377Simp}; 214