1/*
2 * Samsung's Exynos4210 SoC device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 *		http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 *		www.linaro.org
8 *
9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
10 * based board files can include this file and provide values for board specfic
11 * bindings.
12 *
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
15 * nodes can be added to this file.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20*/
21
22#include "exynos4.dtsi"
23#include "exynos4210-pinctrl.dtsi"
24#include "exynos4-cpu-thermal.dtsi"
25
26/ {
27	compatible = "samsung,exynos4210", "samsung,exynos4";
28
29	aliases {
30		pinctrl0 = &pinctrl_0;
31		pinctrl1 = &pinctrl_1;
32		pinctrl2 = &pinctrl_2;
33	};
34
35	cpus {
36		#address-cells = <1>;
37		#size-cells = <0>;
38
39		cpu0: cpu@900 {
40			device_type = "cpu";
41			compatible = "arm,cortex-a9";
42			reg = <0x900>;
43			clocks = <&clock CLK_ARM_CLK>;
44			clock-names = "cpu";
45			clock-latency = <160000>;
46
47			operating-points = <
48				1200000 1250000
49				1000000 1150000
50				800000	1075000
51				500000	975000
52				400000	975000
53				200000	950000
54			>;
55			cooling-min-level = <4>;
56			cooling-max-level = <2>;
57			#cooling-cells = <2>; /* min followed by max */
58		};
59
60		cpu@901 {
61			device_type = "cpu";
62			compatible = "arm,cortex-a9";
63			reg = <0x901>;
64		};
65	};
66
67	sysram: sysram@02020000 {
68		compatible = "mmio-sram";
69		reg = <0x02020000 0x20000>;
70		#address-cells = <1>;
71		#size-cells = <1>;
72		ranges = <0 0x02020000 0x20000>;
73
74		smp-sysram@0 {
75			compatible = "samsung,exynos4210-sysram";
76			reg = <0x0 0x1000>;
77		};
78
79		smp-sysram@1f000 {
80			compatible = "samsung,exynos4210-sysram-ns";
81			reg = <0x1f000 0x1000>;
82		};
83	};
84
85	pd_lcd1: lcd1-power-domain@10023CA0 {
86		compatible = "samsung,exynos4210-pd";
87		reg = <0x10023CA0 0x20>;
88		#power-domain-cells = <0>;
89	};
90
91	l2c: l2-cache-controller@10502000 {
92		compatible = "arm,pl310-cache";
93		reg = <0x10502000 0x1000>;
94		cache-unified;
95		cache-level = <2>;
96		arm,tag-latency = <2 2 1>;
97		arm,data-latency = <2 2 1>;
98	};
99
100	mct: mct@10050000 {
101		compatible = "samsung,exynos4210-mct";
102		reg = <0x10050000 0x800>;
103		interrupt-parent = <&mct_map>;
104		interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
105		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
106		clock-names = "fin_pll", "mct";
107
108		mct_map: mct-map {
109			#interrupt-cells = <1>;
110			#address-cells = <0>;
111			#size-cells = <0>;
112			interrupt-map = <0 &gic 0 57 0>,
113					<1 &gic 0 69 0>,
114					<2 &combiner 12 6>,
115					<3 &combiner 12 7>,
116					<4 &gic 0 42 0>,
117					<5 &gic 0 48 0>;
118		};
119	};
120
121	clock: clock-controller@10030000 {
122		compatible = "samsung,exynos4210-clock";
123		reg = <0x10030000 0x20000>;
124		#clock-cells = <1>;
125	};
126
127	pinctrl_0: pinctrl@11400000 {
128		compatible = "samsung,exynos4210-pinctrl";
129		reg = <0x11400000 0x1000>;
130		interrupts = <0 47 0>;
131	};
132
133	pinctrl_1: pinctrl@11000000 {
134		compatible = "samsung,exynos4210-pinctrl";
135		reg = <0x11000000 0x1000>;
136		interrupts = <0 46 0>;
137
138		wakup_eint: wakeup-interrupt-controller {
139			compatible = "samsung,exynos4210-wakeup-eint";
140			interrupt-parent = <&gic>;
141			interrupts = <0 32 0>;
142		};
143	};
144
145	pinctrl_2: pinctrl@03860000 {
146		compatible = "samsung,exynos4210-pinctrl";
147		reg = <0x03860000 0x1000>;
148	};
149
150	tmu: tmu@100C0000 {
151		compatible = "samsung,exynos4210-tmu";
152		interrupt-parent = <&combiner>;
153		reg = <0x100C0000 0x100>;
154		interrupts = <2 4>;
155		clocks = <&clock CLK_TMU_APBIF>;
156		clock-names = "tmu_apbif";
157		samsung,tmu_gain = <15>;
158		samsung,tmu_reference_voltage = <7>;
159		status = "disabled";
160	};
161
162	thermal-zones {
163		cpu_thermal: cpu-thermal {
164			polling-delay-passive = <0>;
165			polling-delay = <0>;
166			thermal-sensors = <&tmu 0>;
167
168			trips {
169			      cpu_alert0: cpu-alert-0 {
170				      temperature = <85000>; /* millicelsius */
171			      };
172			      cpu_alert1: cpu-alert-1 {
173				      temperature = <100000>; /* millicelsius */
174			      };
175			      cpu_alert2: cpu-alert-2 {
176				      temperature = <110000>; /* millicelsius */
177			      };
178			};
179		};
180	};
181
182	g2d: g2d@12800000 {
183		compatible = "samsung,s5pv210-g2d";
184		reg = <0x12800000 0x1000>;
185		interrupts = <0 89 0>;
186		clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
187		clock-names = "sclk_fimg2d", "fimg2d";
188		power-domains = <&pd_lcd0>;
189		iommus = <&sysmmu_g2d>;
190	};
191
192	camera {
193		clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
194			 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
195		clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
196
197		fimc_0: fimc@11800000 {
198			samsung,pix-limits = <4224 8192 1920 4224>;
199			samsung,mainscaler-ext;
200			samsung,cam-if;
201		};
202
203		fimc_1: fimc@11810000 {
204			samsung,pix-limits = <4224 8192 1920 4224>;
205			samsung,mainscaler-ext;
206			samsung,cam-if;
207		};
208
209		fimc_2: fimc@11820000 {
210			samsung,pix-limits = <4224 8192 1920 4224>;
211			samsung,mainscaler-ext;
212			samsung,lcd-wb;
213		};
214
215		fimc_3: fimc@11830000 {
216			samsung,pix-limits = <1920 8192 1366 1920>;
217			samsung,rotators = <0>;
218			samsung,mainscaler-ext;
219			samsung,lcd-wb;
220		};
221	};
222
223	mixer: mixer@12C10000 {
224		clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
225			"sclk_mixer";
226		clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
227			<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
228			<&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
229	};
230
231	ppmu_lcd1: ppmu_lcd1@12240000 {
232		compatible = "samsung,exynos-ppmu";
233		reg = <0x12240000 0x2000>;
234		clocks = <&clock CLK_PPMULCD1>;
235		clock-names = "ppmu";
236		status = "disabled";
237	};
238
239	sysmmu_g2d: sysmmu@12A20000 {
240		compatible = "samsung,exynos-sysmmu";
241		reg = <0x12A20000 0x1000>;
242		interrupt-parent = <&combiner>;
243		interrupts = <4 7>;
244		clock-names = "sysmmu", "master";
245		clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
246		power-domains = <&pd_lcd0>;
247		#iommu-cells = <0>;
248	};
249
250	sysmmu_fimd1: sysmmu@12220000 {
251		compatible = "samsung,exynos-sysmmu";
252		interrupt-parent = <&combiner>;
253		reg = <0x12220000 0x1000>;
254		interrupts = <5 3>;
255		clock-names = "sysmmu", "master";
256		clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
257		power-domains = <&pd_lcd1>;
258		#iommu-cells = <0>;
259	};
260};
261
262&gic {
263	cpu-offset = <0x8000>;
264};
265
266&combiner {
267	samsung,combiner-nr = <16>;
268	interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
269		     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
270		     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
271		     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
272};
273
274&mdma1 {
275	power-domains = <&pd_lcd0>;
276};
277
278&pmu_system_controller {
279	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
280			"clkout4", "clkout8", "clkout9";
281	clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
282		<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
283		<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
284	#clock-cells = <1>;
285};
286
287&rotator {
288	power-domains = <&pd_lcd0>;
289};
290
291&sysmmu_rotator {
292	power-domains = <&pd_lcd0>;
293};
294