1279377Simp/* 2279377Simp * Samsung's Exynos4210 SoC device tree source 3279377Simp * 4279377Simp * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 5279377Simp * http://www.samsung.com 6279377Simp * Copyright (c) 2010-2011 Linaro Ltd. 7279377Simp * www.linaro.org 8279377Simp * 9279377Simp * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 10279377Simp * based board files can include this file and provide values for board specfic 11279377Simp * bindings. 12279377Simp * 13279377Simp * Note: This file does not include device nodes for all the controllers in 14279377Simp * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional 15279377Simp * nodes can be added to this file. 16279377Simp * 17279377Simp * This program is free software; you can redistribute it and/or modify 18279377Simp * it under the terms of the GNU General Public License version 2 as 19279377Simp * published by the Free Software Foundation. 20279377Simp*/ 21279377Simp 22279377Simp#include "exynos4.dtsi" 23279377Simp#include "exynos4210-pinctrl.dtsi" 24295436Sandrew#include "exynos4-cpu-thermal.dtsi" 25279377Simp 26279377Simp/ { 27279377Simp compatible = "samsung,exynos4210", "samsung,exynos4"; 28279377Simp 29279377Simp aliases { 30279377Simp pinctrl0 = &pinctrl_0; 31279377Simp pinctrl1 = &pinctrl_1; 32279377Simp pinctrl2 = &pinctrl_2; 33279377Simp }; 34279377Simp 35279377Simp cpus { 36279377Simp #address-cells = <1>; 37279377Simp #size-cells = <0>; 38279377Simp 39295436Sandrew cpu0: cpu@900 { 40279377Simp device_type = "cpu"; 41279377Simp compatible = "arm,cortex-a9"; 42279377Simp reg = <0x900>; 43295436Sandrew clocks = <&clock CLK_ARM_CLK>; 44295436Sandrew clock-names = "cpu"; 45295436Sandrew clock-latency = <160000>; 46295436Sandrew 47295436Sandrew operating-points = < 48295436Sandrew 1200000 1250000 49295436Sandrew 1000000 1150000 50295436Sandrew 800000 1075000 51295436Sandrew 500000 975000 52295436Sandrew 400000 975000 53295436Sandrew 200000 950000 54295436Sandrew >; 55295436Sandrew cooling-min-level = <4>; 56295436Sandrew cooling-max-level = <2>; 57295436Sandrew #cooling-cells = <2>; /* min followed by max */ 58279377Simp }; 59279377Simp 60279377Simp cpu@901 { 61279377Simp device_type = "cpu"; 62279377Simp compatible = "arm,cortex-a9"; 63279377Simp reg = <0x901>; 64279377Simp }; 65279377Simp }; 66279377Simp 67295436Sandrew sysram: sysram@02020000 { 68279377Simp compatible = "mmio-sram"; 69279377Simp reg = <0x02020000 0x20000>; 70279377Simp #address-cells = <1>; 71279377Simp #size-cells = <1>; 72279377Simp ranges = <0 0x02020000 0x20000>; 73279377Simp 74279377Simp smp-sysram@0 { 75279377Simp compatible = "samsung,exynos4210-sysram"; 76279377Simp reg = <0x0 0x1000>; 77279377Simp }; 78279377Simp 79279377Simp smp-sysram@1f000 { 80279377Simp compatible = "samsung,exynos4210-sysram-ns"; 81279377Simp reg = <0x1f000 0x1000>; 82279377Simp }; 83279377Simp }; 84279377Simp 85279377Simp pd_lcd1: lcd1-power-domain@10023CA0 { 86279377Simp compatible = "samsung,exynos4210-pd"; 87279377Simp reg = <0x10023CA0 0x20>; 88279377Simp #power-domain-cells = <0>; 89279377Simp }; 90279377Simp 91279377Simp l2c: l2-cache-controller@10502000 { 92279377Simp compatible = "arm,pl310-cache"; 93279377Simp reg = <0x10502000 0x1000>; 94279377Simp cache-unified; 95279377Simp cache-level = <2>; 96279377Simp arm,tag-latency = <2 2 1>; 97279377Simp arm,data-latency = <2 2 1>; 98279377Simp }; 99279377Simp 100295436Sandrew mct: mct@10050000 { 101279377Simp compatible = "samsung,exynos4210-mct"; 102279377Simp reg = <0x10050000 0x800>; 103279377Simp interrupt-parent = <&mct_map>; 104279377Simp interrupts = <0>, <1>, <2>, <3>, <4>, <5>; 105279377Simp clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 106279377Simp clock-names = "fin_pll", "mct"; 107279377Simp 108279377Simp mct_map: mct-map { 109279377Simp #interrupt-cells = <1>; 110279377Simp #address-cells = <0>; 111279377Simp #size-cells = <0>; 112279377Simp interrupt-map = <0 &gic 0 57 0>, 113279377Simp <1 &gic 0 69 0>, 114279377Simp <2 &combiner 12 6>, 115279377Simp <3 &combiner 12 7>, 116279377Simp <4 &gic 0 42 0>, 117279377Simp <5 &gic 0 48 0>; 118279377Simp }; 119279377Simp }; 120279377Simp 121279377Simp clock: clock-controller@10030000 { 122279377Simp compatible = "samsung,exynos4210-clock"; 123279377Simp reg = <0x10030000 0x20000>; 124279377Simp #clock-cells = <1>; 125279377Simp }; 126279377Simp 127279377Simp pinctrl_0: pinctrl@11400000 { 128279377Simp compatible = "samsung,exynos4210-pinctrl"; 129279377Simp reg = <0x11400000 0x1000>; 130279377Simp interrupts = <0 47 0>; 131279377Simp }; 132279377Simp 133279377Simp pinctrl_1: pinctrl@11000000 { 134279377Simp compatible = "samsung,exynos4210-pinctrl"; 135279377Simp reg = <0x11000000 0x1000>; 136279377Simp interrupts = <0 46 0>; 137279377Simp 138279377Simp wakup_eint: wakeup-interrupt-controller { 139279377Simp compatible = "samsung,exynos4210-wakeup-eint"; 140279377Simp interrupt-parent = <&gic>; 141279377Simp interrupts = <0 32 0>; 142279377Simp }; 143279377Simp }; 144279377Simp 145279377Simp pinctrl_2: pinctrl@03860000 { 146279377Simp compatible = "samsung,exynos4210-pinctrl"; 147279377Simp reg = <0x03860000 0x1000>; 148279377Simp }; 149279377Simp 150295436Sandrew tmu: tmu@100C0000 { 151279377Simp compatible = "samsung,exynos4210-tmu"; 152279377Simp interrupt-parent = <&combiner>; 153279377Simp reg = <0x100C0000 0x100>; 154279377Simp interrupts = <2 4>; 155279377Simp clocks = <&clock CLK_TMU_APBIF>; 156279377Simp clock-names = "tmu_apbif"; 157295436Sandrew samsung,tmu_gain = <15>; 158295436Sandrew samsung,tmu_reference_voltage = <7>; 159279377Simp status = "disabled"; 160279377Simp }; 161279377Simp 162295436Sandrew thermal-zones { 163295436Sandrew cpu_thermal: cpu-thermal { 164295436Sandrew polling-delay-passive = <0>; 165295436Sandrew polling-delay = <0>; 166295436Sandrew thermal-sensors = <&tmu 0>; 167295436Sandrew 168295436Sandrew trips { 169295436Sandrew cpu_alert0: cpu-alert-0 { 170295436Sandrew temperature = <85000>; /* millicelsius */ 171295436Sandrew }; 172295436Sandrew cpu_alert1: cpu-alert-1 { 173295436Sandrew temperature = <100000>; /* millicelsius */ 174295436Sandrew }; 175295436Sandrew cpu_alert2: cpu-alert-2 { 176295436Sandrew temperature = <110000>; /* millicelsius */ 177295436Sandrew }; 178295436Sandrew }; 179295436Sandrew }; 180295436Sandrew }; 181295436Sandrew 182295436Sandrew g2d: g2d@12800000 { 183279377Simp compatible = "samsung,s5pv210-g2d"; 184279377Simp reg = <0x12800000 0x1000>; 185279377Simp interrupts = <0 89 0>; 186279377Simp clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; 187279377Simp clock-names = "sclk_fimg2d", "fimg2d"; 188295436Sandrew power-domains = <&pd_lcd0>; 189295436Sandrew iommus = <&sysmmu_g2d>; 190279377Simp }; 191279377Simp 192279377Simp camera { 193279377Simp clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, 194279377Simp <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; 195279377Simp clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 196279377Simp 197279377Simp fimc_0: fimc@11800000 { 198279377Simp samsung,pix-limits = <4224 8192 1920 4224>; 199279377Simp samsung,mainscaler-ext; 200279377Simp samsung,cam-if; 201279377Simp }; 202279377Simp 203279377Simp fimc_1: fimc@11810000 { 204279377Simp samsung,pix-limits = <4224 8192 1920 4224>; 205279377Simp samsung,mainscaler-ext; 206279377Simp samsung,cam-if; 207279377Simp }; 208279377Simp 209279377Simp fimc_2: fimc@11820000 { 210279377Simp samsung,pix-limits = <4224 8192 1920 4224>; 211279377Simp samsung,mainscaler-ext; 212279377Simp samsung,lcd-wb; 213279377Simp }; 214279377Simp 215279377Simp fimc_3: fimc@11830000 { 216279377Simp samsung,pix-limits = <1920 8192 1366 1920>; 217279377Simp samsung,rotators = <0>; 218279377Simp samsung,mainscaler-ext; 219279377Simp samsung,lcd-wb; 220279377Simp }; 221279377Simp }; 222279377Simp 223295436Sandrew mixer: mixer@12C10000 { 224295436Sandrew clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer", 225295436Sandrew "sclk_mixer"; 226295436Sandrew clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 227295436Sandrew <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>, 228295436Sandrew <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>; 229295436Sandrew }; 230295436Sandrew 231279377Simp ppmu_lcd1: ppmu_lcd1@12240000 { 232279377Simp compatible = "samsung,exynos-ppmu"; 233279377Simp reg = <0x12240000 0x2000>; 234279377Simp clocks = <&clock CLK_PPMULCD1>; 235279377Simp clock-names = "ppmu"; 236279377Simp status = "disabled"; 237279377Simp }; 238295436Sandrew 239295436Sandrew sysmmu_g2d: sysmmu@12A20000 { 240295436Sandrew compatible = "samsung,exynos-sysmmu"; 241295436Sandrew reg = <0x12A20000 0x1000>; 242295436Sandrew interrupt-parent = <&combiner>; 243295436Sandrew interrupts = <4 7>; 244295436Sandrew clock-names = "sysmmu", "master"; 245295436Sandrew clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 246295436Sandrew power-domains = <&pd_lcd0>; 247295436Sandrew #iommu-cells = <0>; 248295436Sandrew }; 249295436Sandrew 250295436Sandrew sysmmu_fimd1: sysmmu@12220000 { 251295436Sandrew compatible = "samsung,exynos-sysmmu"; 252295436Sandrew interrupt-parent = <&combiner>; 253295436Sandrew reg = <0x12220000 0x1000>; 254295436Sandrew interrupts = <5 3>; 255295436Sandrew clock-names = "sysmmu", "master"; 256295436Sandrew clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; 257295436Sandrew power-domains = <&pd_lcd1>; 258295436Sandrew #iommu-cells = <0>; 259295436Sandrew }; 260279377Simp}; 261295436Sandrew 262295436Sandrew&gic { 263295436Sandrew cpu-offset = <0x8000>; 264295436Sandrew}; 265295436Sandrew 266295436Sandrew&combiner { 267295436Sandrew samsung,combiner-nr = <16>; 268295436Sandrew interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, 269295436Sandrew <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, 270295436Sandrew <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, 271295436Sandrew <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; 272295436Sandrew}; 273295436Sandrew 274295436Sandrew&mdma1 { 275295436Sandrew power-domains = <&pd_lcd0>; 276295436Sandrew}; 277295436Sandrew 278295436Sandrew&pmu_system_controller { 279295436Sandrew clock-names = "clkout0", "clkout1", "clkout2", "clkout3", 280295436Sandrew "clkout4", "clkout8", "clkout9"; 281295436Sandrew clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, 282295436Sandrew <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, 283295436Sandrew <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; 284295436Sandrew #clock-cells = <1>; 285295436Sandrew}; 286295436Sandrew 287295436Sandrew&rotator { 288295436Sandrew power-domains = <&pd_lcd0>; 289295436Sandrew}; 290295436Sandrew 291295436Sandrew&sysmmu_rotator { 292295436Sandrew power-domains = <&pd_lcd0>; 293295436Sandrew}; 294