1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 */
6
7&pllss_clocks {
8	timer1_fck: timer1_fck {
9		#clock-cells = <0>;
10		compatible = "ti,mux-clock";
11		clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
12			  &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
13		ti,bit-shift = <3>;
14		reg = <0x2e0>;
15	};
16
17	timer2_fck: timer2_fck {
18		#clock-cells = <0>;
19		compatible = "ti,mux-clock";
20		clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
21			  &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
22		ti,bit-shift = <6>;
23		reg = <0x2e0>;
24	};
25
26	sysclk18_ck: sysclk18_ck {
27		#clock-cells = <0>;
28		compatible = "ti,mux-clock";
29		clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
30		ti,bit-shift = <0>;
31		reg = <0x02f0>;
32	};
33};
34
35&scm_clocks {
36	devosc_ck: devosc_ck {
37		#clock-cells = <0>;
38		compatible = "ti,mux-clock";
39		clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
40		ti,bit-shift = <21>;
41		reg = <0x0040>;
42	};
43
44	/* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */
45	auxosc_ck: auxosc_ck {
46		#clock-cells = <0>;
47		compatible = "fixed-clock";
48		clock-frequency = <27000000>;
49	};
50
51	/* Optional 32768Hz crystal or clock on RTCOSC pins */
52	rtcosc_ck: rtcosc_ck {
53		#clock-cells = <0>;
54		compatible = "fixed-clock";
55		clock-frequency = <32768>;
56	};
57
58	/* Optional external clock on TCLKIN pin, set rate in baord dts file */
59	tclkin_ck: tclkin_ck {
60		#clock-cells = <0>;
61		compatible = "fixed-clock";
62		clock-frequency = <0>;
63	};
64
65	virt_20000000_ck: virt_20000000_ck {
66		#clock-cells = <0>;
67		compatible = "fixed-clock";
68		clock-frequency = <20000000>;
69	};
70
71	virt_19200000_ck: virt_19200000_ck {
72		#clock-cells = <0>;
73		compatible = "fixed-clock";
74		clock-frequency = <19200000>;
75	};
76
77	mpu_ck: mpu_ck {
78		#clock-cells = <0>;
79		compatible = "fixed-clock";
80		clock-frequency = <1000000000>;
81	};
82
83	sysclk4_ck: sysclk4_ck {
84		#clock-cells = <0>;
85		compatible = "fixed-clock";
86		clock-frequency = <222000000>;
87	};
88
89	sysclk6_ck: sysclk6_ck {
90		#clock-cells = <0>;
91		compatible = "fixed-clock";
92		clock-frequency = <100000000>;
93	};
94
95	sysclk10_ck: sysclk10_ck {
96		#clock-cells = <0>;
97		compatible = "fixed-clock";
98		clock-frequency = <48000000>;
99	};
100
101        cpsw_125mhz_gclk: cpsw_125mhz_gclk {
102		#clock-cells = <0>;
103		compatible = "fixed-clock";
104		clock-frequency = <125000000>;
105	};
106
107	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
108		#clock-cells = <0>;
109		compatible = "fixed-clock";
110		clock-frequency = <250000000>;
111	};
112
113};
114
115&prcm_clocks {
116	osc_src_ck: osc_src_ck {
117		#clock-cells = <0>;
118		compatible = "fixed-factor-clock";
119		clocks = <&devosc_ck>;
120		clock-mult = <1>;
121		clock-div = <1>;
122	};
123
124	mpu_clksrc_ck: mpu_clksrc_ck {
125		#clock-cells = <0>;
126		compatible = "ti,mux-clock";
127		clocks = <&devosc_ck>, <&rtcdivider_ck>;
128		ti,bit-shift = <0>;
129		reg = <0x0040>;
130	};
131
132	/* Fixed divider clock 0.0016384 * devosc */
133	rtcdivider_ck: rtcdivider_ck {
134		#clock-cells = <0>;
135		compatible = "fixed-factor-clock";
136		clocks = <&devosc_ck>;
137		clock-mult = <128>;
138		clock-div = <78125>;
139	};
140
141	aud_clkin0_ck: aud_clkin0_ck {
142		#clock-cells = <0>;
143		compatible = "fixed-clock";
144		clock-frequency = <20000000>;
145	};
146
147	aud_clkin1_ck: aud_clkin1_ck {
148		#clock-cells = <0>;
149		compatible = "fixed-clock";
150		clock-frequency = <20000000>;
151	};
152
153	aud_clkin2_ck: aud_clkin2_ck {
154		#clock-cells = <0>;
155		compatible = "fixed-clock";
156		clock-frequency = <20000000>;
157	};
158};
159