1295011Sandrew/* 2295011Sandrew * Copyright 2015 Linaro Ltd 3295011Sandrew * 4295011Sandrew * Permission is hereby granted, free of charge, to any person obtaining a copy 5295011Sandrew * of this software and associated documentation files (the "Software"), to deal 6295011Sandrew * in the Software without restriction, including without limitation the rights 7295011Sandrew * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8295011Sandrew * copies of the Software, and to permit persons to whom the Software is 9295011Sandrew * furnished to do so, subject to the following conditions: 10295011Sandrew * 11295011Sandrew * The above copyright notice and this permission notice shall be included in 12295011Sandrew * all copies or substantial portions of the Software. 13295011Sandrew * 14295011Sandrew * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15295011Sandrew * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16295011Sandrew * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17295011Sandrew * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18295011Sandrew * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19295011Sandrew * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20295011Sandrew * THE SOFTWARE. 21295011Sandrew */ 22295011Sandrew 23295011Sandrew/dts-v1/; 24295011Sandrew#include <dt-bindings/interrupt-controller/irq.h> 25295011Sandrew#include <dt-bindings/gpio/gpio.h> 26295011Sandrew#include "skeleton.dtsi" 27295011Sandrew 28295011Sandrew/ { 29295011Sandrew model = "ARM RealView PB11MPcore"; 30295011Sandrew compatible = "arm,realview-pb11mp"; 31295011Sandrew 32295011Sandrew chosen { }; 33295011Sandrew 34295011Sandrew aliases { 35295011Sandrew serial0 = &pb11mp_serial0; 36295011Sandrew serial1 = &pb11mp_serial1; 37295011Sandrew serial2 = &pb11mp_serial2; 38295011Sandrew serial3 = &pb11mp_serial3; 39295011Sandrew }; 40295011Sandrew 41295011Sandrew memory { 42295011Sandrew /* 43295011Sandrew * The PB11MPCore has 512 MiB memory @ 0x70000000 44295011Sandrew * and the first 256 are also remapped @ 0x00000000 45295011Sandrew */ 46295011Sandrew reg = <0x70000000 0x20000000>; 47295011Sandrew }; 48295011Sandrew 49295011Sandrew cpus { 50295011Sandrew #address-cells = <1>; 51295011Sandrew #size-cells = <0>; 52295011Sandrew enable-method = "arm,realview-smp"; 53295011Sandrew 54295011Sandrew MP11_0: cpu@0 { 55295011Sandrew device_type = "cpu"; 56295011Sandrew compatible = "arm,arm11mpcore"; 57295011Sandrew reg = <0>; 58295011Sandrew next-level-cache = <&L2>; 59295011Sandrew }; 60295011Sandrew 61295011Sandrew MP11_1: cpu@1 { 62295011Sandrew device_type = "cpu"; 63295011Sandrew compatible = "arm,arm11mpcore"; 64295011Sandrew reg = <1>; 65295011Sandrew next-level-cache = <&L2>; 66295011Sandrew }; 67295011Sandrew 68295011Sandrew MP11_2: cpu@2 { 69295011Sandrew device_type = "cpu"; 70295011Sandrew compatible = "arm,arm11mpcore"; 71295011Sandrew reg = <2>; 72295011Sandrew next-level-cache = <&L2>; 73295011Sandrew }; 74295011Sandrew 75295011Sandrew MP11_3: cpu@3 { 76295011Sandrew device_type = "cpu"; 77295011Sandrew compatible = "arm,arm11mpcore"; 78295011Sandrew reg = <3>; 79295011Sandrew next-level-cache = <&L2>; 80295011Sandrew }; 81295011Sandrew }; 82295011Sandrew 83295011Sandrew /* Primary TestChip GIC synthesized with the CPU */ 84295011Sandrew intc_tc11mp: interrupt-controller@1f000100 { 85295011Sandrew compatible = "arm,tc11mp-gic"; 86295011Sandrew #interrupt-cells = <3>; 87295011Sandrew #address-cells = <1>; 88295011Sandrew interrupt-controller; 89295011Sandrew reg = <0x1f001000 0x1000>, 90295011Sandrew <0x1f000100 0x100>; 91295011Sandrew }; 92295011Sandrew 93295011Sandrew L2: l2-cache { 94295011Sandrew compatible = "arm,l220-cache"; 95295011Sandrew reg = <0x1f002000 0x1000>; 96295011Sandrew interrupt-parent = <&intc_tc11mp>; 97295011Sandrew interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, 98295011Sandrew <0 30 IRQ_TYPE_LEVEL_HIGH>, 99295011Sandrew <0 31 IRQ_TYPE_LEVEL_HIGH>; 100295011Sandrew cache-unified; 101295011Sandrew cache-level = <2>; 102295011Sandrew /* 103295011Sandrew * Override default cache size, sets and 104295011Sandrew * associativity as these may be erroneously set 105295011Sandrew * up by boot loader(s), probably for safety 106295011Sandrew * since th outer sync operation can cause the 107295011Sandrew * cache to hang unless disabled. 108295011Sandrew */ 109295011Sandrew cache-size = <1048576>; // 1MB 110295011Sandrew cache-sets = <4096>; 111295011Sandrew cache-line-size = <32>; 112295011Sandrew arm,shared-override; 113295011Sandrew arm,parity-enable; 114295011Sandrew arm,outer-sync-disable; 115295011Sandrew }; 116295011Sandrew 117295011Sandrew scu@1f000000 { 118295011Sandrew compatible = "arm,arm11mp-scu"; 119295011Sandrew reg = <0x1f000000 0x100>; 120295011Sandrew }; 121295011Sandrew 122295011Sandrew timer@1f000600 { 123295011Sandrew compatible = "arm,arm11mp-twd-timer"; 124295011Sandrew reg = <0x1f000600 0x20>; 125295011Sandrew interrupt-parent = <&intc_tc11mp>; 126295011Sandrew interrupts = <1 13 0xf04>; 127295011Sandrew }; 128295011Sandrew 129295011Sandrew watchdog@1f000620 { 130295011Sandrew compatible = "arm,arm11mp-twd-wdt"; 131295011Sandrew reg = <0x1f000620 0x20>; 132295011Sandrew interrupt-parent = <&intc_tc11mp>; 133295011Sandrew interrupts = <1 14 0xf04>; 134295011Sandrew }; 135295011Sandrew 136295011Sandrew /* PMU with one IRQ line per core */ 137295011Sandrew pmu { 138295011Sandrew compatible = "arm,arm11mpcore-pmu"; 139295011Sandrew interrupt-parent = <&intc_tc11mp>; 140295011Sandrew interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, 141295011Sandrew <0 18 IRQ_TYPE_LEVEL_HIGH>, 142295011Sandrew <0 19 IRQ_TYPE_LEVEL_HIGH>, 143295011Sandrew <0 20 IRQ_TYPE_LEVEL_HIGH>; 144295011Sandrew interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>; 145295011Sandrew }; 146295011Sandrew 147295011Sandrew /* The voltage to the MMC card is hardwired at 3.3V */ 148295011Sandrew vmmc: fixedregulator@0 { 149295011Sandrew compatible = "regulator-fixed"; 150295011Sandrew regulator-name = "vmmc"; 151295011Sandrew regulator-min-microvolt = <3300000>; 152295011Sandrew regulator-max-microvolt = <3300000>; 153295011Sandrew regulator-boot-on; 154295011Sandrew }; 155295011Sandrew 156295011Sandrew veth: fixedregulator@0 { 157295011Sandrew compatible = "regulator-fixed"; 158295011Sandrew regulator-name = "veth"; 159295011Sandrew regulator-min-microvolt = <3300000>; 160295011Sandrew regulator-max-microvolt = <3300000>; 161295011Sandrew regulator-boot-on; 162295011Sandrew }; 163295011Sandrew 164295011Sandrew xtal24mhz: xtal24mhz@24M { 165295011Sandrew #clock-cells = <0>; 166295011Sandrew compatible = "fixed-clock"; 167295011Sandrew clock-frequency = <24000000>; 168295011Sandrew }; 169295011Sandrew 170295011Sandrew refclk32khz: refclk32khz { 171295011Sandrew compatible = "fixed-clock"; 172295011Sandrew #clock-cells = <0>; 173295011Sandrew clock-frequency = <32768>; 174295011Sandrew }; 175295011Sandrew 176295011Sandrew timclk: timclk@1M { 177295011Sandrew #clock-cells = <0>; 178295011Sandrew compatible = "fixed-factor-clock"; 179295011Sandrew clock-div = <24>; 180295011Sandrew clock-mult = <1>; 181295011Sandrew clocks = <&xtal24mhz>; 182295011Sandrew }; 183295011Sandrew 184295011Sandrew mclk: mclk@24M { 185295011Sandrew #clock-cells = <0>; 186295011Sandrew compatible = "fixed-factor-clock"; 187295011Sandrew clock-div = <1>; 188295011Sandrew clock-mult = <1>; 189295011Sandrew clocks = <&xtal24mhz>; 190295011Sandrew }; 191295011Sandrew 192295011Sandrew kmiclk: kmiclk@24M { 193295011Sandrew #clock-cells = <0>; 194295011Sandrew compatible = "fixed-factor-clock"; 195295011Sandrew clock-div = <1>; 196295011Sandrew clock-mult = <1>; 197295011Sandrew clocks = <&xtal24mhz>; 198295011Sandrew }; 199295011Sandrew 200295011Sandrew sspclk: sspclk@24M { 201295011Sandrew #clock-cells = <0>; 202295011Sandrew compatible = "fixed-factor-clock"; 203295011Sandrew clock-div = <1>; 204295011Sandrew clock-mult = <1>; 205295011Sandrew clocks = <&xtal24mhz>; 206295011Sandrew }; 207295011Sandrew 208295011Sandrew uartclk: uartclk@24M { 209295011Sandrew #clock-cells = <0>; 210295011Sandrew compatible = "fixed-factor-clock"; 211295011Sandrew clock-div = <1>; 212295011Sandrew clock-mult = <1>; 213295011Sandrew clocks = <&xtal24mhz>; 214295011Sandrew }; 215295011Sandrew 216295011Sandrew wdogclk: wdogclk@24M { 217295011Sandrew #clock-cells = <0>; 218295011Sandrew compatible = "fixed-factor-clock"; 219295011Sandrew clock-div = <1>; 220295011Sandrew clock-mult = <1>; 221295011Sandrew clocks = <&xtal24mhz>; 222295011Sandrew }; 223295011Sandrew 224295011Sandrew /* FIXME: this actually hangs off the PLL clocks */ 225295011Sandrew pclk: pclk@0 { 226295011Sandrew #clock-cells = <0>; 227295011Sandrew compatible = "fixed-clock"; 228295011Sandrew clock-frequency = <0>; 229295011Sandrew }; 230295011Sandrew 231295011Sandrew flash0@40000000 { 232295011Sandrew /* 2 * 32MiB NOR Flash memory */ 233295011Sandrew compatible = "arm,vexpress-flash", "cfi-flash"; 234295011Sandrew reg = <0x40000000 0x04000000>; 235295011Sandrew bank-width = <4>; 236295011Sandrew }; 237295011Sandrew 238295011Sandrew flash1@44000000 { 239295011Sandrew // 2 * 32MiB NOR Flash memory 240295011Sandrew compatible = "arm,vexpress-flash", "cfi-flash"; 241295011Sandrew reg = <0x44000000 0x04000000>; 242295011Sandrew bank-width = <4>; 243295011Sandrew }; 244295011Sandrew 245295011Sandrew soc { 246295011Sandrew #address-cells = <1>; 247295011Sandrew #size-cells = <1>; 248295011Sandrew compatible = "arm,realview-pb11mp-soc", "simple-bus"; 249295011Sandrew regmap = <&pb11mp_syscon>; 250295011Sandrew ranges; 251295011Sandrew 252295011Sandrew pb11mp_syscon: syscon@10000000 { 253295011Sandrew compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd"; 254295011Sandrew reg = <0x10000000 0x1000>; 255295011Sandrew 256295011Sandrew led@08.0 { 257295011Sandrew compatible = "register-bit-led"; 258295011Sandrew offset = <0x08>; 259295011Sandrew mask = <0x01>; 260295011Sandrew label = "versatile:0"; 261295011Sandrew linux,default-trigger = "heartbeat"; 262295011Sandrew default-state = "on"; 263295011Sandrew }; 264295011Sandrew led@08.1 { 265295011Sandrew compatible = "register-bit-led"; 266295011Sandrew offset = <0x08>; 267295011Sandrew mask = <0x02>; 268295011Sandrew label = "versatile:1"; 269295011Sandrew linux,default-trigger = "mmc0"; 270295011Sandrew default-state = "off"; 271295011Sandrew }; 272295011Sandrew led@08.2 { 273295011Sandrew compatible = "register-bit-led"; 274295011Sandrew offset = <0x08>; 275295011Sandrew mask = <0x04>; 276295011Sandrew label = "versatile:2"; 277295011Sandrew linux,default-trigger = "cpu0"; 278295011Sandrew default-state = "off"; 279295011Sandrew }; 280295011Sandrew led@08.3 { 281295011Sandrew compatible = "register-bit-led"; 282295011Sandrew offset = <0x08>; 283295011Sandrew mask = <0x08>; 284295011Sandrew label = "versatile:3"; 285295011Sandrew linux,default-trigger = "cpu1"; 286295011Sandrew default-state = "off"; 287295011Sandrew }; 288295011Sandrew led@08.4 { 289295011Sandrew compatible = "register-bit-led"; 290295011Sandrew offset = <0x08>; 291295011Sandrew mask = <0x10>; 292295011Sandrew label = "versatile:4"; 293295011Sandrew linux,default-trigger = "cpu2"; 294295011Sandrew default-state = "off"; 295295011Sandrew }; 296295011Sandrew led@08.5 { 297295011Sandrew compatible = "register-bit-led"; 298295011Sandrew offset = <0x08>; 299295011Sandrew mask = <0x20>; 300295011Sandrew label = "versatile:5"; 301295011Sandrew linux,default-trigger = "cpu3"; 302295011Sandrew default-state = "off"; 303295011Sandrew }; 304295011Sandrew led@08.6 { 305295011Sandrew compatible = "register-bit-led"; 306295011Sandrew offset = <0x08>; 307295011Sandrew mask = <0x40>; 308295011Sandrew label = "versatile:6"; 309295011Sandrew default-state = "off"; 310295011Sandrew }; 311295011Sandrew led@08.7 { 312295011Sandrew compatible = "register-bit-led"; 313295011Sandrew offset = <0x08>; 314295011Sandrew mask = <0x80>; 315295011Sandrew label = "versatile:7"; 316295011Sandrew default-state = "off"; 317295011Sandrew }; 318295011Sandrew 319295011Sandrew oscclk0: osc0@0c { 320295011Sandrew compatible = "arm,syscon-icst307"; 321295011Sandrew #clock-cells = <0>; 322295011Sandrew lock-offset = <0x20>; 323295011Sandrew vco-offset = <0x0C>; 324295011Sandrew clocks = <&xtal24mhz>; 325295011Sandrew }; 326295011Sandrew oscclk1: osc1@10 { 327295011Sandrew compatible = "arm,syscon-icst307"; 328295011Sandrew #clock-cells = <0>; 329295011Sandrew lock-offset = <0x20>; 330295011Sandrew vco-offset = <0x10>; 331295011Sandrew clocks = <&xtal24mhz>; 332295011Sandrew }; 333295011Sandrew oscclk2: osc2@14 { 334295011Sandrew compatible = "arm,syscon-icst307"; 335295011Sandrew #clock-cells = <0>; 336295011Sandrew lock-offset = <0x20>; 337295011Sandrew vco-offset = <0x14>; 338295011Sandrew clocks = <&xtal24mhz>; 339295011Sandrew }; 340295011Sandrew oscclk3: osc3@18 { 341295011Sandrew compatible = "arm,syscon-icst307"; 342295011Sandrew #clock-cells = <0>; 343295011Sandrew lock-offset = <0x20>; 344295011Sandrew vco-offset = <0x18>; 345295011Sandrew clocks = <&xtal24mhz>; 346295011Sandrew }; 347295011Sandrew oscclk4: osc4@1c { 348295011Sandrew compatible = "arm,syscon-icst307"; 349295011Sandrew #clock-cells = <0>; 350295011Sandrew lock-offset = <0x20>; 351295011Sandrew vco-offset = <0x1c>; 352295011Sandrew clocks = <&xtal24mhz>; 353295011Sandrew }; 354295011Sandrew oscclk5: osc5@d4 { 355295011Sandrew compatible = "arm,syscon-icst307"; 356295011Sandrew #clock-cells = <0>; 357295011Sandrew lock-offset = <0x20>; 358295011Sandrew vco-offset = <0xd4>; 359295011Sandrew clocks = <&xtal24mhz>; 360295011Sandrew }; 361295011Sandrew oscclk6: osc6@d8 { 362295011Sandrew compatible = "arm,syscon-icst307"; 363295011Sandrew #clock-cells = <0>; 364295011Sandrew lock-offset = <0x20>; 365295011Sandrew vco-offset = <0xd8>; 366295011Sandrew clocks = <&xtal24mhz>; 367295011Sandrew }; 368295011Sandrew }; 369295011Sandrew 370295011Sandrew sp810_syscon: sysctl@10001000 { 371295011Sandrew compatible = "arm,sp810", "arm,primecell"; 372295011Sandrew reg = <0x10001000 0x1000>; 373295011Sandrew clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; 374295011Sandrew clock-names = "refclk", "timclk", "apb_pclk"; 375295011Sandrew #clock-cells = <1>; 376295011Sandrew clock-output-names = "timerclk0", 377295011Sandrew "timerclk1", 378295011Sandrew "timerclk2", 379295011Sandrew "timerclk3"; 380295011Sandrew assigned-clocks = <&sp810_syscon 0>, 381295011Sandrew <&sp810_syscon 1>, 382295011Sandrew <&sp810_syscon 2>, 383295011Sandrew <&sp810_syscon 3>; 384295011Sandrew assigned-clock-parents = <&timclk>, 385295011Sandrew <&timclk>, 386295011Sandrew <&timclk>, 387295011Sandrew <&timclk>; 388295011Sandrew }; 389295011Sandrew 390295011Sandrew i2c0: i2c@10002000 { 391295011Sandrew #address-cells = <1>; 392295011Sandrew #size-cells = <0>; 393295011Sandrew compatible = "arm,versatile-i2c"; 394295011Sandrew reg = <0x10002000 0x1000>; 395295011Sandrew 396295011Sandrew rtc@68 { 397295011Sandrew compatible = "dallas,ds1338"; 398295011Sandrew reg = <0x68>; 399295011Sandrew }; 400295011Sandrew }; 401295011Sandrew 402295011Sandrew aaci: aaci@10004000 { 403295011Sandrew compatible = "arm,pl041", "arm,primecell"; 404295011Sandrew reg = <0x10004000 0x1000>; 405295011Sandrew interrupt-parent = <&intc_tc11mp>; 406295011Sandrew interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 407295011Sandrew clocks = <&pclk>; 408295011Sandrew clock-names = "apb_pclk"; 409295011Sandrew }; 410295011Sandrew 411295011Sandrew mci: mmcsd@10005000 { 412295011Sandrew compatible = "arm,pl18x", "arm,primecell"; 413295011Sandrew reg = <0x10005000 0x1000>; 414295011Sandrew interrupt-parent = <&intc_tc11mp>; 415295011Sandrew interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, 416295011Sandrew <0 15 IRQ_TYPE_LEVEL_HIGH>; 417295011Sandrew /* Due to frequent FIFO overruns, use just 500 kHz */ 418295011Sandrew max-frequency = <500000>; 419295011Sandrew bus-width = <4>; 420295011Sandrew cap-sd-highspeed; 421295011Sandrew cap-mmc-highspeed; 422295011Sandrew clocks = <&mclk>, <&pclk>; 423295011Sandrew clock-names = "mclk", "apb_pclk"; 424295011Sandrew vmmc-supply = <&vmmc>; 425295011Sandrew cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 426295011Sandrew wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 427295011Sandrew }; 428295011Sandrew 429295011Sandrew kmi0: kmi@10006000 { 430295011Sandrew compatible = "arm,pl050", "arm,primecell"; 431295011Sandrew reg = <0x10006000 0x1000>; 432295011Sandrew interrupt-parent = <&intc_tc11mp>; 433295011Sandrew interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 434295011Sandrew clocks = <&kmiclk>, <&pclk>; 435295011Sandrew clock-names = "KMIREFCLK", "apb_pclk"; 436295011Sandrew }; 437295011Sandrew 438295011Sandrew kmi1: kmi@10007000 { 439295011Sandrew compatible = "arm,pl050", "arm,primecell"; 440295011Sandrew reg = <0x10007000 0x1000>; 441295011Sandrew interrupt-parent = <&intc_tc11mp>; 442295011Sandrew interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 443295011Sandrew clocks = <&kmiclk>, <&pclk>; 444295011Sandrew clock-names = "KMIREFCLK", "apb_pclk"; 445295011Sandrew }; 446295011Sandrew 447295011Sandrew pb11mp_serial0: serial@10009000 { 448295011Sandrew compatible = "arm,pl011", "arm,primecell"; 449295011Sandrew reg = <0x10009000 0x1000>; 450295011Sandrew interrupt-parent = <&intc_tc11mp>; 451295011Sandrew interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 452295011Sandrew clocks = <&uartclk>, <&pclk>; 453295011Sandrew clock-names = "uartclk", "apb_pclk"; 454295011Sandrew }; 455295011Sandrew 456295011Sandrew pb11mp_serial1: serial@1000a000 { 457295011Sandrew compatible = "arm,pl011", "arm,primecell"; 458295011Sandrew reg = <0x1000a000 0x1000>; 459295011Sandrew interrupt-parent = <&intc_tc11mp>; 460295011Sandrew interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; 461295011Sandrew clocks = <&uartclk>, <&pclk>; 462295011Sandrew clock-names = "uartclk", "apb_pclk"; 463295011Sandrew }; 464295011Sandrew 465295011Sandrew pb11mp_serial2: serial@1000b000 { 466295011Sandrew compatible = "arm,pl011", "arm,primecell"; 467295011Sandrew reg = <0x1000b000 0x1000>; 468295011Sandrew interrupt-parent = <&intc_pb11mp>; 469295011Sandrew interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 470295011Sandrew clocks = <&uartclk>, <&pclk>; 471295011Sandrew clock-names = "uartclk", "apb_pclk"; 472295011Sandrew }; 473295011Sandrew 474295011Sandrew pb11mp_serial3: serial@1000c000 { 475295011Sandrew compatible = "arm,pl011", "arm,primecell"; 476295011Sandrew reg = <0x1000c000 0x1000>; 477295011Sandrew interrupt-parent = <&intc_pb11mp>; 478295011Sandrew interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 479295011Sandrew clocks = <&uartclk>, <&pclk>; 480295011Sandrew clock-names = "uartclk", "apb_pclk"; 481295011Sandrew }; 482295011Sandrew 483295011Sandrew ssp@1000d000 { 484295011Sandrew compatible = "arm,pl022", "arm,primecell"; 485295011Sandrew reg = <0x1000d000 0x1000>; 486295011Sandrew interrupt-parent = <&intc_pb11mp>; 487295011Sandrew interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 488295011Sandrew clocks = <&sspclk>, <&pclk>; 489295011Sandrew clock-names = "SSPCLK", "apb_pclk"; 490295011Sandrew }; 491295011Sandrew 492295011Sandrew watchdog@1000f000 { 493295011Sandrew compatible = "arm,sp805", "arm,primecell"; 494295011Sandrew reg = <0x1000f000 0x1000>; 495295011Sandrew interrupt-parent = <&intc_pb11mp>; 496295011Sandrew interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 497295011Sandrew clocks = <&wdogclk>, <&pclk>; 498295011Sandrew clock-names = "wdogclk", "apb_pclk"; 499295011Sandrew status = "disabled"; 500295011Sandrew }; 501295011Sandrew 502295011Sandrew watchdog@10010000 { 503295011Sandrew compatible = "arm,sp805", "arm,primecell"; 504295011Sandrew reg = <0x10010000 0x1000>; 505295011Sandrew interrupt-parent = <&intc_pb11mp>; 506295011Sandrew interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 507295011Sandrew clocks = <&wdogclk>, <&pclk>; 508295011Sandrew clock-names = "wdogclk", "apb_pclk"; 509295011Sandrew }; 510295011Sandrew 511295011Sandrew timer01: timer@10011000 { 512295011Sandrew compatible = "arm,sp804", "arm,primecell"; 513295011Sandrew reg = <0x10011000 0x1000>; 514295011Sandrew interrupt-parent = <&intc_tc11mp>; 515295011Sandrew interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; 516295011Sandrew arm,sp804-has-irq = <1>; 517295011Sandrew clocks = <&sp810_syscon 0>, 518295011Sandrew <&sp810_syscon 1>, 519295011Sandrew <&pclk>; 520295011Sandrew clock-names = "timerclk0", 521295011Sandrew "timerclk1", 522295011Sandrew "apb_pclk"; 523295011Sandrew }; 524295011Sandrew 525295011Sandrew timer23: timer@10012000 { 526295011Sandrew compatible = "arm,sp804", "arm,primecell"; 527295011Sandrew reg = <0x10012000 0x1000>; 528295011Sandrew interrupt-parent = <&intc_tc11mp>; 529295011Sandrew interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 530295011Sandrew arm,sp804-has-irq = <1>; 531295011Sandrew clocks = <&sp810_syscon 2>, 532295011Sandrew <&sp810_syscon 3>, 533295011Sandrew <&pclk>; 534295011Sandrew clock-names = "timerclk2", 535295011Sandrew "timerclk3", 536295011Sandrew "apb_pclk"; 537295011Sandrew }; 538295011Sandrew 539295011Sandrew gpio0: gpio@10013000 { 540295011Sandrew compatible = "arm,pl061", "arm,primecell"; 541295011Sandrew reg = <0x10013000 0x1000>; 542295011Sandrew gpio-controller; 543295011Sandrew interrupt-parent = <&intc_pb11mp>; 544295011Sandrew interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 545295011Sandrew #gpio-cells = <2>; 546295011Sandrew interrupt-controller; 547295011Sandrew #interrupt-cells = <2>; 548295011Sandrew clocks = <&pclk>; 549295011Sandrew clock-names = "apb_pclk"; 550295011Sandrew }; 551295011Sandrew 552295011Sandrew gpio1: gpio@10014000 { 553295011Sandrew compatible = "arm,pl061", "arm,primecell"; 554295011Sandrew reg = <0x10014000 0x1000>; 555295011Sandrew gpio-controller; 556295011Sandrew interrupt-parent = <&intc_pb11mp>; 557295011Sandrew interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 558295011Sandrew #gpio-cells = <2>; 559295011Sandrew interrupt-controller; 560295011Sandrew #interrupt-cells = <2>; 561295011Sandrew clocks = <&pclk>; 562295011Sandrew clock-names = "apb_pclk"; 563295011Sandrew }; 564295011Sandrew 565295011Sandrew gpio2: gpio@10015000 { 566295011Sandrew compatible = "arm,pl061", "arm,primecell"; 567295011Sandrew reg = <0x10015000 0x1000>; 568295011Sandrew gpio-controller; 569295011Sandrew interrupt-parent = <&intc_pb11mp>; 570295011Sandrew interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 571295011Sandrew #gpio-cells = <2>; 572295011Sandrew interrupt-controller; 573295011Sandrew #interrupt-cells = <2>; 574295011Sandrew clocks = <&pclk>; 575295011Sandrew clock-names = "apb_pclk"; 576295011Sandrew }; 577295011Sandrew 578295011Sandrew rtc: rtc@10017000 { 579295011Sandrew compatible = "arm,pl031", "arm,primecell"; 580295011Sandrew reg = <0x10017000 0x1000>; 581295011Sandrew interrupt-parent = <&intc_tc11mp>; 582295011Sandrew interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 583295011Sandrew clocks = <&pclk>; 584295011Sandrew clock-names = "apb_pclk"; 585295011Sandrew }; 586295011Sandrew 587295011Sandrew timer45: timer@10018000 { 588295011Sandrew compatible = "arm,sp804", "arm,primecell"; 589295011Sandrew reg = <0x10018000 0x1000>; 590295011Sandrew clocks = <&timclk>, <&pclk>; 591295011Sandrew clock-names = "timer", "apb_pclk"; 592295011Sandrew status = "disabled"; 593295011Sandrew }; 594295011Sandrew 595295011Sandrew timer67: timer@10019000 { 596295011Sandrew compatible = "arm,sp804", "arm,primecell"; 597295011Sandrew reg = <0x10019000 0x1000>; 598295011Sandrew clocks = <&timclk>, <&pclk>; 599295011Sandrew clock-names = "timer", "apb_pclk"; 600295011Sandrew status = "disabled"; 601295011Sandrew }; 602295011Sandrew 603295011Sandrew 604295011Sandrew clcd@10020000 { 605295011Sandrew compatible = "arm,pl111", "arm,primecell"; 606295011Sandrew reg = <0x10020000 0x1000>; 607295011Sandrew interrupt-parent = <&intc_pb11mp>; 608295011Sandrew interrupt-names = "combined"; 609295011Sandrew interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 610295011Sandrew clocks = <&oscclk4>, <&pclk>; 611295011Sandrew clock-names = "clcdclk", "apb_pclk"; 612295011Sandrew max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ 613295011Sandrew 614295011Sandrew port { 615295011Sandrew clcd_pads: endpoint { 616295011Sandrew remote-endpoint = <&clcd_panel>; 617295011Sandrew arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 618295011Sandrew }; 619295011Sandrew }; 620295011Sandrew 621295011Sandrew panel { 622295011Sandrew compatible = "panel-dpi"; 623295011Sandrew 624295011Sandrew port { 625295011Sandrew clcd_panel: endpoint { 626295011Sandrew remote-endpoint = <&clcd_pads>; 627295011Sandrew }; 628295011Sandrew }; 629295011Sandrew 630295011Sandrew panel-timing { 631295011Sandrew clock-frequency = <63500127>; 632295011Sandrew hactive = <1024>; 633295011Sandrew hback-porch = <152>; 634295011Sandrew hfront-porch = <48>; 635295011Sandrew hsync-len = <104>; 636295011Sandrew vactive = <768>; 637295011Sandrew vback-porch = <23>; 638295011Sandrew vfront-porch = <3>; 639295011Sandrew vsync-len = <4>; 640295011Sandrew }; 641295011Sandrew }; 642295011Sandrew }; 643295011Sandrew 644295011Sandrew /* 645295011Sandrew * This GIC on the Platform Baseboard is cascaded off the 646295011Sandrew * TestChip GIC 647295011Sandrew */ 648295011Sandrew intc_pb11mp: interrupt-controller@1e000000 { 649295011Sandrew compatible = "arm,arm11mp-gic"; 650295011Sandrew #interrupt-cells = <3>; 651295011Sandrew #address-cells = <1>; 652295011Sandrew interrupt-controller; 653295011Sandrew reg = <0x1e001000 0x1000>, 654295011Sandrew <0x1e000000 0x100>; 655295011Sandrew interrupt-parent = <&intc_tc11mp>; 656295011Sandrew interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 657295011Sandrew }; 658295011Sandrew 659295011Sandrew /* SMSC 9118 ethernet with PHY and EEPROM */ 660295011Sandrew ethernet@4e000000 { 661295011Sandrew compatible = "smsc,lan9118", "smsc,lan9115"; 662295011Sandrew reg = <0x4e000000 0x10000>; 663295011Sandrew interrupt-parent = <&intc_tc11mp>; 664295011Sandrew interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 665295011Sandrew phy-mode = "mii"; 666295011Sandrew reg-io-width = <4>; 667295011Sandrew smsc,irq-active-high; 668295011Sandrew smsc,irq-push-pull; 669295011Sandrew vdd33a-supply = <&veth>; 670295011Sandrew vddvario-supply = <&veth>; 671295011Sandrew }; 672295011Sandrew 673295011Sandrew usb@4f000000 { 674295011Sandrew compatible = "nxp,usb-isp1761"; 675295011Sandrew reg = <0x4f000000 0x20000>; 676295011Sandrew interrupt-parent = <&intc_tc11mp>; 677295011Sandrew interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; 678295011Sandrew port1-otg; 679295011Sandrew }; 680295011Sandrew }; 681295011Sandrew}; 682