1/* 2 * Copyright 2015 Linaro Ltd 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23/dts-v1/; 24#include <dt-bindings/interrupt-controller/irq.h> 25#include <dt-bindings/gpio/gpio.h> 26#include "skeleton.dtsi" 27 28/ { 29 model = "ARM RealView PB11MPcore"; 30 compatible = "arm,realview-pb11mp"; 31 32 chosen { }; 33 34 aliases { 35 serial0 = &pb11mp_serial0; 36 serial1 = &pb11mp_serial1; 37 serial2 = &pb11mp_serial2; 38 serial3 = &pb11mp_serial3; 39 }; 40 41 memory { 42 /* 43 * The PB11MPCore has 512 MiB memory @ 0x70000000 44 * and the first 256 are also remapped @ 0x00000000 45 */ 46 reg = <0x70000000 0x20000000>; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 enable-method = "arm,realview-smp"; 53 54 MP11_0: cpu@0 { 55 device_type = "cpu"; 56 compatible = "arm,arm11mpcore"; 57 reg = <0>; 58 next-level-cache = <&L2>; 59 }; 60 61 MP11_1: cpu@1 { 62 device_type = "cpu"; 63 compatible = "arm,arm11mpcore"; 64 reg = <1>; 65 next-level-cache = <&L2>; 66 }; 67 68 MP11_2: cpu@2 { 69 device_type = "cpu"; 70 compatible = "arm,arm11mpcore"; 71 reg = <2>; 72 next-level-cache = <&L2>; 73 }; 74 75 MP11_3: cpu@3 { 76 device_type = "cpu"; 77 compatible = "arm,arm11mpcore"; 78 reg = <3>; 79 next-level-cache = <&L2>; 80 }; 81 }; 82 83 /* Primary TestChip GIC synthesized with the CPU */ 84 intc_tc11mp: interrupt-controller@1f000100 { 85 compatible = "arm,tc11mp-gic"; 86 #interrupt-cells = <3>; 87 #address-cells = <1>; 88 interrupt-controller; 89 reg = <0x1f001000 0x1000>, 90 <0x1f000100 0x100>; 91 }; 92 93 L2: l2-cache { 94 compatible = "arm,l220-cache"; 95 reg = <0x1f002000 0x1000>; 96 interrupt-parent = <&intc_tc11mp>; 97 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, 98 <0 30 IRQ_TYPE_LEVEL_HIGH>, 99 <0 31 IRQ_TYPE_LEVEL_HIGH>; 100 cache-unified; 101 cache-level = <2>; 102 /* 103 * Override default cache size, sets and 104 * associativity as these may be erroneously set 105 * up by boot loader(s), probably for safety 106 * since th outer sync operation can cause the 107 * cache to hang unless disabled. 108 */ 109 cache-size = <1048576>; // 1MB 110 cache-sets = <4096>; 111 cache-line-size = <32>; 112 arm,shared-override; 113 arm,parity-enable; 114 arm,outer-sync-disable; 115 }; 116 117 scu@1f000000 { 118 compatible = "arm,arm11mp-scu"; 119 reg = <0x1f000000 0x100>; 120 }; 121 122 timer@1f000600 { 123 compatible = "arm,arm11mp-twd-timer"; 124 reg = <0x1f000600 0x20>; 125 interrupt-parent = <&intc_tc11mp>; 126 interrupts = <1 13 0xf04>; 127 }; 128 129 watchdog@1f000620 { 130 compatible = "arm,arm11mp-twd-wdt"; 131 reg = <0x1f000620 0x20>; 132 interrupt-parent = <&intc_tc11mp>; 133 interrupts = <1 14 0xf04>; 134 }; 135 136 /* PMU with one IRQ line per core */ 137 pmu { 138 compatible = "arm,arm11mpcore-pmu"; 139 interrupt-parent = <&intc_tc11mp>; 140 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, 141 <0 18 IRQ_TYPE_LEVEL_HIGH>, 142 <0 19 IRQ_TYPE_LEVEL_HIGH>, 143 <0 20 IRQ_TYPE_LEVEL_HIGH>; 144 interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>; 145 }; 146 147 /* The voltage to the MMC card is hardwired at 3.3V */ 148 vmmc: fixedregulator@0 { 149 compatible = "regulator-fixed"; 150 regulator-name = "vmmc"; 151 regulator-min-microvolt = <3300000>; 152 regulator-max-microvolt = <3300000>; 153 regulator-boot-on; 154 }; 155 156 veth: fixedregulator@0 { 157 compatible = "regulator-fixed"; 158 regulator-name = "veth"; 159 regulator-min-microvolt = <3300000>; 160 regulator-max-microvolt = <3300000>; 161 regulator-boot-on; 162 }; 163 164 xtal24mhz: xtal24mhz@24M { 165 #clock-cells = <0>; 166 compatible = "fixed-clock"; 167 clock-frequency = <24000000>; 168 }; 169 170 refclk32khz: refclk32khz { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <32768>; 174 }; 175 176 timclk: timclk@1M { 177 #clock-cells = <0>; 178 compatible = "fixed-factor-clock"; 179 clock-div = <24>; 180 clock-mult = <1>; 181 clocks = <&xtal24mhz>; 182 }; 183 184 mclk: mclk@24M { 185 #clock-cells = <0>; 186 compatible = "fixed-factor-clock"; 187 clock-div = <1>; 188 clock-mult = <1>; 189 clocks = <&xtal24mhz>; 190 }; 191 192 kmiclk: kmiclk@24M { 193 #clock-cells = <0>; 194 compatible = "fixed-factor-clock"; 195 clock-div = <1>; 196 clock-mult = <1>; 197 clocks = <&xtal24mhz>; 198 }; 199 200 sspclk: sspclk@24M { 201 #clock-cells = <0>; 202 compatible = "fixed-factor-clock"; 203 clock-div = <1>; 204 clock-mult = <1>; 205 clocks = <&xtal24mhz>; 206 }; 207 208 uartclk: uartclk@24M { 209 #clock-cells = <0>; 210 compatible = "fixed-factor-clock"; 211 clock-div = <1>; 212 clock-mult = <1>; 213 clocks = <&xtal24mhz>; 214 }; 215 216 wdogclk: wdogclk@24M { 217 #clock-cells = <0>; 218 compatible = "fixed-factor-clock"; 219 clock-div = <1>; 220 clock-mult = <1>; 221 clocks = <&xtal24mhz>; 222 }; 223 224 /* FIXME: this actually hangs off the PLL clocks */ 225 pclk: pclk@0 { 226 #clock-cells = <0>; 227 compatible = "fixed-clock"; 228 clock-frequency = <0>; 229 }; 230 231 flash0@40000000 { 232 /* 2 * 32MiB NOR Flash memory */ 233 compatible = "arm,vexpress-flash", "cfi-flash"; 234 reg = <0x40000000 0x04000000>; 235 bank-width = <4>; 236 }; 237 238 flash1@44000000 { 239 // 2 * 32MiB NOR Flash memory 240 compatible = "arm,vexpress-flash", "cfi-flash"; 241 reg = <0x44000000 0x04000000>; 242 bank-width = <4>; 243 }; 244 245 soc { 246 #address-cells = <1>; 247 #size-cells = <1>; 248 compatible = "arm,realview-pb11mp-soc", "simple-bus"; 249 regmap = <&pb11mp_syscon>; 250 ranges; 251 252 pb11mp_syscon: syscon@10000000 { 253 compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd"; 254 reg = <0x10000000 0x1000>; 255 256 led@08.0 { 257 compatible = "register-bit-led"; 258 offset = <0x08>; 259 mask = <0x01>; 260 label = "versatile:0"; 261 linux,default-trigger = "heartbeat"; 262 default-state = "on"; 263 }; 264 led@08.1 { 265 compatible = "register-bit-led"; 266 offset = <0x08>; 267 mask = <0x02>; 268 label = "versatile:1"; 269 linux,default-trigger = "mmc0"; 270 default-state = "off"; 271 }; 272 led@08.2 { 273 compatible = "register-bit-led"; 274 offset = <0x08>; 275 mask = <0x04>; 276 label = "versatile:2"; 277 linux,default-trigger = "cpu0"; 278 default-state = "off"; 279 }; 280 led@08.3 { 281 compatible = "register-bit-led"; 282 offset = <0x08>; 283 mask = <0x08>; 284 label = "versatile:3"; 285 linux,default-trigger = "cpu1"; 286 default-state = "off"; 287 }; 288 led@08.4 { 289 compatible = "register-bit-led"; 290 offset = <0x08>; 291 mask = <0x10>; 292 label = "versatile:4"; 293 linux,default-trigger = "cpu2"; 294 default-state = "off"; 295 }; 296 led@08.5 { 297 compatible = "register-bit-led"; 298 offset = <0x08>; 299 mask = <0x20>; 300 label = "versatile:5"; 301 linux,default-trigger = "cpu3"; 302 default-state = "off"; 303 }; 304 led@08.6 { 305 compatible = "register-bit-led"; 306 offset = <0x08>; 307 mask = <0x40>; 308 label = "versatile:6"; 309 default-state = "off"; 310 }; 311 led@08.7 { 312 compatible = "register-bit-led"; 313 offset = <0x08>; 314 mask = <0x80>; 315 label = "versatile:7"; 316 default-state = "off"; 317 }; 318 319 oscclk0: osc0@0c { 320 compatible = "arm,syscon-icst307"; 321 #clock-cells = <0>; 322 lock-offset = <0x20>; 323 vco-offset = <0x0C>; 324 clocks = <&xtal24mhz>; 325 }; 326 oscclk1: osc1@10 { 327 compatible = "arm,syscon-icst307"; 328 #clock-cells = <0>; 329 lock-offset = <0x20>; 330 vco-offset = <0x10>; 331 clocks = <&xtal24mhz>; 332 }; 333 oscclk2: osc2@14 { 334 compatible = "arm,syscon-icst307"; 335 #clock-cells = <0>; 336 lock-offset = <0x20>; 337 vco-offset = <0x14>; 338 clocks = <&xtal24mhz>; 339 }; 340 oscclk3: osc3@18 { 341 compatible = "arm,syscon-icst307"; 342 #clock-cells = <0>; 343 lock-offset = <0x20>; 344 vco-offset = <0x18>; 345 clocks = <&xtal24mhz>; 346 }; 347 oscclk4: osc4@1c { 348 compatible = "arm,syscon-icst307"; 349 #clock-cells = <0>; 350 lock-offset = <0x20>; 351 vco-offset = <0x1c>; 352 clocks = <&xtal24mhz>; 353 }; 354 oscclk5: osc5@d4 { 355 compatible = "arm,syscon-icst307"; 356 #clock-cells = <0>; 357 lock-offset = <0x20>; 358 vco-offset = <0xd4>; 359 clocks = <&xtal24mhz>; 360 }; 361 oscclk6: osc6@d8 { 362 compatible = "arm,syscon-icst307"; 363 #clock-cells = <0>; 364 lock-offset = <0x20>; 365 vco-offset = <0xd8>; 366 clocks = <&xtal24mhz>; 367 }; 368 }; 369 370 sp810_syscon: sysctl@10001000 { 371 compatible = "arm,sp810", "arm,primecell"; 372 reg = <0x10001000 0x1000>; 373 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; 374 clock-names = "refclk", "timclk", "apb_pclk"; 375 #clock-cells = <1>; 376 clock-output-names = "timerclk0", 377 "timerclk1", 378 "timerclk2", 379 "timerclk3"; 380 assigned-clocks = <&sp810_syscon 0>, 381 <&sp810_syscon 1>, 382 <&sp810_syscon 2>, 383 <&sp810_syscon 3>; 384 assigned-clock-parents = <&timclk>, 385 <&timclk>, 386 <&timclk>, 387 <&timclk>; 388 }; 389 390 i2c0: i2c@10002000 { 391 #address-cells = <1>; 392 #size-cells = <0>; 393 compatible = "arm,versatile-i2c"; 394 reg = <0x10002000 0x1000>; 395 396 rtc@68 { 397 compatible = "dallas,ds1338"; 398 reg = <0x68>; 399 }; 400 }; 401 402 aaci: aaci@10004000 { 403 compatible = "arm,pl041", "arm,primecell"; 404 reg = <0x10004000 0x1000>; 405 interrupt-parent = <&intc_tc11mp>; 406 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&pclk>; 408 clock-names = "apb_pclk"; 409 }; 410 411 mci: mmcsd@10005000 { 412 compatible = "arm,pl18x", "arm,primecell"; 413 reg = <0x10005000 0x1000>; 414 interrupt-parent = <&intc_tc11mp>; 415 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, 416 <0 15 IRQ_TYPE_LEVEL_HIGH>; 417 /* Due to frequent FIFO overruns, use just 500 kHz */ 418 max-frequency = <500000>; 419 bus-width = <4>; 420 cap-sd-highspeed; 421 cap-mmc-highspeed; 422 clocks = <&mclk>, <&pclk>; 423 clock-names = "mclk", "apb_pclk"; 424 vmmc-supply = <&vmmc>; 425 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 426 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 427 }; 428 429 kmi0: kmi@10006000 { 430 compatible = "arm,pl050", "arm,primecell"; 431 reg = <0x10006000 0x1000>; 432 interrupt-parent = <&intc_tc11mp>; 433 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&kmiclk>, <&pclk>; 435 clock-names = "KMIREFCLK", "apb_pclk"; 436 }; 437 438 kmi1: kmi@10007000 { 439 compatible = "arm,pl050", "arm,primecell"; 440 reg = <0x10007000 0x1000>; 441 interrupt-parent = <&intc_tc11mp>; 442 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&kmiclk>, <&pclk>; 444 clock-names = "KMIREFCLK", "apb_pclk"; 445 }; 446 447 pb11mp_serial0: serial@10009000 { 448 compatible = "arm,pl011", "arm,primecell"; 449 reg = <0x10009000 0x1000>; 450 interrupt-parent = <&intc_tc11mp>; 451 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&uartclk>, <&pclk>; 453 clock-names = "uartclk", "apb_pclk"; 454 }; 455 456 pb11mp_serial1: serial@1000a000 { 457 compatible = "arm,pl011", "arm,primecell"; 458 reg = <0x1000a000 0x1000>; 459 interrupt-parent = <&intc_tc11mp>; 460 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&uartclk>, <&pclk>; 462 clock-names = "uartclk", "apb_pclk"; 463 }; 464 465 pb11mp_serial2: serial@1000b000 { 466 compatible = "arm,pl011", "arm,primecell"; 467 reg = <0x1000b000 0x1000>; 468 interrupt-parent = <&intc_pb11mp>; 469 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&uartclk>, <&pclk>; 471 clock-names = "uartclk", "apb_pclk"; 472 }; 473 474 pb11mp_serial3: serial@1000c000 { 475 compatible = "arm,pl011", "arm,primecell"; 476 reg = <0x1000c000 0x1000>; 477 interrupt-parent = <&intc_pb11mp>; 478 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&uartclk>, <&pclk>; 480 clock-names = "uartclk", "apb_pclk"; 481 }; 482 483 ssp@1000d000 { 484 compatible = "arm,pl022", "arm,primecell"; 485 reg = <0x1000d000 0x1000>; 486 interrupt-parent = <&intc_pb11mp>; 487 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&sspclk>, <&pclk>; 489 clock-names = "SSPCLK", "apb_pclk"; 490 }; 491 492 watchdog@1000f000 { 493 compatible = "arm,sp805", "arm,primecell"; 494 reg = <0x1000f000 0x1000>; 495 interrupt-parent = <&intc_pb11mp>; 496 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&wdogclk>, <&pclk>; 498 clock-names = "wdogclk", "apb_pclk"; 499 status = "disabled"; 500 }; 501 502 watchdog@10010000 { 503 compatible = "arm,sp805", "arm,primecell"; 504 reg = <0x10010000 0x1000>; 505 interrupt-parent = <&intc_pb11mp>; 506 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&wdogclk>, <&pclk>; 508 clock-names = "wdogclk", "apb_pclk"; 509 }; 510 511 timer01: timer@10011000 { 512 compatible = "arm,sp804", "arm,primecell"; 513 reg = <0x10011000 0x1000>; 514 interrupt-parent = <&intc_tc11mp>; 515 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; 516 arm,sp804-has-irq = <1>; 517 clocks = <&sp810_syscon 0>, 518 <&sp810_syscon 1>, 519 <&pclk>; 520 clock-names = "timerclk0", 521 "timerclk1", 522 "apb_pclk"; 523 }; 524 525 timer23: timer@10012000 { 526 compatible = "arm,sp804", "arm,primecell"; 527 reg = <0x10012000 0x1000>; 528 interrupt-parent = <&intc_tc11mp>; 529 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 530 arm,sp804-has-irq = <1>; 531 clocks = <&sp810_syscon 2>, 532 <&sp810_syscon 3>, 533 <&pclk>; 534 clock-names = "timerclk2", 535 "timerclk3", 536 "apb_pclk"; 537 }; 538 539 gpio0: gpio@10013000 { 540 compatible = "arm,pl061", "arm,primecell"; 541 reg = <0x10013000 0x1000>; 542 gpio-controller; 543 interrupt-parent = <&intc_pb11mp>; 544 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 545 #gpio-cells = <2>; 546 interrupt-controller; 547 #interrupt-cells = <2>; 548 clocks = <&pclk>; 549 clock-names = "apb_pclk"; 550 }; 551 552 gpio1: gpio@10014000 { 553 compatible = "arm,pl061", "arm,primecell"; 554 reg = <0x10014000 0x1000>; 555 gpio-controller; 556 interrupt-parent = <&intc_pb11mp>; 557 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 558 #gpio-cells = <2>; 559 interrupt-controller; 560 #interrupt-cells = <2>; 561 clocks = <&pclk>; 562 clock-names = "apb_pclk"; 563 }; 564 565 gpio2: gpio@10015000 { 566 compatible = "arm,pl061", "arm,primecell"; 567 reg = <0x10015000 0x1000>; 568 gpio-controller; 569 interrupt-parent = <&intc_pb11mp>; 570 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 571 #gpio-cells = <2>; 572 interrupt-controller; 573 #interrupt-cells = <2>; 574 clocks = <&pclk>; 575 clock-names = "apb_pclk"; 576 }; 577 578 rtc: rtc@10017000 { 579 compatible = "arm,pl031", "arm,primecell"; 580 reg = <0x10017000 0x1000>; 581 interrupt-parent = <&intc_tc11mp>; 582 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&pclk>; 584 clock-names = "apb_pclk"; 585 }; 586 587 timer45: timer@10018000 { 588 compatible = "arm,sp804", "arm,primecell"; 589 reg = <0x10018000 0x1000>; 590 clocks = <&timclk>, <&pclk>; 591 clock-names = "timer", "apb_pclk"; 592 status = "disabled"; 593 }; 594 595 timer67: timer@10019000 { 596 compatible = "arm,sp804", "arm,primecell"; 597 reg = <0x10019000 0x1000>; 598 clocks = <&timclk>, <&pclk>; 599 clock-names = "timer", "apb_pclk"; 600 status = "disabled"; 601 }; 602 603 604 clcd@10020000 { 605 compatible = "arm,pl111", "arm,primecell"; 606 reg = <0x10020000 0x1000>; 607 interrupt-parent = <&intc_pb11mp>; 608 interrupt-names = "combined"; 609 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&oscclk4>, <&pclk>; 611 clock-names = "clcdclk", "apb_pclk"; 612 max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ 613 614 port { 615 clcd_pads: endpoint { 616 remote-endpoint = <&clcd_panel>; 617 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 618 }; 619 }; 620 621 panel { 622 compatible = "panel-dpi"; 623 624 port { 625 clcd_panel: endpoint { 626 remote-endpoint = <&clcd_pads>; 627 }; 628 }; 629 630 panel-timing { 631 clock-frequency = <63500127>; 632 hactive = <1024>; 633 hback-porch = <152>; 634 hfront-porch = <48>; 635 hsync-len = <104>; 636 vactive = <768>; 637 vback-porch = <23>; 638 vfront-porch = <3>; 639 vsync-len = <4>; 640 }; 641 }; 642 }; 643 644 /* 645 * This GIC on the Platform Baseboard is cascaded off the 646 * TestChip GIC 647 */ 648 intc_pb11mp: interrupt-controller@1e000000 { 649 compatible = "arm,arm11mp-gic"; 650 #interrupt-cells = <3>; 651 #address-cells = <1>; 652 interrupt-controller; 653 reg = <0x1e001000 0x1000>, 654 <0x1e000000 0x100>; 655 interrupt-parent = <&intc_tc11mp>; 656 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 657 }; 658 659 /* SMSC 9118 ethernet with PHY and EEPROM */ 660 ethernet@4e000000 { 661 compatible = "smsc,lan9118", "smsc,lan9115"; 662 reg = <0x4e000000 0x10000>; 663 interrupt-parent = <&intc_tc11mp>; 664 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 665 phy-mode = "mii"; 666 reg-io-width = <4>; 667 smsc,irq-active-high; 668 smsc,irq-push-pull; 669 vdd33a-supply = <&veth>; 670 vddvario-supply = <&veth>; 671 }; 672 673 usb@4f000000 { 674 compatible = "nxp,usb-isp1761"; 675 reg = <0x4f000000 0x20000>; 676 interrupt-parent = <&intc_tc11mp>; 677 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; 678 port1-otg; 679 }; 680 }; 681}; 682