1/* 2 * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ 3 * Author: Rostislav Lisovy <lisovy@jablotron.cz> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9#include "am33xx.dtsi" 10 11/ { 12 model = "Grinn AM335x ChiliSOM"; 13 compatible = "grinn,am335x-chilisom", "ti,am33xx"; 14 15 cpus { 16 cpu@0 { 17 cpu0-supply = <&dcdc2_reg>; 18 }; 19 }; 20 21 memory { 22 device_type = "memory"; 23 reg = <0x80000000 0x20000000>; /* 512 MB */ 24 }; 25}; 26 27&am33xx_pinmux { 28 pinctrl-names = "default"; 29 30 i2c0_pins: pinmux_i2c0_pins { 31 pinctrl-single,pins = < 32 AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 33 AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 34 >; 35 }; 36 37 uart0_pins: pinmux_uart0_pins { 38 pinctrl-single,pins = < 39 AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 40 AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ 41 >; 42 }; 43 44 cpsw_default: cpsw_default { 45 pinctrl-single,pins = < 46 /* Slave 1 */ 47 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ 48 AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ 49 AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ 50 AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ 51 AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ 52 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ 53 AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ 54 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */ 55 >; 56 }; 57 58 cpsw_sleep: cpsw_sleep { 59 pinctrl-single,pins = < 60 /* Slave 1 reset value */ 61 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) 62 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) 63 AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) 64 AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) 65 AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) 66 AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) 67 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) 68 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) 69 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) 70 >; 71 }; 72 73 davinci_mdio_default: davinci_mdio_default { 74 pinctrl-single,pins = < 75 /* mdio_data.mdio_data */ 76 AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) 77 /* mdio_clk.mdio_clk */ 78 AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) 79 >; 80 }; 81 82 davinci_mdio_sleep: davinci_mdio_sleep { 83 pinctrl-single,pins = < 84 /* MDIO reset value */ 85 AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) 86 AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) 87 >; 88 }; 89 90 nandflash_pins: nandflash_pins { 91 pinctrl-single,pins = < 92 AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 93 AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 94 AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 95 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 96 AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 97 AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 98 AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 99 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 100 101 AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 102 AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 103 AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 104 AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 105 AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 106 AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 107 >; 108 }; 109}; 110 111&uart0 { 112 pinctrl-names = "default"; 113 pinctrl-0 = <&uart0_pins>; 114 115 status = "okay"; 116}; 117 118&i2c0 { 119 pinctrl-names = "default"; 120 pinctrl-0 = <&i2c0_pins>; 121 122 status = "okay"; 123 clock-frequency = <400000>; 124 125 tps: tps@24 { 126 reg = <0x24>; 127 }; 128 129}; 130 131&tps { 132 compatible = "ti,tps65217"; 133 134 regulators { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 dcdc1_reg: regulator@0 { 139 reg = <0>; 140 regulator-name = "vdds_dpr"; 141 regulator-always-on; 142 }; 143 144 dcdc2_reg: regulator@1 { 145 reg = <1>; 146 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 147 regulator-name = "vdd_mpu"; 148 regulator-min-microvolt = <925000>; 149 regulator-max-microvolt = <1325000>; 150 regulator-boot-on; 151 regulator-always-on; 152 }; 153 154 dcdc3_reg: regulator@2 { 155 reg = <2>; 156 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 157 regulator-name = "vdd_core"; 158 regulator-min-microvolt = <925000>; 159 regulator-max-microvolt = <1150000>; 160 regulator-boot-on; 161 regulator-always-on; 162 }; 163 164 ldo1_reg: regulator@3 { 165 reg = <3>; 166 regulator-name = "vio,vrtc,vdds"; 167 regulator-boot-on; 168 regulator-always-on; 169 }; 170 171 ldo2_reg: regulator@4 { 172 reg = <4>; 173 regulator-name = "vdd_3v3aux"; 174 regulator-boot-on; 175 regulator-always-on; 176 }; 177 178 ldo3_reg: regulator@5 { 179 reg = <5>; 180 regulator-name = "vdd_1v8"; 181 regulator-boot-on; 182 regulator-always-on; 183 }; 184 185 ldo4_reg: regulator@6 { 186 reg = <6>; 187 regulator-name = "vdd_3v3d"; 188 regulator-boot-on; 189 regulator-always-on; 190 }; 191 }; 192}; 193 194/* Ethernet MAC */ 195&mac { 196 slaves = <1>; 197 pinctrl-names = "default", "sleep"; 198 pinctrl-0 = <&cpsw_default>; 199 pinctrl-1 = <&cpsw_sleep>; 200 status = "okay"; 201}; 202 203&davinci_mdio { 204 pinctrl-names = "default", "sleep"; 205 pinctrl-0 = <&davinci_mdio_default>; 206 pinctrl-1 = <&davinci_mdio_sleep>; 207 status = "okay"; 208}; 209 210/* NAND Flash */ 211&elm { 212 status = "okay"; 213}; 214 215&gpmc { 216 status = "okay"; 217 pinctrl-names = "default"; 218 pinctrl-0 = <&nandflash_pins>; 219 ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */ 220 nand@0,0 { 221 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 222 ti,nand-ecc-opt = "bch8"; 223 ti,elm-id = <&elm>; 224 nand-bus-width = <8>; 225 gpmc,device-width = <1>; 226 gpmc,sync-clk-ps = <0>; 227 gpmc,cs-on-ns = <0>; 228 gpmc,cs-rd-off-ns = <44>; 229 gpmc,cs-wr-off-ns = <44>; 230 gpmc,adv-on-ns = <6>; 231 gpmc,adv-rd-off-ns = <34>; 232 gpmc,adv-wr-off-ns = <44>; 233 gpmc,we-on-ns = <0>; 234 gpmc,we-off-ns = <40>; 235 gpmc,oe-on-ns = <0>; 236 gpmc,oe-off-ns = <54>; 237 gpmc,access-ns = <64>; 238 gpmc,rd-cycle-ns = <82>; 239 gpmc,wr-cycle-ns = <82>; 240 gpmc,wait-on-read = "true"; 241 gpmc,wait-on-write = "true"; 242 gpmc,bus-turnaround-ns = <0>; 243 gpmc,cycle2cycle-delay-ns = <0>; 244 gpmc,clk-activation-ns = <0>; 245 gpmc,wait-monitoring-ns = <0>; 246 gpmc,wr-access-ns = <40>; 247 gpmc,wr-data-mux-bus-ns = <0>; 248 }; 249}; 250