if_wb.c revision 87846
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_wb.c 87846 2001-12-14 05:56:35Z luigi $ 33 */ 34 35/* 36 * Winbond fast ethernet PCI NIC driver 37 * 38 * Supports various cheap network adapters based on the Winbond W89C840F 39 * fast ethernet controller chip. This includes adapters manufactured by 40 * Winbond itself and some made by Linksys. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "opt_bdg.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95#include <sys/queue.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102 103#include <net/bpf.h> 104 105#include <vm/vm.h> /* for vtophys */ 106#include <vm/pmap.h> /* for vtophys */ 107#include <machine/bus_memio.h> 108#include <machine/bus_pio.h> 109#include <machine/bus.h> 110#include <machine/resource.h> 111#include <sys/bus.h> 112#include <sys/rman.h> 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117#include <dev/mii/mii.h> 118#include <dev/mii/miivar.h> 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#define WB_USEIOSPACE 124 125#include <pci/if_wbreg.h> 126 127MODULE_DEPEND(wb, miibus, 1, 1, 1); 128 129#ifndef lint 130static const char rcsid[] = 131 "$FreeBSD: head/sys/pci/if_wb.c 87846 2001-12-14 05:56:35Z luigi $"; 132#endif 133 134/* 135 * Various supported device vendors/types and their names. 136 */ 137static struct wb_type wb_devs[] = { 138 { WB_VENDORID, WB_DEVICEID_840F, 139 "Winbond W89C840F 10/100BaseTX" }, 140 { CP_VENDORID, CP_DEVICEID_RL100, 141 "Compex RL100-ATX 10/100baseTX" }, 142 { 0, 0, NULL } 143}; 144 145static int wb_probe __P((device_t)); 146static int wb_attach __P((device_t)); 147static int wb_detach __P((device_t)); 148 149static void wb_bfree __P((caddr_t, void *args)); 150static int wb_newbuf __P((struct wb_softc *, 151 struct wb_chain_onefrag *, 152 struct mbuf *)); 153static int wb_encap __P((struct wb_softc *, struct wb_chain *, 154 struct mbuf *)); 155 156static void wb_rxeof __P((struct wb_softc *)); 157static void wb_rxeoc __P((struct wb_softc *)); 158static void wb_txeof __P((struct wb_softc *)); 159static void wb_txeoc __P((struct wb_softc *)); 160static void wb_intr __P((void *)); 161static void wb_tick __P((void *)); 162static void wb_start __P((struct ifnet *)); 163static int wb_ioctl __P((struct ifnet *, u_long, caddr_t)); 164static void wb_init __P((void *)); 165static void wb_stop __P((struct wb_softc *)); 166static void wb_watchdog __P((struct ifnet *)); 167static void wb_shutdown __P((device_t)); 168static int wb_ifmedia_upd __P((struct ifnet *)); 169static void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 170 171static void wb_eeprom_putbyte __P((struct wb_softc *, int)); 172static void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *)); 173static void wb_read_eeprom __P((struct wb_softc *, caddr_t, int, 174 int, int)); 175static void wb_mii_sync __P((struct wb_softc *)); 176static void wb_mii_send __P((struct wb_softc *, u_int32_t, int)); 177static int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *)); 178static int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *)); 179 180static void wb_setcfg __P((struct wb_softc *, u_int32_t)); 181static u_int8_t wb_calchash __P((caddr_t)); 182static void wb_setmulti __P((struct wb_softc *)); 183static void wb_reset __P((struct wb_softc *)); 184static void wb_fixmedia __P((struct wb_softc *)); 185static int wb_list_rx_init __P((struct wb_softc *)); 186static int wb_list_tx_init __P((struct wb_softc *)); 187 188static int wb_miibus_readreg __P((device_t, int, int)); 189static int wb_miibus_writereg __P((device_t, int, int, int)); 190static void wb_miibus_statchg __P((device_t)); 191 192#ifdef WB_USEIOSPACE 193#define WB_RES SYS_RES_IOPORT 194#define WB_RID WB_PCI_LOIO 195#else 196#define WB_RES SYS_RES_MEMORY 197#define WB_RID WB_PCI_LOMEM 198#endif 199 200static device_method_t wb_methods[] = { 201 /* Device interface */ 202 DEVMETHOD(device_probe, wb_probe), 203 DEVMETHOD(device_attach, wb_attach), 204 DEVMETHOD(device_detach, wb_detach), 205 DEVMETHOD(device_shutdown, wb_shutdown), 206 207 /* bus interface, for miibus */ 208 DEVMETHOD(bus_print_child, bus_generic_print_child), 209 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 210 211 /* MII interface */ 212 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 213 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 214 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 215 { 0, 0 } 216}; 217 218static driver_t wb_driver = { 219 "wb", 220 wb_methods, 221 sizeof(struct wb_softc) 222}; 223 224static devclass_t wb_devclass; 225 226DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 227DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 228 229#define WB_SETBIT(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, \ 231 CSR_READ_4(sc, reg) | x) 232 233#define WB_CLRBIT(sc, reg, x) \ 234 CSR_WRITE_4(sc, reg, \ 235 CSR_READ_4(sc, reg) & ~x) 236 237#define SIO_SET(x) \ 238 CSR_WRITE_4(sc, WB_SIO, \ 239 CSR_READ_4(sc, WB_SIO) | x) 240 241#define SIO_CLR(x) \ 242 CSR_WRITE_4(sc, WB_SIO, \ 243 CSR_READ_4(sc, WB_SIO) & ~x) 244 245/* 246 * Send a read command and address to the EEPROM, check for ACK. 247 */ 248static void wb_eeprom_putbyte(sc, addr) 249 struct wb_softc *sc; 250 int addr; 251{ 252 register int d, i; 253 254 d = addr | WB_EECMD_READ; 255 256 /* 257 * Feed in each bit and stobe the clock. 258 */ 259 for (i = 0x400; i; i >>= 1) { 260 if (d & i) { 261 SIO_SET(WB_SIO_EE_DATAIN); 262 } else { 263 SIO_CLR(WB_SIO_EE_DATAIN); 264 } 265 DELAY(100); 266 SIO_SET(WB_SIO_EE_CLK); 267 DELAY(150); 268 SIO_CLR(WB_SIO_EE_CLK); 269 DELAY(100); 270 } 271 272 return; 273} 274 275/* 276 * Read a word of data stored in the EEPROM at address 'addr.' 277 */ 278static void wb_eeprom_getword(sc, addr, dest) 279 struct wb_softc *sc; 280 int addr; 281 u_int16_t *dest; 282{ 283 register int i; 284 u_int16_t word = 0; 285 286 /* Enter EEPROM access mode. */ 287 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 288 289 /* 290 * Send address of word we want to read. 291 */ 292 wb_eeprom_putbyte(sc, addr); 293 294 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 295 296 /* 297 * Start reading bits from EEPROM. 298 */ 299 for (i = 0x8000; i; i >>= 1) { 300 SIO_SET(WB_SIO_EE_CLK); 301 DELAY(100); 302 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 303 word |= i; 304 SIO_CLR(WB_SIO_EE_CLK); 305 DELAY(100); 306 } 307 308 /* Turn off EEPROM access mode. */ 309 CSR_WRITE_4(sc, WB_SIO, 0); 310 311 *dest = word; 312 313 return; 314} 315 316/* 317 * Read a sequence of words from the EEPROM. 318 */ 319static void wb_read_eeprom(sc, dest, off, cnt, swap) 320 struct wb_softc *sc; 321 caddr_t dest; 322 int off; 323 int cnt; 324 int swap; 325{ 326 int i; 327 u_int16_t word = 0, *ptr; 328 329 for (i = 0; i < cnt; i++) { 330 wb_eeprom_getword(sc, off + i, &word); 331 ptr = (u_int16_t *)(dest + (i * 2)); 332 if (swap) 333 *ptr = ntohs(word); 334 else 335 *ptr = word; 336 } 337 338 return; 339} 340 341/* 342 * Sync the PHYs by setting data bit and strobing the clock 32 times. 343 */ 344static void wb_mii_sync(sc) 345 struct wb_softc *sc; 346{ 347 register int i; 348 349 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 350 351 for (i = 0; i < 32; i++) { 352 SIO_SET(WB_SIO_MII_CLK); 353 DELAY(1); 354 SIO_CLR(WB_SIO_MII_CLK); 355 DELAY(1); 356 } 357 358 return; 359} 360 361/* 362 * Clock a series of bits through the MII. 363 */ 364static void wb_mii_send(sc, bits, cnt) 365 struct wb_softc *sc; 366 u_int32_t bits; 367 int cnt; 368{ 369 int i; 370 371 SIO_CLR(WB_SIO_MII_CLK); 372 373 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 374 if (bits & i) { 375 SIO_SET(WB_SIO_MII_DATAIN); 376 } else { 377 SIO_CLR(WB_SIO_MII_DATAIN); 378 } 379 DELAY(1); 380 SIO_CLR(WB_SIO_MII_CLK); 381 DELAY(1); 382 SIO_SET(WB_SIO_MII_CLK); 383 } 384} 385 386/* 387 * Read an PHY register through the MII. 388 */ 389static int wb_mii_readreg(sc, frame) 390 struct wb_softc *sc; 391 struct wb_mii_frame *frame; 392 393{ 394 int i, ack; 395 396 WB_LOCK(sc); 397 398 /* 399 * Set up frame for RX. 400 */ 401 frame->mii_stdelim = WB_MII_STARTDELIM; 402 frame->mii_opcode = WB_MII_READOP; 403 frame->mii_turnaround = 0; 404 frame->mii_data = 0; 405 406 CSR_WRITE_4(sc, WB_SIO, 0); 407 408 /* 409 * Turn on data xmit. 410 */ 411 SIO_SET(WB_SIO_MII_DIR); 412 413 wb_mii_sync(sc); 414 415 /* 416 * Send command/address info. 417 */ 418 wb_mii_send(sc, frame->mii_stdelim, 2); 419 wb_mii_send(sc, frame->mii_opcode, 2); 420 wb_mii_send(sc, frame->mii_phyaddr, 5); 421 wb_mii_send(sc, frame->mii_regaddr, 5); 422 423 /* Idle bit */ 424 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 425 DELAY(1); 426 SIO_SET(WB_SIO_MII_CLK); 427 DELAY(1); 428 429 /* Turn off xmit. */ 430 SIO_CLR(WB_SIO_MII_DIR); 431 /* Check for ack */ 432 SIO_CLR(WB_SIO_MII_CLK); 433 DELAY(1); 434 SIO_SET(WB_SIO_MII_CLK); 435 DELAY(1); 436 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 437 SIO_CLR(WB_SIO_MII_CLK); 438 DELAY(1); 439 SIO_SET(WB_SIO_MII_CLK); 440 DELAY(1); 441 442 /* 443 * Now try reading data bits. If the ack failed, we still 444 * need to clock through 16 cycles to keep the PHY(s) in sync. 445 */ 446 if (ack) { 447 for(i = 0; i < 16; i++) { 448 SIO_CLR(WB_SIO_MII_CLK); 449 DELAY(1); 450 SIO_SET(WB_SIO_MII_CLK); 451 DELAY(1); 452 } 453 goto fail; 454 } 455 456 for (i = 0x8000; i; i >>= 1) { 457 SIO_CLR(WB_SIO_MII_CLK); 458 DELAY(1); 459 if (!ack) { 460 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 461 frame->mii_data |= i; 462 DELAY(1); 463 } 464 SIO_SET(WB_SIO_MII_CLK); 465 DELAY(1); 466 } 467 468fail: 469 470 SIO_CLR(WB_SIO_MII_CLK); 471 DELAY(1); 472 SIO_SET(WB_SIO_MII_CLK); 473 DELAY(1); 474 475 WB_UNLOCK(sc); 476 477 if (ack) 478 return(1); 479 return(0); 480} 481 482/* 483 * Write to a PHY register through the MII. 484 */ 485static int wb_mii_writereg(sc, frame) 486 struct wb_softc *sc; 487 struct wb_mii_frame *frame; 488 489{ 490 WB_LOCK(sc); 491 492 /* 493 * Set up frame for TX. 494 */ 495 496 frame->mii_stdelim = WB_MII_STARTDELIM; 497 frame->mii_opcode = WB_MII_WRITEOP; 498 frame->mii_turnaround = WB_MII_TURNAROUND; 499 500 /* 501 * Turn on data output. 502 */ 503 SIO_SET(WB_SIO_MII_DIR); 504 505 wb_mii_sync(sc); 506 507 wb_mii_send(sc, frame->mii_stdelim, 2); 508 wb_mii_send(sc, frame->mii_opcode, 2); 509 wb_mii_send(sc, frame->mii_phyaddr, 5); 510 wb_mii_send(sc, frame->mii_regaddr, 5); 511 wb_mii_send(sc, frame->mii_turnaround, 2); 512 wb_mii_send(sc, frame->mii_data, 16); 513 514 /* Idle bit. */ 515 SIO_SET(WB_SIO_MII_CLK); 516 DELAY(1); 517 SIO_CLR(WB_SIO_MII_CLK); 518 DELAY(1); 519 520 /* 521 * Turn off xmit. 522 */ 523 SIO_CLR(WB_SIO_MII_DIR); 524 525 WB_UNLOCK(sc); 526 527 return(0); 528} 529 530static int wb_miibus_readreg(dev, phy, reg) 531 device_t dev; 532 int phy, reg; 533{ 534 struct wb_softc *sc; 535 struct wb_mii_frame frame; 536 537 sc = device_get_softc(dev); 538 539 bzero((char *)&frame, sizeof(frame)); 540 541 frame.mii_phyaddr = phy; 542 frame.mii_regaddr = reg; 543 wb_mii_readreg(sc, &frame); 544 545 return(frame.mii_data); 546} 547 548static int wb_miibus_writereg(dev, phy, reg, data) 549 device_t dev; 550 int phy, reg, data; 551{ 552 struct wb_softc *sc; 553 struct wb_mii_frame frame; 554 555 sc = device_get_softc(dev); 556 557 bzero((char *)&frame, sizeof(frame)); 558 559 frame.mii_phyaddr = phy; 560 frame.mii_regaddr = reg; 561 frame.mii_data = data; 562 563 wb_mii_writereg(sc, &frame); 564 565 return(0); 566} 567 568static void wb_miibus_statchg(dev) 569 device_t dev; 570{ 571 struct wb_softc *sc; 572 struct mii_data *mii; 573 574 sc = device_get_softc(dev); 575 WB_LOCK(sc); 576 mii = device_get_softc(sc->wb_miibus); 577 wb_setcfg(sc, mii->mii_media_active); 578 WB_UNLOCK(sc); 579 580 return; 581} 582 583static u_int8_t wb_calchash(addr) 584 caddr_t addr; 585{ 586 u_int32_t crc, carry; 587 int i, j; 588 u_int8_t c; 589 590 /* Compute CRC for the address value. */ 591 crc = 0xFFFFFFFF; /* initial value */ 592 593 for (i = 0; i < 6; i++) { 594 c = *(addr + i); 595 for (j = 0; j < 8; j++) { 596 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 597 crc <<= 1; 598 c >>= 1; 599 if (carry) 600 crc = (crc ^ 0x04c11db6) | carry; 601 } 602 } 603 604 /* 605 * return the filter bit position 606 * Note: I arrived at the following nonsense 607 * through experimentation. It's not the usual way to 608 * generate the bit position but it's the only thing 609 * I could come up with that works. 610 */ 611 return(~(crc >> 26) & 0x0000003F); 612} 613 614/* 615 * Program the 64-bit multicast hash filter. 616 */ 617static void wb_setmulti(sc) 618 struct wb_softc *sc; 619{ 620 struct ifnet *ifp; 621 int h = 0; 622 u_int32_t hashes[2] = { 0, 0 }; 623 struct ifmultiaddr *ifma; 624 u_int32_t rxfilt; 625 int mcnt = 0; 626 627 ifp = &sc->arpcom.ac_if; 628 629 rxfilt = CSR_READ_4(sc, WB_NETCFG); 630 631 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 632 rxfilt |= WB_NETCFG_RX_MULTI; 633 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 634 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 635 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 636 return; 637 } 638 639 /* first, zot all the existing hash bits */ 640 CSR_WRITE_4(sc, WB_MAR0, 0); 641 CSR_WRITE_4(sc, WB_MAR1, 0); 642 643 /* now program new ones */ 644 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 645 if (ifma->ifma_addr->sa_family != AF_LINK) 646 continue; 647 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 648 if (h < 32) 649 hashes[0] |= (1 << h); 650 else 651 hashes[1] |= (1 << (h - 32)); 652 mcnt++; 653 } 654 655 if (mcnt) 656 rxfilt |= WB_NETCFG_RX_MULTI; 657 else 658 rxfilt &= ~WB_NETCFG_RX_MULTI; 659 660 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 661 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 662 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 663 664 return; 665} 666 667/* 668 * The Winbond manual states that in order to fiddle with the 669 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 670 * first have to put the transmit and/or receive logic in the idle state. 671 */ 672static void wb_setcfg(sc, media) 673 struct wb_softc *sc; 674 u_int32_t media; 675{ 676 int i, restart = 0; 677 678 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 679 restart = 1; 680 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 681 682 for (i = 0; i < WB_TIMEOUT; i++) { 683 DELAY(10); 684 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 685 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 686 break; 687 } 688 689 if (i == WB_TIMEOUT) 690 printf("wb%d: failed to force tx and " 691 "rx to idle state\n", sc->wb_unit); 692 } 693 694 if (IFM_SUBTYPE(media) == IFM_10_T) 695 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 696 else 697 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 698 699 if ((media & IFM_GMASK) == IFM_FDX) 700 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 701 else 702 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 703 704 if (restart) 705 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 706 707 return; 708} 709 710static void wb_reset(sc) 711 struct wb_softc *sc; 712{ 713 register int i; 714 struct mii_data *mii; 715 716 CSR_WRITE_4(sc, WB_NETCFG, 0); 717 CSR_WRITE_4(sc, WB_BUSCTL, 0); 718 CSR_WRITE_4(sc, WB_TXADDR, 0); 719 CSR_WRITE_4(sc, WB_RXADDR, 0); 720 721 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 722 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 723 724 for (i = 0; i < WB_TIMEOUT; i++) { 725 DELAY(10); 726 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 727 break; 728 } 729 if (i == WB_TIMEOUT) 730 printf("wb%d: reset never completed!\n", sc->wb_unit); 731 732 /* Wait a little while for the chip to get its brains in order. */ 733 DELAY(1000); 734 735 if (sc->wb_miibus == NULL) 736 return; 737 738 mii = device_get_softc(sc->wb_miibus); 739 if (mii == NULL) 740 return; 741 742 if (mii->mii_instance) { 743 struct mii_softc *miisc; 744 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 745 mii_phy_reset(miisc); 746 } 747 748 return; 749} 750 751static void wb_fixmedia(sc) 752 struct wb_softc *sc; 753{ 754 struct mii_data *mii = NULL; 755 struct ifnet *ifp; 756 u_int32_t media; 757 758 if (sc->wb_miibus == NULL) 759 return; 760 761 mii = device_get_softc(sc->wb_miibus); 762 ifp = &sc->arpcom.ac_if; 763 764 mii_pollstat(mii); 765 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 766 media = mii->mii_media_active & ~IFM_10_T; 767 media |= IFM_100_TX; 768 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 769 media = mii->mii_media_active & ~IFM_100_TX; 770 media |= IFM_10_T; 771 } else 772 return; 773 774 ifmedia_set(&mii->mii_media, media); 775 776 return; 777} 778 779/* 780 * Probe for a Winbond chip. Check the PCI vendor and device 781 * IDs against our list and return a device name if we find a match. 782 */ 783static int wb_probe(dev) 784 device_t dev; 785{ 786 struct wb_type *t; 787 788 t = wb_devs; 789 790 while(t->wb_name != NULL) { 791 if ((pci_get_vendor(dev) == t->wb_vid) && 792 (pci_get_device(dev) == t->wb_did)) { 793 device_set_desc(dev, t->wb_name); 794 return(0); 795 } 796 t++; 797 } 798 799 return(ENXIO); 800} 801 802/* 803 * Attach the interface. Allocate softc structures, do ifmedia 804 * setup and ethernet/BPF attach. 805 */ 806static int wb_attach(dev) 807 device_t dev; 808{ 809 u_char eaddr[ETHER_ADDR_LEN]; 810 u_int32_t command; 811 struct wb_softc *sc; 812 struct ifnet *ifp; 813 int unit, error = 0, rid; 814 815 sc = device_get_softc(dev); 816 unit = device_get_unit(dev); 817 818 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 819 WB_LOCK(sc); 820 821 /* 822 * Handle power management nonsense. 823 */ 824 825 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 826 u_int32_t iobase, membase, irq; 827 828 /* Save important PCI config data. */ 829 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 830 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 831 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 832 833 /* Reset the power state. */ 834 printf("wb%d: chip is in D%d power mode " 835 "-- setting to D0\n", unit, 836 pci_get_powerstate(dev)); 837 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 838 839 /* Restore PCI config data. */ 840 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 841 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 842 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 843 } 844 845 /* 846 * Map control/status registers. 847 */ 848 pci_enable_busmaster(dev); 849 pci_enable_io(dev, SYS_RES_IOPORT); 850 pci_enable_io(dev, SYS_RES_MEMORY); 851 command = pci_read_config(dev, PCIR_COMMAND, 4); 852 853#ifdef WB_USEIOSPACE 854 if (!(command & PCIM_CMD_PORTEN)) { 855 printf("wb%d: failed to enable I/O ports!\n", unit); 856 error = ENXIO; 857 goto fail; 858 } 859#else 860 if (!(command & PCIM_CMD_MEMEN)) { 861 printf("wb%d: failed to enable memory mapping!\n", unit); 862 error = ENXIO; 863 goto fail; 864 } 865#endif 866 867 rid = WB_RID; 868 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 869 0, ~0, 1, RF_ACTIVE); 870 871 if (sc->wb_res == NULL) { 872 printf("wb%d: couldn't map ports/memory\n", unit); 873 error = ENXIO; 874 goto fail; 875 } 876 877 sc->wb_btag = rman_get_bustag(sc->wb_res); 878 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 879 880 /* Allocate interrupt */ 881 rid = 0; 882 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 883 RF_SHAREABLE | RF_ACTIVE); 884 885 if (sc->wb_irq == NULL) { 886 printf("wb%d: couldn't map interrupt\n", unit); 887 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 888 error = ENXIO; 889 goto fail; 890 } 891 892 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 893 wb_intr, sc, &sc->wb_intrhand); 894 895 if (error) { 896 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 897 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 898 printf("wb%d: couldn't set up irq\n", unit); 899 goto fail; 900 } 901 902 /* Save the cache line size. */ 903 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 904 905 /* Reset the adapter. */ 906 wb_reset(sc); 907 908 /* 909 * Get station address from the EEPROM. 910 */ 911 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 912 913 /* 914 * A Winbond chip was detected. Inform the world. 915 */ 916 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 917 918 sc->wb_unit = unit; 919 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 920 921 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 922 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 923 924 if (sc->wb_ldata == NULL) { 925 printf("wb%d: no memory for list buffers!\n", unit); 926 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 927 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 928 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 929 error = ENXIO; 930 goto fail; 931 } 932 933 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 934 935 ifp = &sc->arpcom.ac_if; 936 ifp->if_softc = sc; 937 ifp->if_unit = unit; 938 ifp->if_name = "wb"; 939 ifp->if_mtu = ETHERMTU; 940 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 941 ifp->if_ioctl = wb_ioctl; 942 ifp->if_output = ether_output; 943 ifp->if_start = wb_start; 944 ifp->if_watchdog = wb_watchdog; 945 ifp->if_init = wb_init; 946 ifp->if_baudrate = 10000000; 947 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 948 949 /* 950 * Do MII setup. 951 */ 952 if (mii_phy_probe(dev, &sc->wb_miibus, 953 wb_ifmedia_upd, wb_ifmedia_sts)) { 954 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 955 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 956 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 957 free(sc->wb_ldata_ptr, M_DEVBUF); 958 error = ENXIO; 959 goto fail; 960 } 961 962 /* 963 * Call MI attach routine. 964 */ 965 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 966 WB_UNLOCK(sc); 967 return(0); 968 969fail: 970 if (error) 971 device_delete_child(dev, sc->wb_miibus); 972 WB_UNLOCK(sc); 973 mtx_destroy(&sc->wb_mtx); 974 975 return(error); 976} 977 978static int wb_detach(dev) 979 device_t dev; 980{ 981 struct wb_softc *sc; 982 struct ifnet *ifp; 983 984 sc = device_get_softc(dev); 985 WB_LOCK(sc); 986 ifp = &sc->arpcom.ac_if; 987 988 wb_stop(sc); 989 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 990 991 /* Delete any miibus and phy devices attached to this interface */ 992 bus_generic_detach(dev); 993 device_delete_child(dev, sc->wb_miibus); 994 995 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 996 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 997 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 998 999 free(sc->wb_ldata_ptr, M_DEVBUF); 1000 1001 WB_UNLOCK(sc); 1002 mtx_destroy(&sc->wb_mtx); 1003 1004 return(0); 1005} 1006 1007/* 1008 * Initialize the transmit descriptors. 1009 */ 1010static int wb_list_tx_init(sc) 1011 struct wb_softc *sc; 1012{ 1013 struct wb_chain_data *cd; 1014 struct wb_list_data *ld; 1015 int i; 1016 1017 cd = &sc->wb_cdata; 1018 ld = sc->wb_ldata; 1019 1020 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1021 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1022 if (i == (WB_TX_LIST_CNT - 1)) { 1023 cd->wb_tx_chain[i].wb_nextdesc = 1024 &cd->wb_tx_chain[0]; 1025 } else { 1026 cd->wb_tx_chain[i].wb_nextdesc = 1027 &cd->wb_tx_chain[i + 1]; 1028 } 1029 } 1030 1031 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1032 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1033 1034 return(0); 1035} 1036 1037 1038/* 1039 * Initialize the RX descriptors and allocate mbufs for them. Note that 1040 * we arrange the descriptors in a closed ring, so that the last descriptor 1041 * points back to the first. 1042 */ 1043static int wb_list_rx_init(sc) 1044 struct wb_softc *sc; 1045{ 1046 struct wb_chain_data *cd; 1047 struct wb_list_data *ld; 1048 int i; 1049 1050 cd = &sc->wb_cdata; 1051 ld = sc->wb_ldata; 1052 1053 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1054 cd->wb_rx_chain[i].wb_ptr = 1055 (struct wb_desc *)&ld->wb_rx_list[i]; 1056 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1057 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1058 return(ENOBUFS); 1059 if (i == (WB_RX_LIST_CNT - 1)) { 1060 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1061 ld->wb_rx_list[i].wb_next = 1062 vtophys(&ld->wb_rx_list[0]); 1063 } else { 1064 cd->wb_rx_chain[i].wb_nextdesc = 1065 &cd->wb_rx_chain[i + 1]; 1066 ld->wb_rx_list[i].wb_next = 1067 vtophys(&ld->wb_rx_list[i + 1]); 1068 } 1069 } 1070 1071 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1072 1073 return(0); 1074} 1075 1076static void wb_bfree(buf, args) 1077 caddr_t buf; 1078 void *args; 1079{ 1080 return; 1081} 1082 1083/* 1084 * Initialize an RX descriptor and attach an MBUF cluster. 1085 */ 1086static int wb_newbuf(sc, c, m) 1087 struct wb_softc *sc; 1088 struct wb_chain_onefrag *c; 1089 struct mbuf *m; 1090{ 1091 struct mbuf *m_new = NULL; 1092 1093 if (m == NULL) { 1094 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1095 if (m_new == NULL) 1096 return(ENOBUFS); 1097 m_new->m_data = c->wb_buf; 1098 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1099 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1100 EXT_NET_DRV); 1101 } else { 1102 m_new = m; 1103 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1104 m_new->m_data = m_new->m_ext.ext_buf; 1105 } 1106 1107 m_adj(m_new, sizeof(u_int64_t)); 1108 1109 c->wb_mbuf = m_new; 1110 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1111 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1112 c->wb_ptr->wb_status = WB_RXSTAT; 1113 1114 return(0); 1115} 1116 1117/* 1118 * A frame has been uploaded: pass the resulting mbuf chain up to 1119 * the higher level protocols. 1120 */ 1121static void wb_rxeof(sc) 1122 struct wb_softc *sc; 1123{ 1124 struct ether_header *eh; 1125 struct mbuf *m = NULL; 1126 struct ifnet *ifp; 1127 struct wb_chain_onefrag *cur_rx; 1128 int total_len = 0; 1129 u_int32_t rxstat; 1130 1131 ifp = &sc->arpcom.ac_if; 1132 1133 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1134 WB_RXSTAT_OWN)) { 1135 struct mbuf *m0 = NULL; 1136 1137 cur_rx = sc->wb_cdata.wb_rx_head; 1138 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1139 1140 m = cur_rx->wb_mbuf; 1141 1142 if ((rxstat & WB_RXSTAT_MIIERR) || 1143 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1144 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1145 !(rxstat & WB_RXSTAT_LASTFRAG) || 1146 !(rxstat & WB_RXSTAT_RXCMP)) { 1147 ifp->if_ierrors++; 1148 wb_newbuf(sc, cur_rx, m); 1149 printf("wb%x: receiver babbling: possible chip " 1150 "bug, forcing reset\n", sc->wb_unit); 1151 wb_fixmedia(sc); 1152 wb_reset(sc); 1153 wb_init(sc); 1154 return; 1155 } 1156 1157 if (rxstat & WB_RXSTAT_RXERR) { 1158 ifp->if_ierrors++; 1159 wb_newbuf(sc, cur_rx, m); 1160 break; 1161 } 1162 1163 /* No errors; receive the packet. */ 1164 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1165 1166 /* 1167 * XXX The Winbond chip includes the CRC with every 1168 * received frame, and there's no way to turn this 1169 * behavior off (at least, I can't find anything in 1170 * the manual that explains how to do it) so we have 1171 * to trim off the CRC manually. 1172 */ 1173 total_len -= ETHER_CRC_LEN; 1174 1175 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1176 NULL); 1177 wb_newbuf(sc, cur_rx, m); 1178 if (m0 == NULL) { 1179 ifp->if_ierrors++; 1180 break; 1181 } 1182 m = m0; 1183 1184 ifp->if_ipackets++; 1185 eh = mtod(m, struct ether_header *); 1186 1187 /* Remove header from mbuf and pass it on. */ 1188 m_adj(m, sizeof(struct ether_header)); 1189 ether_input(ifp, eh, m); 1190 } 1191} 1192 1193void wb_rxeoc(sc) 1194 struct wb_softc *sc; 1195{ 1196 wb_rxeof(sc); 1197 1198 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1199 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1200 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1201 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1202 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1203 1204 return; 1205} 1206 1207/* 1208 * A frame was downloaded to the chip. It's safe for us to clean up 1209 * the list buffers. 1210 */ 1211static void wb_txeof(sc) 1212 struct wb_softc *sc; 1213{ 1214 struct wb_chain *cur_tx; 1215 struct ifnet *ifp; 1216 1217 ifp = &sc->arpcom.ac_if; 1218 1219 /* Clear the timeout timer. */ 1220 ifp->if_timer = 0; 1221 1222 if (sc->wb_cdata.wb_tx_head == NULL) 1223 return; 1224 1225 /* 1226 * Go through our tx list and free mbufs for those 1227 * frames that have been transmitted. 1228 */ 1229 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1230 u_int32_t txstat; 1231 1232 cur_tx = sc->wb_cdata.wb_tx_head; 1233 txstat = WB_TXSTATUS(cur_tx); 1234 1235 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1236 break; 1237 1238 if (txstat & WB_TXSTAT_TXERR) { 1239 ifp->if_oerrors++; 1240 if (txstat & WB_TXSTAT_ABORT) 1241 ifp->if_collisions++; 1242 if (txstat & WB_TXSTAT_LATECOLL) 1243 ifp->if_collisions++; 1244 } 1245 1246 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1247 1248 ifp->if_opackets++; 1249 m_freem(cur_tx->wb_mbuf); 1250 cur_tx->wb_mbuf = NULL; 1251 1252 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1253 sc->wb_cdata.wb_tx_head = NULL; 1254 sc->wb_cdata.wb_tx_tail = NULL; 1255 break; 1256 } 1257 1258 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1259 } 1260 1261 return; 1262} 1263 1264/* 1265 * TX 'end of channel' interrupt handler. 1266 */ 1267static void wb_txeoc(sc) 1268 struct wb_softc *sc; 1269{ 1270 struct ifnet *ifp; 1271 1272 ifp = &sc->arpcom.ac_if; 1273 1274 ifp->if_timer = 0; 1275 1276 if (sc->wb_cdata.wb_tx_head == NULL) { 1277 ifp->if_flags &= ~IFF_OACTIVE; 1278 sc->wb_cdata.wb_tx_tail = NULL; 1279 } else { 1280 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1281 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1282 ifp->if_timer = 5; 1283 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1284 } 1285 } 1286 1287 return; 1288} 1289 1290static void wb_intr(arg) 1291 void *arg; 1292{ 1293 struct wb_softc *sc; 1294 struct ifnet *ifp; 1295 u_int32_t status; 1296 1297 sc = arg; 1298 WB_LOCK(sc); 1299 ifp = &sc->arpcom.ac_if; 1300 1301 if (!(ifp->if_flags & IFF_UP)) { 1302 WB_UNLOCK(sc); 1303 return; 1304 } 1305 1306 /* Disable interrupts. */ 1307 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1308 1309 for (;;) { 1310 1311 status = CSR_READ_4(sc, WB_ISR); 1312 if (status) 1313 CSR_WRITE_4(sc, WB_ISR, status); 1314 1315 if ((status & WB_INTRS) == 0) 1316 break; 1317 1318 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1319 ifp->if_ierrors++; 1320 wb_reset(sc); 1321 if (status & WB_ISR_RX_ERR) 1322 wb_fixmedia(sc); 1323 wb_init(sc); 1324 continue; 1325 } 1326 1327 if (status & WB_ISR_RX_OK) 1328 wb_rxeof(sc); 1329 1330 if (status & WB_ISR_RX_IDLE) 1331 wb_rxeoc(sc); 1332 1333 if (status & WB_ISR_TX_OK) 1334 wb_txeof(sc); 1335 1336 if (status & WB_ISR_TX_NOBUF) 1337 wb_txeoc(sc); 1338 1339 if (status & WB_ISR_TX_IDLE) { 1340 wb_txeof(sc); 1341 if (sc->wb_cdata.wb_tx_head != NULL) { 1342 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1343 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1344 } 1345 } 1346 1347 if (status & WB_ISR_TX_UNDERRUN) { 1348 ifp->if_oerrors++; 1349 wb_txeof(sc); 1350 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1351 /* Jack up TX threshold */ 1352 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1353 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1354 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1355 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1356 } 1357 1358 if (status & WB_ISR_BUS_ERR) { 1359 wb_reset(sc); 1360 wb_init(sc); 1361 } 1362 1363 } 1364 1365 /* Re-enable interrupts. */ 1366 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1367 1368 if (ifp->if_snd.ifq_head != NULL) { 1369 wb_start(ifp); 1370 } 1371 1372 WB_UNLOCK(sc); 1373 1374 return; 1375} 1376 1377static void wb_tick(xsc) 1378 void *xsc; 1379{ 1380 struct wb_softc *sc; 1381 struct mii_data *mii; 1382 1383 sc = xsc; 1384 WB_LOCK(sc); 1385 mii = device_get_softc(sc->wb_miibus); 1386 1387 mii_tick(mii); 1388 1389 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1390 1391 WB_UNLOCK(sc); 1392 1393 return; 1394} 1395 1396/* 1397 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1398 * pointers to the fragment pointers. 1399 */ 1400static int wb_encap(sc, c, m_head) 1401 struct wb_softc *sc; 1402 struct wb_chain *c; 1403 struct mbuf *m_head; 1404{ 1405 int frag = 0; 1406 struct wb_desc *f = NULL; 1407 int total_len; 1408 struct mbuf *m; 1409 1410 /* 1411 * Start packing the mbufs in this chain into 1412 * the fragment pointers. Stop when we run out 1413 * of fragments or hit the end of the mbuf chain. 1414 */ 1415 m = m_head; 1416 total_len = 0; 1417 1418 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1419 if (m->m_len != 0) { 1420 if (frag == WB_MAXFRAGS) 1421 break; 1422 total_len += m->m_len; 1423 f = &c->wb_ptr->wb_frag[frag]; 1424 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1425 if (frag == 0) { 1426 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1427 f->wb_status = 0; 1428 } else 1429 f->wb_status = WB_TXSTAT_OWN; 1430 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1431 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1432 frag++; 1433 } 1434 } 1435 1436 /* 1437 * Handle special case: we used up all 16 fragments, 1438 * but we have more mbufs left in the chain. Copy the 1439 * data into an mbuf cluster. Note that we don't 1440 * bother clearing the values in the other fragment 1441 * pointers/counters; it wouldn't gain us anything, 1442 * and would waste cycles. 1443 */ 1444 if (m != NULL) { 1445 struct mbuf *m_new = NULL; 1446 1447 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1448 if (m_new == NULL) 1449 return(1); 1450 if (m_head->m_pkthdr.len > MHLEN) { 1451 MCLGET(m_new, M_DONTWAIT); 1452 if (!(m_new->m_flags & M_EXT)) { 1453 m_freem(m_new); 1454 return(1); 1455 } 1456 } 1457 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1458 mtod(m_new, caddr_t)); 1459 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1460 m_freem(m_head); 1461 m_head = m_new; 1462 f = &c->wb_ptr->wb_frag[0]; 1463 f->wb_status = 0; 1464 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1465 f->wb_ctl = total_len = m_new->m_len; 1466 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1467 frag = 1; 1468 } 1469 1470 if (total_len < WB_MIN_FRAMELEN) { 1471 f = &c->wb_ptr->wb_frag[frag]; 1472 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1473 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1474 f->wb_ctl |= WB_TXCTL_TLINK; 1475 f->wb_status = WB_TXSTAT_OWN; 1476 frag++; 1477 } 1478 1479 c->wb_mbuf = m_head; 1480 c->wb_lastdesc = frag - 1; 1481 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1482 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1483 1484 return(0); 1485} 1486 1487/* 1488 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1489 * to the mbuf data regions directly in the transmit lists. We also save a 1490 * copy of the pointers since the transmit list fragment pointers are 1491 * physical addresses. 1492 */ 1493 1494static void wb_start(ifp) 1495 struct ifnet *ifp; 1496{ 1497 struct wb_softc *sc; 1498 struct mbuf *m_head = NULL; 1499 struct wb_chain *cur_tx = NULL, *start_tx; 1500 1501 sc = ifp->if_softc; 1502 WB_LOCK(sc); 1503 1504 /* 1505 * Check for an available queue slot. If there are none, 1506 * punt. 1507 */ 1508 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1509 ifp->if_flags |= IFF_OACTIVE; 1510 WB_UNLOCK(sc); 1511 return; 1512 } 1513 1514 start_tx = sc->wb_cdata.wb_tx_free; 1515 1516 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1517 IF_DEQUEUE(&ifp->if_snd, m_head); 1518 if (m_head == NULL) 1519 break; 1520 1521 /* Pick a descriptor off the free list. */ 1522 cur_tx = sc->wb_cdata.wb_tx_free; 1523 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1524 1525 /* Pack the data into the descriptor. */ 1526 wb_encap(sc, cur_tx, m_head); 1527 1528 if (cur_tx != start_tx) 1529 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1530 1531 /* 1532 * If there's a BPF listener, bounce a copy of this frame 1533 * to him. 1534 */ 1535 if (ifp->if_bpf) 1536 bpf_mtap(ifp, cur_tx->wb_mbuf); 1537 } 1538 1539 /* 1540 * If there are no packets queued, bail. 1541 */ 1542 if (cur_tx == NULL) { 1543 WB_UNLOCK(sc); 1544 return; 1545 } 1546 1547 /* 1548 * Place the request for the upload interrupt 1549 * in the last descriptor in the chain. This way, if 1550 * we're chaining several packets at once, we'll only 1551 * get an interupt once for the whole chain rather than 1552 * once for each packet. 1553 */ 1554 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1555 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1556 sc->wb_cdata.wb_tx_tail = cur_tx; 1557 1558 if (sc->wb_cdata.wb_tx_head == NULL) { 1559 sc->wb_cdata.wb_tx_head = start_tx; 1560 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1561 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1562 } else { 1563 /* 1564 * We need to distinguish between the case where 1565 * the own bit is clear because the chip cleared it 1566 * and where the own bit is clear because we haven't 1567 * set it yet. The magic value WB_UNSET is just some 1568 * ramdomly chosen number which doesn't have the own 1569 * bit set. When we actually transmit the frame, the 1570 * status word will have _only_ the own bit set, so 1571 * the txeoc handler will be able to tell if it needs 1572 * to initiate another transmission to flush out pending 1573 * frames. 1574 */ 1575 WB_TXOWN(start_tx) = WB_UNSENT; 1576 } 1577 1578 /* 1579 * Set a timeout in case the chip goes out to lunch. 1580 */ 1581 ifp->if_timer = 5; 1582 WB_UNLOCK(sc); 1583 1584 return; 1585} 1586 1587static void wb_init(xsc) 1588 void *xsc; 1589{ 1590 struct wb_softc *sc = xsc; 1591 struct ifnet *ifp = &sc->arpcom.ac_if; 1592 int i; 1593 struct mii_data *mii; 1594 1595 WB_LOCK(sc); 1596 mii = device_get_softc(sc->wb_miibus); 1597 1598 /* 1599 * Cancel pending I/O and free all RX/TX buffers. 1600 */ 1601 wb_stop(sc); 1602 wb_reset(sc); 1603 1604 sc->wb_txthresh = WB_TXTHRESH_INIT; 1605 1606 /* 1607 * Set cache alignment and burst length. 1608 */ 1609#ifdef foo 1610 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1611 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1612 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1613#endif 1614 1615 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1616 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1617 switch(sc->wb_cachesize) { 1618 case 32: 1619 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1620 break; 1621 case 16: 1622 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1623 break; 1624 case 8: 1625 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1626 break; 1627 case 0: 1628 default: 1629 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1630 break; 1631 } 1632 1633 /* This doesn't tend to work too well at 100Mbps. */ 1634 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1635 1636 /* Init our MAC address */ 1637 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1638 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1639 } 1640 1641 /* Init circular RX list. */ 1642 if (wb_list_rx_init(sc) == ENOBUFS) { 1643 printf("wb%d: initialization failed: no " 1644 "memory for rx buffers\n", sc->wb_unit); 1645 wb_stop(sc); 1646 WB_UNLOCK(sc); 1647 return; 1648 } 1649 1650 /* Init TX descriptors. */ 1651 wb_list_tx_init(sc); 1652 1653 /* If we want promiscuous mode, set the allframes bit. */ 1654 if (ifp->if_flags & IFF_PROMISC) { 1655 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1656 } else { 1657 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1658 } 1659 1660 /* 1661 * Set capture broadcast bit to capture broadcast frames. 1662 */ 1663 if (ifp->if_flags & IFF_BROADCAST) { 1664 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1665 } else { 1666 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1667 } 1668 1669 /* 1670 * Program the multicast filter, if necessary. 1671 */ 1672 wb_setmulti(sc); 1673 1674 /* 1675 * Load the address of the RX list. 1676 */ 1677 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1678 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1679 1680 /* 1681 * Enable interrupts. 1682 */ 1683 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1684 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1685 1686 /* Enable receiver and transmitter. */ 1687 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1688 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1689 1690 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1691 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1692 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1693 1694 mii_mediachg(mii); 1695 1696 ifp->if_flags |= IFF_RUNNING; 1697 ifp->if_flags &= ~IFF_OACTIVE; 1698 1699 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1700 WB_UNLOCK(sc); 1701 1702 return; 1703} 1704 1705/* 1706 * Set media options. 1707 */ 1708static int wb_ifmedia_upd(ifp) 1709 struct ifnet *ifp; 1710{ 1711 struct wb_softc *sc; 1712 1713 sc = ifp->if_softc; 1714 1715 if (ifp->if_flags & IFF_UP) 1716 wb_init(sc); 1717 1718 return(0); 1719} 1720 1721/* 1722 * Report current media status. 1723 */ 1724static void wb_ifmedia_sts(ifp, ifmr) 1725 struct ifnet *ifp; 1726 struct ifmediareq *ifmr; 1727{ 1728 struct wb_softc *sc; 1729 struct mii_data *mii; 1730 1731 sc = ifp->if_softc; 1732 1733 mii = device_get_softc(sc->wb_miibus); 1734 1735 mii_pollstat(mii); 1736 ifmr->ifm_active = mii->mii_media_active; 1737 ifmr->ifm_status = mii->mii_media_status; 1738 1739 return; 1740} 1741 1742static int wb_ioctl(ifp, command, data) 1743 struct ifnet *ifp; 1744 u_long command; 1745 caddr_t data; 1746{ 1747 struct wb_softc *sc = ifp->if_softc; 1748 struct mii_data *mii; 1749 struct ifreq *ifr = (struct ifreq *) data; 1750 int error = 0; 1751 1752 WB_LOCK(sc); 1753 1754 switch(command) { 1755 case SIOCSIFADDR: 1756 case SIOCGIFADDR: 1757 case SIOCSIFMTU: 1758 error = ether_ioctl(ifp, command, data); 1759 break; 1760 case SIOCSIFFLAGS: 1761 if (ifp->if_flags & IFF_UP) { 1762 wb_init(sc); 1763 } else { 1764 if (ifp->if_flags & IFF_RUNNING) 1765 wb_stop(sc); 1766 } 1767 error = 0; 1768 break; 1769 case SIOCADDMULTI: 1770 case SIOCDELMULTI: 1771 wb_setmulti(sc); 1772 error = 0; 1773 break; 1774 case SIOCGIFMEDIA: 1775 case SIOCSIFMEDIA: 1776 mii = device_get_softc(sc->wb_miibus); 1777 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1778 break; 1779 default: 1780 error = EINVAL; 1781 break; 1782 } 1783 1784 WB_UNLOCK(sc); 1785 1786 return(error); 1787} 1788 1789static void wb_watchdog(ifp) 1790 struct ifnet *ifp; 1791{ 1792 struct wb_softc *sc; 1793 1794 sc = ifp->if_softc; 1795 1796 WB_LOCK(sc); 1797 ifp->if_oerrors++; 1798 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1799#ifdef foo 1800 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1801 printf("wb%d: no carrier - transceiver cable problem?\n", 1802 sc->wb_unit); 1803#endif 1804 wb_stop(sc); 1805 wb_reset(sc); 1806 wb_init(sc); 1807 1808 if (ifp->if_snd.ifq_head != NULL) 1809 wb_start(ifp); 1810 WB_UNLOCK(sc); 1811 1812 return; 1813} 1814 1815/* 1816 * Stop the adapter and free any mbufs allocated to the 1817 * RX and TX lists. 1818 */ 1819static void wb_stop(sc) 1820 struct wb_softc *sc; 1821{ 1822 register int i; 1823 struct ifnet *ifp; 1824 1825 WB_LOCK(sc); 1826 ifp = &sc->arpcom.ac_if; 1827 ifp->if_timer = 0; 1828 1829 untimeout(wb_tick, sc, sc->wb_stat_ch); 1830 1831 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1832 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1833 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1834 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1835 1836 /* 1837 * Free data in the RX lists. 1838 */ 1839 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1840 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1841 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1842 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1843 } 1844 } 1845 bzero((char *)&sc->wb_ldata->wb_rx_list, 1846 sizeof(sc->wb_ldata->wb_rx_list)); 1847 1848 /* 1849 * Free the TX list buffers. 1850 */ 1851 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1852 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1853 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1854 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1855 } 1856 } 1857 1858 bzero((char *)&sc->wb_ldata->wb_tx_list, 1859 sizeof(sc->wb_ldata->wb_tx_list)); 1860 1861 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1862 WB_UNLOCK(sc); 1863 1864 return; 1865} 1866 1867/* 1868 * Stop all chip I/O so that the kernel's probe routines don't 1869 * get confused by errant DMAs when rebooting. 1870 */ 1871static void wb_shutdown(dev) 1872 device_t dev; 1873{ 1874 struct wb_softc *sc; 1875 1876 sc = device_get_softc(dev); 1877 wb_stop(sc); 1878 1879 return; 1880} 1881