if_wb.c revision 59758
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_wb.c 59758 2000-04-29 13:41:57Z peter $ 33 */ 34 35/* 36 * Winbond fast ethernet PCI NIC driver 37 * 38 * Supports various cheap network adapters based on the Winbond W89C840F 39 * fast ethernet controller chip. This includes adapters manufactured by 40 * Winbond itself and some made by Linksys. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "opt_bdg.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95#include <sys/queue.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102 103#include <net/bpf.h> 104 105#ifdef BRIDGE 106#include <net/bridge.h> 107#endif 108 109#include <vm/vm.h> /* for vtophys */ 110#include <vm/pmap.h> /* for vtophys */ 111#include <machine/clock.h> /* for DELAY */ 112#include <machine/bus_memio.h> 113#include <machine/bus_pio.h> 114#include <machine/bus.h> 115#include <machine/resource.h> 116#include <sys/bus.h> 117#include <sys/rman.h> 118 119#include <pci/pcireg.h> 120#include <pci/pcivar.h> 121 122#include <dev/mii/mii.h> 123#include <dev/mii/miivar.h> 124 125/* "controller miibus0" required. See GENERIC if you get errors here. */ 126#include "miibus_if.h" 127 128#define WB_USEIOSPACE 129 130#include <pci/if_wbreg.h> 131 132MODULE_DEPEND(wb, miibus, 1, 1, 1); 133 134#ifndef lint 135static const char rcsid[] = 136 "$FreeBSD: head/sys/pci/if_wb.c 59758 2000-04-29 13:41:57Z peter $"; 137#endif 138 139/* 140 * Various supported device vendors/types and their names. 141 */ 142static struct wb_type wb_devs[] = { 143 { WB_VENDORID, WB_DEVICEID_840F, 144 "Winbond W89C840F 10/100BaseTX" }, 145 { CP_VENDORID, CP_DEVICEID_RL100, 146 "Compex RL100-ATX 10/100baseTX" }, 147 { 0, 0, NULL } 148}; 149 150static int wb_probe __P((device_t)); 151static int wb_attach __P((device_t)); 152static int wb_detach __P((device_t)); 153 154static void wb_bfree __P((caddr_t, u_int)); 155static int wb_newbuf __P((struct wb_softc *, 156 struct wb_chain_onefrag *, 157 struct mbuf *)); 158static int wb_encap __P((struct wb_softc *, struct wb_chain *, 159 struct mbuf *)); 160 161static void wb_rxeof __P((struct wb_softc *)); 162static void wb_rxeoc __P((struct wb_softc *)); 163static void wb_txeof __P((struct wb_softc *)); 164static void wb_txeoc __P((struct wb_softc *)); 165static void wb_intr __P((void *)); 166static void wb_tick __P((void *)); 167static void wb_start __P((struct ifnet *)); 168static int wb_ioctl __P((struct ifnet *, u_long, caddr_t)); 169static void wb_init __P((void *)); 170static void wb_stop __P((struct wb_softc *)); 171static void wb_watchdog __P((struct ifnet *)); 172static void wb_shutdown __P((device_t)); 173static int wb_ifmedia_upd __P((struct ifnet *)); 174static void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 175 176static void wb_eeprom_putbyte __P((struct wb_softc *, int)); 177static void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *)); 178static void wb_read_eeprom __P((struct wb_softc *, caddr_t, int, 179 int, int)); 180static void wb_mii_sync __P((struct wb_softc *)); 181static void wb_mii_send __P((struct wb_softc *, u_int32_t, int)); 182static int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *)); 183static int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *)); 184 185static void wb_setcfg __P((struct wb_softc *, u_int32_t)); 186static u_int8_t wb_calchash __P((caddr_t)); 187static void wb_setmulti __P((struct wb_softc *)); 188static void wb_reset __P((struct wb_softc *)); 189static void wb_fixmedia __P((struct wb_softc *)); 190static int wb_list_rx_init __P((struct wb_softc *)); 191static int wb_list_tx_init __P((struct wb_softc *)); 192 193static int wb_miibus_readreg __P((device_t, int, int)); 194static int wb_miibus_writereg __P((device_t, int, int, int)); 195static void wb_miibus_statchg __P((device_t)); 196 197#ifdef WB_USEIOSPACE 198#define WB_RES SYS_RES_IOPORT 199#define WB_RID WB_PCI_LOIO 200#else 201#define WB_RES SYS_RES_MEMORY 202#define WB_RID WB_PCI_LOMEM 203#endif 204 205static device_method_t wb_methods[] = { 206 /* Device interface */ 207 DEVMETHOD(device_probe, wb_probe), 208 DEVMETHOD(device_attach, wb_attach), 209 DEVMETHOD(device_detach, wb_detach), 210 DEVMETHOD(device_shutdown, wb_shutdown), 211 212 /* bus interface, for miibus */ 213 DEVMETHOD(bus_print_child, bus_generic_print_child), 214 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 215 216 /* MII interface */ 217 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 218 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 219 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 220 { 0, 0 } 221}; 222 223static driver_t wb_driver = { 224 "wb", 225 wb_methods, 226 sizeof(struct wb_softc) 227}; 228 229static devclass_t wb_devclass; 230 231DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 232DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 233 234#define WB_SETBIT(sc, reg, x) \ 235 CSR_WRITE_4(sc, reg, \ 236 CSR_READ_4(sc, reg) | x) 237 238#define WB_CLRBIT(sc, reg, x) \ 239 CSR_WRITE_4(sc, reg, \ 240 CSR_READ_4(sc, reg) & ~x) 241 242#define SIO_SET(x) \ 243 CSR_WRITE_4(sc, WB_SIO, \ 244 CSR_READ_4(sc, WB_SIO) | x) 245 246#define SIO_CLR(x) \ 247 CSR_WRITE_4(sc, WB_SIO, \ 248 CSR_READ_4(sc, WB_SIO) & ~x) 249 250/* 251 * Send a read command and address to the EEPROM, check for ACK. 252 */ 253static void wb_eeprom_putbyte(sc, addr) 254 struct wb_softc *sc; 255 int addr; 256{ 257 register int d, i; 258 259 d = addr | WB_EECMD_READ; 260 261 /* 262 * Feed in each bit and stobe the clock. 263 */ 264 for (i = 0x400; i; i >>= 1) { 265 if (d & i) { 266 SIO_SET(WB_SIO_EE_DATAIN); 267 } else { 268 SIO_CLR(WB_SIO_EE_DATAIN); 269 } 270 DELAY(100); 271 SIO_SET(WB_SIO_EE_CLK); 272 DELAY(150); 273 SIO_CLR(WB_SIO_EE_CLK); 274 DELAY(100); 275 } 276 277 return; 278} 279 280/* 281 * Read a word of data stored in the EEPROM at address 'addr.' 282 */ 283static void wb_eeprom_getword(sc, addr, dest) 284 struct wb_softc *sc; 285 int addr; 286 u_int16_t *dest; 287{ 288 register int i; 289 u_int16_t word = 0; 290 291 /* Enter EEPROM access mode. */ 292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 293 294 /* 295 * Send address of word we want to read. 296 */ 297 wb_eeprom_putbyte(sc, addr); 298 299 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 300 301 /* 302 * Start reading bits from EEPROM. 303 */ 304 for (i = 0x8000; i; i >>= 1) { 305 SIO_SET(WB_SIO_EE_CLK); 306 DELAY(100); 307 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 308 word |= i; 309 SIO_CLR(WB_SIO_EE_CLK); 310 DELAY(100); 311 } 312 313 /* Turn off EEPROM access mode. */ 314 CSR_WRITE_4(sc, WB_SIO, 0); 315 316 *dest = word; 317 318 return; 319} 320 321/* 322 * Read a sequence of words from the EEPROM. 323 */ 324static void wb_read_eeprom(sc, dest, off, cnt, swap) 325 struct wb_softc *sc; 326 caddr_t dest; 327 int off; 328 int cnt; 329 int swap; 330{ 331 int i; 332 u_int16_t word = 0, *ptr; 333 334 for (i = 0; i < cnt; i++) { 335 wb_eeprom_getword(sc, off + i, &word); 336 ptr = (u_int16_t *)(dest + (i * 2)); 337 if (swap) 338 *ptr = ntohs(word); 339 else 340 *ptr = word; 341 } 342 343 return; 344} 345 346/* 347 * Sync the PHYs by setting data bit and strobing the clock 32 times. 348 */ 349static void wb_mii_sync(sc) 350 struct wb_softc *sc; 351{ 352 register int i; 353 354 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 355 356 for (i = 0; i < 32; i++) { 357 SIO_SET(WB_SIO_MII_CLK); 358 DELAY(1); 359 SIO_CLR(WB_SIO_MII_CLK); 360 DELAY(1); 361 } 362 363 return; 364} 365 366/* 367 * Clock a series of bits through the MII. 368 */ 369static void wb_mii_send(sc, bits, cnt) 370 struct wb_softc *sc; 371 u_int32_t bits; 372 int cnt; 373{ 374 int i; 375 376 SIO_CLR(WB_SIO_MII_CLK); 377 378 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 379 if (bits & i) { 380 SIO_SET(WB_SIO_MII_DATAIN); 381 } else { 382 SIO_CLR(WB_SIO_MII_DATAIN); 383 } 384 DELAY(1); 385 SIO_CLR(WB_SIO_MII_CLK); 386 DELAY(1); 387 SIO_SET(WB_SIO_MII_CLK); 388 } 389} 390 391/* 392 * Read an PHY register through the MII. 393 */ 394static int wb_mii_readreg(sc, frame) 395 struct wb_softc *sc; 396 struct wb_mii_frame *frame; 397 398{ 399 int i, ack, s; 400 401 s = splimp(); 402 403 /* 404 * Set up frame for RX. 405 */ 406 frame->mii_stdelim = WB_MII_STARTDELIM; 407 frame->mii_opcode = WB_MII_READOP; 408 frame->mii_turnaround = 0; 409 frame->mii_data = 0; 410 411 CSR_WRITE_4(sc, WB_SIO, 0); 412 413 /* 414 * Turn on data xmit. 415 */ 416 SIO_SET(WB_SIO_MII_DIR); 417 418 wb_mii_sync(sc); 419 420 /* 421 * Send command/address info. 422 */ 423 wb_mii_send(sc, frame->mii_stdelim, 2); 424 wb_mii_send(sc, frame->mii_opcode, 2); 425 wb_mii_send(sc, frame->mii_phyaddr, 5); 426 wb_mii_send(sc, frame->mii_regaddr, 5); 427 428 /* Idle bit */ 429 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 430 DELAY(1); 431 SIO_SET(WB_SIO_MII_CLK); 432 DELAY(1); 433 434 /* Turn off xmit. */ 435 SIO_CLR(WB_SIO_MII_DIR); 436 /* Check for ack */ 437 SIO_CLR(WB_SIO_MII_CLK); 438 DELAY(1); 439 SIO_SET(WB_SIO_MII_CLK); 440 DELAY(1); 441 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 442 SIO_CLR(WB_SIO_MII_CLK); 443 DELAY(1); 444 SIO_SET(WB_SIO_MII_CLK); 445 DELAY(1); 446 447 /* 448 * Now try reading data bits. If the ack failed, we still 449 * need to clock through 16 cycles to keep the PHY(s) in sync. 450 */ 451 if (ack) { 452 for(i = 0; i < 16; i++) { 453 SIO_CLR(WB_SIO_MII_CLK); 454 DELAY(1); 455 SIO_SET(WB_SIO_MII_CLK); 456 DELAY(1); 457 } 458 goto fail; 459 } 460 461 for (i = 0x8000; i; i >>= 1) { 462 SIO_CLR(WB_SIO_MII_CLK); 463 DELAY(1); 464 if (!ack) { 465 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 466 frame->mii_data |= i; 467 DELAY(1); 468 } 469 SIO_SET(WB_SIO_MII_CLK); 470 DELAY(1); 471 } 472 473fail: 474 475 SIO_CLR(WB_SIO_MII_CLK); 476 DELAY(1); 477 SIO_SET(WB_SIO_MII_CLK); 478 DELAY(1); 479 480 splx(s); 481 482 if (ack) 483 return(1); 484 return(0); 485} 486 487/* 488 * Write to a PHY register through the MII. 489 */ 490static int wb_mii_writereg(sc, frame) 491 struct wb_softc *sc; 492 struct wb_mii_frame *frame; 493 494{ 495 int s; 496 497 s = splimp(); 498 /* 499 * Set up frame for TX. 500 */ 501 502 frame->mii_stdelim = WB_MII_STARTDELIM; 503 frame->mii_opcode = WB_MII_WRITEOP; 504 frame->mii_turnaround = WB_MII_TURNAROUND; 505 506 /* 507 * Turn on data output. 508 */ 509 SIO_SET(WB_SIO_MII_DIR); 510 511 wb_mii_sync(sc); 512 513 wb_mii_send(sc, frame->mii_stdelim, 2); 514 wb_mii_send(sc, frame->mii_opcode, 2); 515 wb_mii_send(sc, frame->mii_phyaddr, 5); 516 wb_mii_send(sc, frame->mii_regaddr, 5); 517 wb_mii_send(sc, frame->mii_turnaround, 2); 518 wb_mii_send(sc, frame->mii_data, 16); 519 520 /* Idle bit. */ 521 SIO_SET(WB_SIO_MII_CLK); 522 DELAY(1); 523 SIO_CLR(WB_SIO_MII_CLK); 524 DELAY(1); 525 526 /* 527 * Turn off xmit. 528 */ 529 SIO_CLR(WB_SIO_MII_DIR); 530 531 splx(s); 532 533 return(0); 534} 535 536static int wb_miibus_readreg(dev, phy, reg) 537 device_t dev; 538 int phy, reg; 539{ 540 struct wb_softc *sc; 541 struct wb_mii_frame frame; 542 543 sc = device_get_softc(dev); 544 545 bzero((char *)&frame, sizeof(frame)); 546 547 frame.mii_phyaddr = phy; 548 frame.mii_regaddr = reg; 549 wb_mii_readreg(sc, &frame); 550 551 return(frame.mii_data); 552} 553 554static int wb_miibus_writereg(dev, phy, reg, data) 555 device_t dev; 556 int phy, reg, data; 557{ 558 struct wb_softc *sc; 559 struct wb_mii_frame frame; 560 561 sc = device_get_softc(dev); 562 563 bzero((char *)&frame, sizeof(frame)); 564 565 frame.mii_phyaddr = phy; 566 frame.mii_regaddr = reg; 567 frame.mii_data = data; 568 569 wb_mii_writereg(sc, &frame); 570 571 return(0); 572} 573 574static void wb_miibus_statchg(dev) 575 device_t dev; 576{ 577 struct wb_softc *sc; 578 struct mii_data *mii; 579 580 sc = device_get_softc(dev); 581 mii = device_get_softc(sc->wb_miibus); 582 wb_setcfg(sc, mii->mii_media_active); 583 584 return; 585} 586 587static u_int8_t wb_calchash(addr) 588 caddr_t addr; 589{ 590 u_int32_t crc, carry; 591 int i, j; 592 u_int8_t c; 593 594 /* Compute CRC for the address value. */ 595 crc = 0xFFFFFFFF; /* initial value */ 596 597 for (i = 0; i < 6; i++) { 598 c = *(addr + i); 599 for (j = 0; j < 8; j++) { 600 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 601 crc <<= 1; 602 c >>= 1; 603 if (carry) 604 crc = (crc ^ 0x04c11db6) | carry; 605 } 606 } 607 608 /* 609 * return the filter bit position 610 * Note: I arrived at the following nonsense 611 * through experimentation. It's not the usual way to 612 * generate the bit position but it's the only thing 613 * I could come up with that works. 614 */ 615 return(~(crc >> 26) & 0x0000003F); 616} 617 618/* 619 * Program the 64-bit multicast hash filter. 620 */ 621static void wb_setmulti(sc) 622 struct wb_softc *sc; 623{ 624 struct ifnet *ifp; 625 int h = 0; 626 u_int32_t hashes[2] = { 0, 0 }; 627 struct ifmultiaddr *ifma; 628 u_int32_t rxfilt; 629 int mcnt = 0; 630 631 ifp = &sc->arpcom.ac_if; 632 633 rxfilt = CSR_READ_4(sc, WB_NETCFG); 634 635 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 636 rxfilt |= WB_NETCFG_RX_MULTI; 637 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 638 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 639 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 640 return; 641 } 642 643 /* first, zot all the existing hash bits */ 644 CSR_WRITE_4(sc, WB_MAR0, 0); 645 CSR_WRITE_4(sc, WB_MAR1, 0); 646 647 /* now program new ones */ 648 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 649 ifma = ifma->ifma_link.le_next) { 650 if (ifma->ifma_addr->sa_family != AF_LINK) 651 continue; 652 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 653 if (h < 32) 654 hashes[0] |= (1 << h); 655 else 656 hashes[1] |= (1 << (h - 32)); 657 mcnt++; 658 } 659 660 if (mcnt) 661 rxfilt |= WB_NETCFG_RX_MULTI; 662 else 663 rxfilt &= ~WB_NETCFG_RX_MULTI; 664 665 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 666 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 667 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 668 669 return; 670} 671 672/* 673 * The Winbond manual states that in order to fiddle with the 674 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 675 * first have to put the transmit and/or receive logic in the idle state. 676 */ 677static void wb_setcfg(sc, media) 678 struct wb_softc *sc; 679 u_int32_t media; 680{ 681 int i, restart = 0; 682 683 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 684 restart = 1; 685 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 686 687 for (i = 0; i < WB_TIMEOUT; i++) { 688 DELAY(10); 689 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 690 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 691 break; 692 } 693 694 if (i == WB_TIMEOUT) 695 printf("wb%d: failed to force tx and " 696 "rx to idle state\n", sc->wb_unit); 697 } 698 699 if (IFM_SUBTYPE(media) == IFM_10_T) 700 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 701 else 702 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 703 704 if ((media & IFM_GMASK) == IFM_FDX) 705 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 706 else 707 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 708 709 if (restart) 710 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 711 712 return; 713} 714 715static void wb_reset(sc) 716 struct wb_softc *sc; 717{ 718 register int i; 719 struct mii_data *mii; 720 721 CSR_WRITE_4(sc, WB_NETCFG, 0); 722 CSR_WRITE_4(sc, WB_BUSCTL, 0); 723 CSR_WRITE_4(sc, WB_TXADDR, 0); 724 CSR_WRITE_4(sc, WB_RXADDR, 0); 725 726 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 727 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 728 729 for (i = 0; i < WB_TIMEOUT; i++) { 730 DELAY(10); 731 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 732 break; 733 } 734 if (i == WB_TIMEOUT) 735 printf("wb%d: reset never completed!\n", sc->wb_unit); 736 737 /* Wait a little while for the chip to get its brains in order. */ 738 DELAY(1000); 739 740 if (sc->wb_miibus == NULL) 741 return; 742 743 mii = device_get_softc(sc->wb_miibus); 744 if (mii == NULL) 745 return; 746 747 if (mii->mii_instance) { 748 struct mii_softc *miisc; 749 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 750 miisc = LIST_NEXT(miisc, mii_list)) 751 mii_phy_reset(miisc); 752 } 753 754 return; 755} 756 757static void wb_fixmedia(sc) 758 struct wb_softc *sc; 759{ 760 struct mii_data *mii = NULL; 761 struct ifnet *ifp; 762 u_int32_t media; 763 764 if (sc->wb_miibus == NULL) 765 return; 766 767 mii = device_get_softc(sc->wb_miibus); 768 ifp = &sc->arpcom.ac_if; 769 770 mii_pollstat(mii); 771 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 772 media = mii->mii_media_active & ~IFM_10_T; 773 media |= IFM_100_TX; 774 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 775 media = mii->mii_media_active & ~IFM_100_TX; 776 media |= IFM_10_T; 777 } else 778 return; 779 780 ifmedia_set(&mii->mii_media, media); 781 782 return; 783} 784 785/* 786 * Probe for a Winbond chip. Check the PCI vendor and device 787 * IDs against our list and return a device name if we find a match. 788 */ 789static int wb_probe(dev) 790 device_t dev; 791{ 792 struct wb_type *t; 793 794 t = wb_devs; 795 796 while(t->wb_name != NULL) { 797 if ((pci_get_vendor(dev) == t->wb_vid) && 798 (pci_get_device(dev) == t->wb_did)) { 799 device_set_desc(dev, t->wb_name); 800 return(0); 801 } 802 t++; 803 } 804 805 return(ENXIO); 806} 807 808/* 809 * Attach the interface. Allocate softc structures, do ifmedia 810 * setup and ethernet/BPF attach. 811 */ 812static int wb_attach(dev) 813 device_t dev; 814{ 815 int s; 816 u_char eaddr[ETHER_ADDR_LEN]; 817 u_int32_t command; 818 struct wb_softc *sc; 819 struct ifnet *ifp; 820 int unit, error = 0, rid; 821 822 s = splimp(); 823 824 sc = device_get_softc(dev); 825 unit = device_get_unit(dev); 826 827 /* 828 * Handle power management nonsense. 829 */ 830 831 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF; 832 if (command == 0x01) { 833 834 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4); 835 if (command & WB_PSTATE_MASK) { 836 u_int32_t iobase, membase, irq; 837 838 /* Save important PCI config data. */ 839 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 840 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 841 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 842 843 /* Reset the power state. */ 844 printf("wb%d: chip is in D%d power mode " 845 "-- setting to D0\n", unit, command & WB_PSTATE_MASK); 846 command &= 0xFFFFFFFC; 847 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4); 848 849 /* Restore PCI config data. */ 850 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 851 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 852 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 853 } 854 } 855 856 /* 857 * Map control/status registers. 858 */ 859 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 860 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 861 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 862 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 863 864#ifdef WB_USEIOSPACE 865 if (!(command & PCIM_CMD_PORTEN)) { 866 printf("wb%d: failed to enable I/O ports!\n", unit); 867 error = ENXIO; 868 goto fail; 869 } 870#else 871 if (!(command & PCIM_CMD_MEMEN)) { 872 printf("wb%d: failed to enable memory mapping!\n", unit); 873 error = ENXIO; 874 goto fail; 875 } 876#endif 877 878 rid = WB_RID; 879 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 880 0, ~0, 1, RF_ACTIVE); 881 882 if (sc->wb_res == NULL) { 883 printf("wb%d: couldn't map ports/memory\n", unit); 884 error = ENXIO; 885 goto fail; 886 } 887 888 sc->wb_btag = rman_get_bustag(sc->wb_res); 889 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 890 891 /* Allocate interrupt */ 892 rid = 0; 893 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 894 RF_SHAREABLE | RF_ACTIVE); 895 896 if (sc->wb_irq == NULL) { 897 printf("wb%d: couldn't map interrupt\n", unit); 898 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 899 error = ENXIO; 900 goto fail; 901 } 902 903 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 904 wb_intr, sc, &sc->wb_intrhand); 905 906 if (error) { 907 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 908 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 909 printf("wb%d: couldn't set up irq\n", unit); 910 goto fail; 911 } 912 913 /* Save the cache line size. */ 914 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 915 916 /* Reset the adapter. */ 917 wb_reset(sc); 918 919 /* 920 * Get station address from the EEPROM. 921 */ 922 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 923 924 /* 925 * A Winbond chip was detected. Inform the world. 926 */ 927 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 928 929 sc->wb_unit = unit; 930 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 931 932 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 933 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 934 935 if (sc->wb_ldata == NULL) { 936 printf("wb%d: no memory for list buffers!\n", unit); 937 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 938 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 939 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 940 error = ENXIO; 941 goto fail; 942 } 943 944 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 945 946 ifp = &sc->arpcom.ac_if; 947 ifp->if_softc = sc; 948 ifp->if_unit = unit; 949 ifp->if_name = "wb"; 950 ifp->if_mtu = ETHERMTU; 951 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 952 ifp->if_ioctl = wb_ioctl; 953 ifp->if_output = ether_output; 954 ifp->if_start = wb_start; 955 ifp->if_watchdog = wb_watchdog; 956 ifp->if_init = wb_init; 957 ifp->if_baudrate = 10000000; 958 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 959 960 /* 961 * Do MII setup. 962 */ 963 if (mii_phy_probe(dev, &sc->wb_miibus, 964 wb_ifmedia_upd, wb_ifmedia_sts)) { 965 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 966 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 967 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 968 free(sc->wb_ldata_ptr, M_DEVBUF); 969 error = ENXIO; 970 goto fail; 971 } 972 973 /* 974 * Call MI attach routines. 975 */ 976 if_attach(ifp); 977 ether_ifattach(ifp); 978 979 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 980 981fail: 982 if (error) 983 device_delete_child(dev, sc->wb_miibus); 984 splx(s); 985 986 return(error); 987} 988 989static int wb_detach(dev) 990 device_t dev; 991{ 992 struct wb_softc *sc; 993 struct ifnet *ifp; 994 int s; 995 996 s = splimp(); 997 998 sc = device_get_softc(dev); 999 ifp = &sc->arpcom.ac_if; 1000 1001 wb_stop(sc); 1002 if_detach(ifp); 1003 1004 /* Delete any miibus and phy devices attached to this interface */ 1005 bus_generic_detach(dev); 1006 device_delete_child(dev, sc->wb_miibus); 1007 1008 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 1009 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 1010 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 1011 1012 free(sc->wb_ldata_ptr, M_DEVBUF); 1013 1014 splx(s); 1015 1016 return(0); 1017} 1018 1019/* 1020 * Initialize the transmit descriptors. 1021 */ 1022static int wb_list_tx_init(sc) 1023 struct wb_softc *sc; 1024{ 1025 struct wb_chain_data *cd; 1026 struct wb_list_data *ld; 1027 int i; 1028 1029 cd = &sc->wb_cdata; 1030 ld = sc->wb_ldata; 1031 1032 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1033 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1034 if (i == (WB_TX_LIST_CNT - 1)) { 1035 cd->wb_tx_chain[i].wb_nextdesc = 1036 &cd->wb_tx_chain[0]; 1037 } else { 1038 cd->wb_tx_chain[i].wb_nextdesc = 1039 &cd->wb_tx_chain[i + 1]; 1040 } 1041 } 1042 1043 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1044 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1045 1046 return(0); 1047} 1048 1049 1050/* 1051 * Initialize the RX descriptors and allocate mbufs for them. Note that 1052 * we arrange the descriptors in a closed ring, so that the last descriptor 1053 * points back to the first. 1054 */ 1055static int wb_list_rx_init(sc) 1056 struct wb_softc *sc; 1057{ 1058 struct wb_chain_data *cd; 1059 struct wb_list_data *ld; 1060 int i; 1061 1062 cd = &sc->wb_cdata; 1063 ld = sc->wb_ldata; 1064 1065 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1066 cd->wb_rx_chain[i].wb_ptr = 1067 (struct wb_desc *)&ld->wb_rx_list[i]; 1068 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1069 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1070 return(ENOBUFS); 1071 if (i == (WB_RX_LIST_CNT - 1)) { 1072 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1073 ld->wb_rx_list[i].wb_next = 1074 vtophys(&ld->wb_rx_list[0]); 1075 } else { 1076 cd->wb_rx_chain[i].wb_nextdesc = 1077 &cd->wb_rx_chain[i + 1]; 1078 ld->wb_rx_list[i].wb_next = 1079 vtophys(&ld->wb_rx_list[i + 1]); 1080 } 1081 } 1082 1083 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1084 1085 return(0); 1086} 1087 1088static void wb_bfree(buf, size) 1089 caddr_t buf; 1090 u_int size; 1091{ 1092 return; 1093} 1094 1095/* 1096 * Initialize an RX descriptor and attach an MBUF cluster. 1097 */ 1098static int wb_newbuf(sc, c, m) 1099 struct wb_softc *sc; 1100 struct wb_chain_onefrag *c; 1101 struct mbuf *m; 1102{ 1103 struct mbuf *m_new = NULL; 1104 1105 if (m == NULL) { 1106 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1107 if (m_new == NULL) { 1108 printf("wb%d: no memory for rx " 1109 "list -- packet dropped!\n", sc->wb_unit); 1110 return(ENOBUFS); 1111 } 1112 1113 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 1114 m_new->m_flags |= M_EXT; 1115 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 1116 m_new->m_len = WB_BUFBYTES; 1117 m_new->m_ext.ext_free = wb_bfree; 1118 m_new->m_ext.ext_ref = wb_bfree; 1119 } else { 1120 m_new = m; 1121 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1122 m_new->m_data = m_new->m_ext.ext_buf; 1123 } 1124 1125 m_adj(m_new, sizeof(u_int64_t)); 1126 1127 c->wb_mbuf = m_new; 1128 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1129 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1130 c->wb_ptr->wb_status = WB_RXSTAT; 1131 1132 return(0); 1133} 1134 1135/* 1136 * A frame has been uploaded: pass the resulting mbuf chain up to 1137 * the higher level protocols. 1138 */ 1139static void wb_rxeof(sc) 1140 struct wb_softc *sc; 1141{ 1142 struct ether_header *eh; 1143 struct mbuf *m = NULL; 1144 struct ifnet *ifp; 1145 struct wb_chain_onefrag *cur_rx; 1146 int total_len = 0; 1147 u_int32_t rxstat; 1148 1149 ifp = &sc->arpcom.ac_if; 1150 1151 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1152 WB_RXSTAT_OWN)) { 1153 struct mbuf *m0 = NULL; 1154 1155 cur_rx = sc->wb_cdata.wb_rx_head; 1156 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1157 1158 m = cur_rx->wb_mbuf; 1159 1160 if ((rxstat & WB_RXSTAT_MIIERR) || 1161 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1162 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1163 !(rxstat & WB_RXSTAT_LASTFRAG) || 1164 !(rxstat & WB_RXSTAT_RXCMP)) { 1165 ifp->if_ierrors++; 1166 wb_newbuf(sc, cur_rx, m); 1167 printf("wb%x: receiver babbling: possible chip " 1168 "bug, forcing reset\n", sc->wb_unit); 1169 wb_fixmedia(sc); 1170 wb_reset(sc); 1171 wb_init(sc); 1172 return; 1173 } 1174 1175 if (rxstat & WB_RXSTAT_RXERR) { 1176 ifp->if_ierrors++; 1177 wb_newbuf(sc, cur_rx, m); 1178 break; 1179 } 1180 1181 /* No errors; receive the packet. */ 1182 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1183 1184 /* 1185 * XXX The Winbond chip includes the CRC with every 1186 * received frame, and there's no way to turn this 1187 * behavior off (at least, I can't find anything in 1188 * the manual that explains how to do it) so we have 1189 * to trim off the CRC manually. 1190 */ 1191 total_len -= ETHER_CRC_LEN; 1192 1193 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1194 total_len + ETHER_ALIGN, 0, ifp, NULL); 1195 wb_newbuf(sc, cur_rx, m); 1196 if (m0 == NULL) { 1197 ifp->if_ierrors++; 1198 break; 1199 } 1200 m_adj(m0, ETHER_ALIGN); 1201 m = m0; 1202 1203 ifp->if_ipackets++; 1204 eh = mtod(m, struct ether_header *); 1205 1206#ifdef BRIDGE 1207 if (do_bridge) { 1208 struct ifnet *bdg_ifp; 1209 bdg_ifp = bridge_in(m); 1210 if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP) 1211 bdg_forward(&m, bdg_ifp); 1212 if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) && 1213 (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) { 1214 m_freem(m); 1215 break; 1216 } 1217 } 1218#endif 1219 1220 /* 1221 * Handle BPF listeners. Let the BPF user see the packet, but 1222 * don't pass it up to the ether_input() layer unless it's 1223 * a broadcast packet, multicast packet, matches our ethernet 1224 * address or the interface is in promiscuous mode. 1225 */ 1226 if (ifp->if_bpf) { 1227 bpf_mtap(ifp, m); 1228 if (ifp->if_flags & IFF_PROMISC && 1229 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1230 ETHER_ADDR_LEN) && 1231 (eh->ether_dhost[0] & 1) == 0)) { 1232 m_freem(m); 1233 break; 1234 } 1235 } 1236 1237 /* Remove header from mbuf and pass it on. */ 1238 m_adj(m, sizeof(struct ether_header)); 1239 ether_input(ifp, eh, m); 1240 } 1241 1242 return; 1243} 1244 1245void wb_rxeoc(sc) 1246 struct wb_softc *sc; 1247{ 1248 wb_rxeof(sc); 1249 1250 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1251 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1252 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1253 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1254 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1255 1256 return; 1257} 1258 1259/* 1260 * A frame was downloaded to the chip. It's safe for us to clean up 1261 * the list buffers. 1262 */ 1263static void wb_txeof(sc) 1264 struct wb_softc *sc; 1265{ 1266 struct wb_chain *cur_tx; 1267 struct ifnet *ifp; 1268 1269 ifp = &sc->arpcom.ac_if; 1270 1271 /* Clear the timeout timer. */ 1272 ifp->if_timer = 0; 1273 1274 if (sc->wb_cdata.wb_tx_head == NULL) 1275 return; 1276 1277 /* 1278 * Go through our tx list and free mbufs for those 1279 * frames that have been transmitted. 1280 */ 1281 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1282 u_int32_t txstat; 1283 1284 cur_tx = sc->wb_cdata.wb_tx_head; 1285 txstat = WB_TXSTATUS(cur_tx); 1286 1287 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1288 break; 1289 1290 if (txstat & WB_TXSTAT_TXERR) { 1291 ifp->if_oerrors++; 1292 if (txstat & WB_TXSTAT_ABORT) 1293 ifp->if_collisions++; 1294 if (txstat & WB_TXSTAT_LATECOLL) 1295 ifp->if_collisions++; 1296 } 1297 1298 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1299 1300 ifp->if_opackets++; 1301 m_freem(cur_tx->wb_mbuf); 1302 cur_tx->wb_mbuf = NULL; 1303 1304 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1305 sc->wb_cdata.wb_tx_head = NULL; 1306 sc->wb_cdata.wb_tx_tail = NULL; 1307 break; 1308 } 1309 1310 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1311 } 1312 1313 return; 1314} 1315 1316/* 1317 * TX 'end of channel' interrupt handler. 1318 */ 1319static void wb_txeoc(sc) 1320 struct wb_softc *sc; 1321{ 1322 struct ifnet *ifp; 1323 1324 ifp = &sc->arpcom.ac_if; 1325 1326 ifp->if_timer = 0; 1327 1328 if (sc->wb_cdata.wb_tx_head == NULL) { 1329 ifp->if_flags &= ~IFF_OACTIVE; 1330 sc->wb_cdata.wb_tx_tail = NULL; 1331 } else { 1332 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1333 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1334 ifp->if_timer = 5; 1335 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1336 } 1337 } 1338 1339 return; 1340} 1341 1342static void wb_intr(arg) 1343 void *arg; 1344{ 1345 struct wb_softc *sc; 1346 struct ifnet *ifp; 1347 u_int32_t status; 1348 1349 sc = arg; 1350 ifp = &sc->arpcom.ac_if; 1351 1352 if (!(ifp->if_flags & IFF_UP)) 1353 return; 1354 1355 /* Disable interrupts. */ 1356 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1357 1358 for (;;) { 1359 1360 status = CSR_READ_4(sc, WB_ISR); 1361 if (status) 1362 CSR_WRITE_4(sc, WB_ISR, status); 1363 1364 if ((status & WB_INTRS) == 0) 1365 break; 1366 1367 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1368 ifp->if_ierrors++; 1369 wb_reset(sc); 1370 if (status & WB_ISR_RX_ERR) 1371 wb_fixmedia(sc); 1372 wb_init(sc); 1373 continue; 1374 } 1375 1376 if (status & WB_ISR_RX_OK) 1377 wb_rxeof(sc); 1378 1379 if (status & WB_ISR_RX_IDLE) 1380 wb_rxeoc(sc); 1381 1382 if (status & WB_ISR_TX_OK) 1383 wb_txeof(sc); 1384 1385 if (status & WB_ISR_TX_NOBUF) 1386 wb_txeoc(sc); 1387 1388 if (status & WB_ISR_TX_IDLE) { 1389 wb_txeof(sc); 1390 if (sc->wb_cdata.wb_tx_head != NULL) { 1391 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1392 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1393 } 1394 } 1395 1396 if (status & WB_ISR_TX_UNDERRUN) { 1397 ifp->if_oerrors++; 1398 wb_txeof(sc); 1399 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1400 /* Jack up TX threshold */ 1401 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1402 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1403 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1404 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1405 } 1406 1407 if (status & WB_ISR_BUS_ERR) { 1408 wb_reset(sc); 1409 wb_init(sc); 1410 } 1411 1412 } 1413 1414 /* Re-enable interrupts. */ 1415 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1416 1417 if (ifp->if_snd.ifq_head != NULL) { 1418 wb_start(ifp); 1419 } 1420 1421 return; 1422} 1423 1424static void wb_tick(xsc) 1425 void *xsc; 1426{ 1427 struct wb_softc *sc; 1428 struct mii_data *mii; 1429 int s; 1430 1431 s = splimp(); 1432 1433 sc = xsc; 1434 mii = device_get_softc(sc->wb_miibus); 1435 1436 mii_tick(mii); 1437 1438 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1439 1440 splx(s); 1441 1442 return; 1443} 1444 1445/* 1446 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1447 * pointers to the fragment pointers. 1448 */ 1449static int wb_encap(sc, c, m_head) 1450 struct wb_softc *sc; 1451 struct wb_chain *c; 1452 struct mbuf *m_head; 1453{ 1454 int frag = 0; 1455 struct wb_desc *f = NULL; 1456 int total_len; 1457 struct mbuf *m; 1458 1459 /* 1460 * Start packing the mbufs in this chain into 1461 * the fragment pointers. Stop when we run out 1462 * of fragments or hit the end of the mbuf chain. 1463 */ 1464 m = m_head; 1465 total_len = 0; 1466 1467 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1468 if (m->m_len != 0) { 1469 if (frag == WB_MAXFRAGS) 1470 break; 1471 total_len += m->m_len; 1472 f = &c->wb_ptr->wb_frag[frag]; 1473 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1474 if (frag == 0) { 1475 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1476 f->wb_status = 0; 1477 } else 1478 f->wb_status = WB_TXSTAT_OWN; 1479 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1480 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1481 frag++; 1482 } 1483 } 1484 1485 /* 1486 * Handle special case: we used up all 16 fragments, 1487 * but we have more mbufs left in the chain. Copy the 1488 * data into an mbuf cluster. Note that we don't 1489 * bother clearing the values in the other fragment 1490 * pointers/counters; it wouldn't gain us anything, 1491 * and would waste cycles. 1492 */ 1493 if (m != NULL) { 1494 struct mbuf *m_new = NULL; 1495 1496 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1497 if (m_new == NULL) { 1498 printf("wb%d: no memory for tx list", sc->wb_unit); 1499 return(1); 1500 } 1501 if (m_head->m_pkthdr.len > MHLEN) { 1502 MCLGET(m_new, M_DONTWAIT); 1503 if (!(m_new->m_flags & M_EXT)) { 1504 m_freem(m_new); 1505 printf("wb%d: no memory for tx list", 1506 sc->wb_unit); 1507 return(1); 1508 } 1509 } 1510 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1511 mtod(m_new, caddr_t)); 1512 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1513 m_freem(m_head); 1514 m_head = m_new; 1515 f = &c->wb_ptr->wb_frag[0]; 1516 f->wb_status = 0; 1517 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1518 f->wb_ctl = total_len = m_new->m_len; 1519 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1520 frag = 1; 1521 } 1522 1523 if (total_len < WB_MIN_FRAMELEN) { 1524 f = &c->wb_ptr->wb_frag[frag]; 1525 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1526 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1527 f->wb_ctl |= WB_TXCTL_TLINK; 1528 f->wb_status = WB_TXSTAT_OWN; 1529 frag++; 1530 } 1531 1532 c->wb_mbuf = m_head; 1533 c->wb_lastdesc = frag - 1; 1534 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1535 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1536 1537 return(0); 1538} 1539 1540/* 1541 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1542 * to the mbuf data regions directly in the transmit lists. We also save a 1543 * copy of the pointers since the transmit list fragment pointers are 1544 * physical addresses. 1545 */ 1546 1547static void wb_start(ifp) 1548 struct ifnet *ifp; 1549{ 1550 struct wb_softc *sc; 1551 struct mbuf *m_head = NULL; 1552 struct wb_chain *cur_tx = NULL, *start_tx; 1553 1554 sc = ifp->if_softc; 1555 1556 /* 1557 * Check for an available queue slot. If there are none, 1558 * punt. 1559 */ 1560 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1561 ifp->if_flags |= IFF_OACTIVE; 1562 return; 1563 } 1564 1565 start_tx = sc->wb_cdata.wb_tx_free; 1566 1567 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1568 IF_DEQUEUE(&ifp->if_snd, m_head); 1569 if (m_head == NULL) 1570 break; 1571 1572 /* Pick a descriptor off the free list. */ 1573 cur_tx = sc->wb_cdata.wb_tx_free; 1574 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1575 1576 /* Pack the data into the descriptor. */ 1577 wb_encap(sc, cur_tx, m_head); 1578 1579 if (cur_tx != start_tx) 1580 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1581 1582 /* 1583 * If there's a BPF listener, bounce a copy of this frame 1584 * to him. 1585 */ 1586 if (ifp->if_bpf) 1587 bpf_mtap(ifp, cur_tx->wb_mbuf); 1588 } 1589 1590 /* 1591 * If there are no packets queued, bail. 1592 */ 1593 if (cur_tx == NULL) 1594 return; 1595 1596 /* 1597 * Place the request for the upload interrupt 1598 * in the last descriptor in the chain. This way, if 1599 * we're chaining several packets at once, we'll only 1600 * get an interupt once for the whole chain rather than 1601 * once for each packet. 1602 */ 1603 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1604 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1605 sc->wb_cdata.wb_tx_tail = cur_tx; 1606 1607 if (sc->wb_cdata.wb_tx_head == NULL) { 1608 sc->wb_cdata.wb_tx_head = start_tx; 1609 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1610 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1611 } else { 1612 /* 1613 * We need to distinguish between the case where 1614 * the own bit is clear because the chip cleared it 1615 * and where the own bit is clear because we haven't 1616 * set it yet. The magic value WB_UNSET is just some 1617 * ramdomly chosen number which doesn't have the own 1618 * bit set. When we actually transmit the frame, the 1619 * status word will have _only_ the own bit set, so 1620 * the txeoc handler will be able to tell if it needs 1621 * to initiate another transmission to flush out pending 1622 * frames. 1623 */ 1624 WB_TXOWN(start_tx) = WB_UNSENT; 1625 } 1626 1627 /* 1628 * Set a timeout in case the chip goes out to lunch. 1629 */ 1630 ifp->if_timer = 5; 1631 1632 return; 1633} 1634 1635static void wb_init(xsc) 1636 void *xsc; 1637{ 1638 struct wb_softc *sc = xsc; 1639 struct ifnet *ifp = &sc->arpcom.ac_if; 1640 int s, i; 1641 struct mii_data *mii; 1642 1643 s = splimp(); 1644 1645 mii = device_get_softc(sc->wb_miibus); 1646 1647 /* 1648 * Cancel pending I/O and free all RX/TX buffers. 1649 */ 1650 wb_stop(sc); 1651 wb_reset(sc); 1652 1653 sc->wb_txthresh = WB_TXTHRESH_INIT; 1654 1655 /* 1656 * Set cache alignment and burst length. 1657 */ 1658#ifdef foo 1659 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1660 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1661 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1662#endif 1663 1664 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1665 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1666 switch(sc->wb_cachesize) { 1667 case 32: 1668 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1669 break; 1670 case 16: 1671 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1672 break; 1673 case 8: 1674 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1675 break; 1676 case 0: 1677 default: 1678 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1679 break; 1680 } 1681 1682 /* This doesn't tend to work too well at 100Mbps. */ 1683 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1684 1685 /* Init our MAC address */ 1686 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1687 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1688 } 1689 1690 /* Init circular RX list. */ 1691 if (wb_list_rx_init(sc) == ENOBUFS) { 1692 printf("wb%d: initialization failed: no " 1693 "memory for rx buffers\n", sc->wb_unit); 1694 wb_stop(sc); 1695 (void)splx(s); 1696 return; 1697 } 1698 1699 /* Init TX descriptors. */ 1700 wb_list_tx_init(sc); 1701 1702 /* If we want promiscuous mode, set the allframes bit. */ 1703 if (ifp->if_flags & IFF_PROMISC) { 1704 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1705 } else { 1706 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1707 } 1708 1709 /* 1710 * Set capture broadcast bit to capture broadcast frames. 1711 */ 1712 if (ifp->if_flags & IFF_BROADCAST) { 1713 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1714 } else { 1715 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1716 } 1717 1718 /* 1719 * Program the multicast filter, if necessary. 1720 */ 1721 wb_setmulti(sc); 1722 1723 /* 1724 * Load the address of the RX list. 1725 */ 1726 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1727 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1728 1729 /* 1730 * Enable interrupts. 1731 */ 1732 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1733 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1734 1735 /* Enable receiver and transmitter. */ 1736 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1737 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1738 1739 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1740 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1741 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1742 1743 mii_mediachg(mii); 1744 1745 ifp->if_flags |= IFF_RUNNING; 1746 ifp->if_flags &= ~IFF_OACTIVE; 1747 1748 (void)splx(s); 1749 1750 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1751 1752 return; 1753} 1754 1755/* 1756 * Set media options. 1757 */ 1758static int wb_ifmedia_upd(ifp) 1759 struct ifnet *ifp; 1760{ 1761 struct wb_softc *sc; 1762 1763 sc = ifp->if_softc; 1764 1765 if (ifp->if_flags & IFF_UP) 1766 wb_init(sc); 1767 1768 return(0); 1769} 1770 1771/* 1772 * Report current media status. 1773 */ 1774static void wb_ifmedia_sts(ifp, ifmr) 1775 struct ifnet *ifp; 1776 struct ifmediareq *ifmr; 1777{ 1778 struct wb_softc *sc; 1779 struct mii_data *mii; 1780 1781 sc = ifp->if_softc; 1782 1783 mii = device_get_softc(sc->wb_miibus); 1784 1785 mii_pollstat(mii); 1786 ifmr->ifm_active = mii->mii_media_active; 1787 ifmr->ifm_status = mii->mii_media_status; 1788 1789 return; 1790} 1791 1792static int wb_ioctl(ifp, command, data) 1793 struct ifnet *ifp; 1794 u_long command; 1795 caddr_t data; 1796{ 1797 struct wb_softc *sc = ifp->if_softc; 1798 struct mii_data *mii; 1799 struct ifreq *ifr = (struct ifreq *) data; 1800 int s, error = 0; 1801 1802 s = splimp(); 1803 1804 switch(command) { 1805 case SIOCSIFADDR: 1806 case SIOCGIFADDR: 1807 case SIOCSIFMTU: 1808 error = ether_ioctl(ifp, command, data); 1809 break; 1810 case SIOCSIFFLAGS: 1811 if (ifp->if_flags & IFF_UP) { 1812 wb_init(sc); 1813 } else { 1814 if (ifp->if_flags & IFF_RUNNING) 1815 wb_stop(sc); 1816 } 1817 error = 0; 1818 break; 1819 case SIOCADDMULTI: 1820 case SIOCDELMULTI: 1821 wb_setmulti(sc); 1822 error = 0; 1823 break; 1824 case SIOCGIFMEDIA: 1825 case SIOCSIFMEDIA: 1826 mii = device_get_softc(sc->wb_miibus); 1827 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1828 break; 1829 default: 1830 error = EINVAL; 1831 break; 1832 } 1833 1834 (void)splx(s); 1835 1836 return(error); 1837} 1838 1839static void wb_watchdog(ifp) 1840 struct ifnet *ifp; 1841{ 1842 struct wb_softc *sc; 1843 1844 sc = ifp->if_softc; 1845 1846 ifp->if_oerrors++; 1847 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1848#ifdef foo 1849 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1850 printf("wb%d: no carrier - transceiver cable problem?\n", 1851 sc->wb_unit); 1852#endif 1853 wb_stop(sc); 1854 wb_reset(sc); 1855 wb_init(sc); 1856 1857 if (ifp->if_snd.ifq_head != NULL) 1858 wb_start(ifp); 1859 1860 return; 1861} 1862 1863/* 1864 * Stop the adapter and free any mbufs allocated to the 1865 * RX and TX lists. 1866 */ 1867static void wb_stop(sc) 1868 struct wb_softc *sc; 1869{ 1870 register int i; 1871 struct ifnet *ifp; 1872 1873 ifp = &sc->arpcom.ac_if; 1874 ifp->if_timer = 0; 1875 1876 untimeout(wb_tick, sc, sc->wb_stat_ch); 1877 1878 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1879 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1880 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1881 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1882 1883 /* 1884 * Free data in the RX lists. 1885 */ 1886 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1887 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1888 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1889 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1890 } 1891 } 1892 bzero((char *)&sc->wb_ldata->wb_rx_list, 1893 sizeof(sc->wb_ldata->wb_rx_list)); 1894 1895 /* 1896 * Free the TX list buffers. 1897 */ 1898 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1899 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1900 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1901 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1902 } 1903 } 1904 1905 bzero((char *)&sc->wb_ldata->wb_tx_list, 1906 sizeof(sc->wb_ldata->wb_tx_list)); 1907 1908 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1909 1910 return; 1911} 1912 1913/* 1914 * Stop all chip I/O so that the kernel's probe routines don't 1915 * get confused by errant DMAs when rebooting. 1916 */ 1917static void wb_shutdown(dev) 1918 device_t dev; 1919{ 1920 struct wb_softc *sc; 1921 1922 sc = device_get_softc(dev); 1923 wb_stop(sc); 1924 1925 return; 1926} 1927