if_wb.c revision 50685
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_wb.c 50685 1999-08-31 05:30:13Z wpaul $ 33 */ 34 35/* 36 * Winbond fast ethernet PCI NIC driver 37 * 38 * Supports various cheap network adapters based on the Winbond W89C840F 39 * fast ethernet controller chip. This includes adapters manufactured by 40 * Winbond itself and some made by Linksys. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "bpf.h" 87#include "opt_bdg.h" 88 89#include <sys/param.h> 90#include <sys/systm.h> 91#include <sys/sockio.h> 92#include <sys/mbuf.h> 93#include <sys/malloc.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96#include <sys/queue.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103 104#if NBPF > 0 105#include <net/bpf.h> 106#endif 107 108#ifdef BRIDGE 109#include <net/bridge.h> 110#endif 111 112#include <vm/vm.h> /* for vtophys */ 113#include <vm/pmap.h> /* for vtophys */ 114#include <machine/clock.h> /* for DELAY */ 115#include <machine/bus_memio.h> 116#include <machine/bus_pio.h> 117#include <machine/bus.h> 118#include <machine/resource.h> 119#include <sys/bus.h> 120#include <sys/rman.h> 121 122#include <pci/pcireg.h> 123#include <pci/pcivar.h> 124 125#include <dev/mii/mii.h> 126#include <dev/mii/miivar.h> 127 128#include "miibus_if.h" 129 130#define WB_USEIOSPACE 131 132#include <pci/if_wbreg.h> 133 134#ifndef lint 135static const char rcsid[] = 136 "$FreeBSD: head/sys/pci/if_wb.c 50685 1999-08-31 05:30:13Z wpaul $"; 137#endif 138 139/* 140 * Various supported device vendors/types and their names. 141 */ 142static struct wb_type wb_devs[] = { 143 { WB_VENDORID, WB_DEVICEID_840F, 144 "Winbond W89C840F 10/100BaseTX" }, 145 { CP_VENDORID, CP_DEVICEID_RL100, 146 "Compex RL100-ATX 10/100baseTX" }, 147 { 0, 0, NULL } 148}; 149 150static int wb_probe __P((device_t)); 151static int wb_attach __P((device_t)); 152static int wb_detach __P((device_t)); 153 154static void wb_bfree __P((caddr_t, u_int)); 155static int wb_newbuf __P((struct wb_softc *, 156 struct wb_chain_onefrag *, 157 struct mbuf *)); 158static int wb_encap __P((struct wb_softc *, struct wb_chain *, 159 struct mbuf *)); 160 161static void wb_rxeof __P((struct wb_softc *)); 162static void wb_rxeoc __P((struct wb_softc *)); 163static void wb_txeof __P((struct wb_softc *)); 164static void wb_txeoc __P((struct wb_softc *)); 165static void wb_intr __P((void *)); 166static void wb_tick __P((void *)); 167static void wb_start __P((struct ifnet *)); 168static int wb_ioctl __P((struct ifnet *, u_long, caddr_t)); 169static void wb_init __P((void *)); 170static void wb_stop __P((struct wb_softc *)); 171static void wb_watchdog __P((struct ifnet *)); 172static void wb_shutdown __P((device_t)); 173static int wb_ifmedia_upd __P((struct ifnet *)); 174static void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 175 176static void wb_eeprom_putbyte __P((struct wb_softc *, int)); 177static void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *)); 178static void wb_read_eeprom __P((struct wb_softc *, caddr_t, int, 179 int, int)); 180static void wb_mii_sync __P((struct wb_softc *)); 181static void wb_mii_send __P((struct wb_softc *, u_int32_t, int)); 182static int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *)); 183static int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *)); 184 185static void wb_setcfg __P((struct wb_softc *, u_int32_t)); 186static u_int8_t wb_calchash __P((caddr_t)); 187static void wb_setmulti __P((struct wb_softc *)); 188static void wb_reset __P((struct wb_softc *)); 189static void wb_fixmedia __P((struct wb_softc *)); 190static int wb_list_rx_init __P((struct wb_softc *)); 191static int wb_list_tx_init __P((struct wb_softc *)); 192 193static int wb_miibus_readreg __P((device_t, int, int)); 194static int wb_miibus_writereg __P((device_t, int, int, int)); 195static void wb_miibus_statchg __P((device_t)); 196 197#ifdef WB_USEIOSPACE 198#define WB_RES SYS_RES_IOPORT 199#define WB_RID WB_PCI_LOIO 200#else 201#define WB_RES SYS_RES_MEMORY 202#define WB_RID WB_PCI_LOMEM 203#endif 204 205static device_method_t wb_methods[] = { 206 /* Device interface */ 207 DEVMETHOD(device_probe, wb_probe), 208 DEVMETHOD(device_attach, wb_attach), 209 DEVMETHOD(device_detach, wb_detach), 210 DEVMETHOD(device_shutdown, wb_shutdown), 211 212 /* bus interface, for miibus */ 213 DEVMETHOD(bus_print_child, bus_generic_print_child), 214 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 215 216 /* MII interface */ 217 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 218 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 219 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 220 { 0, 0 } 221}; 222 223static driver_t wb_driver = { 224 "wb", 225 wb_methods, 226 sizeof(struct wb_softc) 227}; 228 229static devclass_t wb_devclass; 230 231DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 232DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 233 234#define WB_SETBIT(sc, reg, x) \ 235 CSR_WRITE_4(sc, reg, \ 236 CSR_READ_4(sc, reg) | x) 237 238#define WB_CLRBIT(sc, reg, x) \ 239 CSR_WRITE_4(sc, reg, \ 240 CSR_READ_4(sc, reg) & ~x) 241 242#define SIO_SET(x) \ 243 CSR_WRITE_4(sc, WB_SIO, \ 244 CSR_READ_4(sc, WB_SIO) | x) 245 246#define SIO_CLR(x) \ 247 CSR_WRITE_4(sc, WB_SIO, \ 248 CSR_READ_4(sc, WB_SIO) & ~x) 249 250/* 251 * Send a read command and address to the EEPROM, check for ACK. 252 */ 253static void wb_eeprom_putbyte(sc, addr) 254 struct wb_softc *sc; 255 int addr; 256{ 257 register int d, i; 258 259 d = addr | WB_EECMD_READ; 260 261 /* 262 * Feed in each bit and stobe the clock. 263 */ 264 for (i = 0x400; i; i >>= 1) { 265 if (d & i) { 266 SIO_SET(WB_SIO_EE_DATAIN); 267 } else { 268 SIO_CLR(WB_SIO_EE_DATAIN); 269 } 270 DELAY(100); 271 SIO_SET(WB_SIO_EE_CLK); 272 DELAY(150); 273 SIO_CLR(WB_SIO_EE_CLK); 274 DELAY(100); 275 } 276 277 return; 278} 279 280/* 281 * Read a word of data stored in the EEPROM at address 'addr.' 282 */ 283static void wb_eeprom_getword(sc, addr, dest) 284 struct wb_softc *sc; 285 int addr; 286 u_int16_t *dest; 287{ 288 register int i; 289 u_int16_t word = 0; 290 291 /* Enter EEPROM access mode. */ 292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 293 294 /* 295 * Send address of word we want to read. 296 */ 297 wb_eeprom_putbyte(sc, addr); 298 299 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 300 301 /* 302 * Start reading bits from EEPROM. 303 */ 304 for (i = 0x8000; i; i >>= 1) { 305 SIO_SET(WB_SIO_EE_CLK); 306 DELAY(100); 307 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 308 word |= i; 309 SIO_CLR(WB_SIO_EE_CLK); 310 DELAY(100); 311 } 312 313 /* Turn off EEPROM access mode. */ 314 CSR_WRITE_4(sc, WB_SIO, 0); 315 316 *dest = word; 317 318 return; 319} 320 321/* 322 * Read a sequence of words from the EEPROM. 323 */ 324static void wb_read_eeprom(sc, dest, off, cnt, swap) 325 struct wb_softc *sc; 326 caddr_t dest; 327 int off; 328 int cnt; 329 int swap; 330{ 331 int i; 332 u_int16_t word = 0, *ptr; 333 334 for (i = 0; i < cnt; i++) { 335 wb_eeprom_getword(sc, off + i, &word); 336 ptr = (u_int16_t *)(dest + (i * 2)); 337 if (swap) 338 *ptr = ntohs(word); 339 else 340 *ptr = word; 341 } 342 343 return; 344} 345 346/* 347 * Sync the PHYs by setting data bit and strobing the clock 32 times. 348 */ 349static void wb_mii_sync(sc) 350 struct wb_softc *sc; 351{ 352 register int i; 353 354 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 355 356 for (i = 0; i < 32; i++) { 357 SIO_SET(WB_SIO_MII_CLK); 358 DELAY(1); 359 SIO_CLR(WB_SIO_MII_CLK); 360 DELAY(1); 361 } 362 363 return; 364} 365 366/* 367 * Clock a series of bits through the MII. 368 */ 369static void wb_mii_send(sc, bits, cnt) 370 struct wb_softc *sc; 371 u_int32_t bits; 372 int cnt; 373{ 374 int i; 375 376 SIO_CLR(WB_SIO_MII_CLK); 377 378 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 379 if (bits & i) { 380 SIO_SET(WB_SIO_MII_DATAIN); 381 } else { 382 SIO_CLR(WB_SIO_MII_DATAIN); 383 } 384 DELAY(1); 385 SIO_CLR(WB_SIO_MII_CLK); 386 DELAY(1); 387 SIO_SET(WB_SIO_MII_CLK); 388 } 389} 390 391/* 392 * Read an PHY register through the MII. 393 */ 394static int wb_mii_readreg(sc, frame) 395 struct wb_softc *sc; 396 struct wb_mii_frame *frame; 397 398{ 399 int i, ack, s; 400 401 s = splimp(); 402 403 /* 404 * Set up frame for RX. 405 */ 406 frame->mii_stdelim = WB_MII_STARTDELIM; 407 frame->mii_opcode = WB_MII_READOP; 408 frame->mii_turnaround = 0; 409 frame->mii_data = 0; 410 411 CSR_WRITE_4(sc, WB_SIO, 0); 412 413 /* 414 * Turn on data xmit. 415 */ 416 SIO_SET(WB_SIO_MII_DIR); 417 418 wb_mii_sync(sc); 419 420 /* 421 * Send command/address info. 422 */ 423 wb_mii_send(sc, frame->mii_stdelim, 2); 424 wb_mii_send(sc, frame->mii_opcode, 2); 425 wb_mii_send(sc, frame->mii_phyaddr, 5); 426 wb_mii_send(sc, frame->mii_regaddr, 5); 427 428 /* Idle bit */ 429 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 430 DELAY(1); 431 SIO_SET(WB_SIO_MII_CLK); 432 DELAY(1); 433 434 /* Turn off xmit. */ 435 SIO_CLR(WB_SIO_MII_DIR); 436 /* Check for ack */ 437 SIO_CLR(WB_SIO_MII_CLK); 438 DELAY(1); 439 SIO_SET(WB_SIO_MII_CLK); 440 DELAY(1); 441 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 442 SIO_CLR(WB_SIO_MII_CLK); 443 DELAY(1); 444 SIO_SET(WB_SIO_MII_CLK); 445 DELAY(1); 446 447 /* 448 * Now try reading data bits. If the ack failed, we still 449 * need to clock through 16 cycles to keep the PHY(s) in sync. 450 */ 451 if (ack) { 452 for(i = 0; i < 16; i++) { 453 SIO_CLR(WB_SIO_MII_CLK); 454 DELAY(1); 455 SIO_SET(WB_SIO_MII_CLK); 456 DELAY(1); 457 } 458 goto fail; 459 } 460 461 for (i = 0x8000; i; i >>= 1) { 462 SIO_CLR(WB_SIO_MII_CLK); 463 DELAY(1); 464 if (!ack) { 465 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 466 frame->mii_data |= i; 467 DELAY(1); 468 } 469 SIO_SET(WB_SIO_MII_CLK); 470 DELAY(1); 471 } 472 473fail: 474 475 SIO_CLR(WB_SIO_MII_CLK); 476 DELAY(1); 477 SIO_SET(WB_SIO_MII_CLK); 478 DELAY(1); 479 480 splx(s); 481 482 if (ack) 483 return(1); 484 return(0); 485} 486 487/* 488 * Write to a PHY register through the MII. 489 */ 490static int wb_mii_writereg(sc, frame) 491 struct wb_softc *sc; 492 struct wb_mii_frame *frame; 493 494{ 495 int s; 496 497 s = splimp(); 498 /* 499 * Set up frame for TX. 500 */ 501 502 frame->mii_stdelim = WB_MII_STARTDELIM; 503 frame->mii_opcode = WB_MII_WRITEOP; 504 frame->mii_turnaround = WB_MII_TURNAROUND; 505 506 /* 507 * Turn on data output. 508 */ 509 SIO_SET(WB_SIO_MII_DIR); 510 511 wb_mii_sync(sc); 512 513 wb_mii_send(sc, frame->mii_stdelim, 2); 514 wb_mii_send(sc, frame->mii_opcode, 2); 515 wb_mii_send(sc, frame->mii_phyaddr, 5); 516 wb_mii_send(sc, frame->mii_regaddr, 5); 517 wb_mii_send(sc, frame->mii_turnaround, 2); 518 wb_mii_send(sc, frame->mii_data, 16); 519 520 /* Idle bit. */ 521 SIO_SET(WB_SIO_MII_CLK); 522 DELAY(1); 523 SIO_CLR(WB_SIO_MII_CLK); 524 DELAY(1); 525 526 /* 527 * Turn off xmit. 528 */ 529 SIO_CLR(WB_SIO_MII_DIR); 530 531 splx(s); 532 533 return(0); 534} 535 536static int wb_miibus_readreg(dev, phy, reg) 537 device_t dev; 538 int phy, reg; 539{ 540 struct wb_softc *sc; 541 struct wb_mii_frame frame; 542 543 sc = device_get_softc(dev); 544 545 bzero((char *)&frame, sizeof(frame)); 546 547 frame.mii_phyaddr = phy; 548 frame.mii_regaddr = reg; 549 wb_mii_readreg(sc, &frame); 550 551 return(frame.mii_data); 552} 553 554static int wb_miibus_writereg(dev, phy, reg, data) 555 device_t dev; 556 int phy, reg, data; 557{ 558 struct wb_softc *sc; 559 struct wb_mii_frame frame; 560 561 sc = device_get_softc(dev); 562 563 bzero((char *)&frame, sizeof(frame)); 564 565 frame.mii_phyaddr = phy; 566 frame.mii_regaddr = reg; 567 frame.mii_data = data; 568 569 wb_mii_writereg(sc, &frame); 570 571 return(0); 572} 573 574static void wb_miibus_statchg(dev) 575 device_t dev; 576{ 577 struct wb_softc *sc; 578 struct mii_data *mii; 579 580 sc = device_get_softc(dev); 581 mii = device_get_softc(sc->wb_miibus); 582 wb_setcfg(sc, mii->mii_media_active); 583 584 return; 585} 586 587static u_int8_t wb_calchash(addr) 588 caddr_t addr; 589{ 590 u_int32_t crc, carry; 591 int i, j; 592 u_int8_t c; 593 594 /* Compute CRC for the address value. */ 595 crc = 0xFFFFFFFF; /* initial value */ 596 597 for (i = 0; i < 6; i++) { 598 c = *(addr + i); 599 for (j = 0; j < 8; j++) { 600 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 601 crc <<= 1; 602 c >>= 1; 603 if (carry) 604 crc = (crc ^ 0x04c11db6) | carry; 605 } 606 } 607 608 /* 609 * return the filter bit position 610 * Note: I arrived at the following nonsense 611 * through experimentation. It's not the usual way to 612 * generate the bit position but it's the only thing 613 * I could come up with that works. 614 */ 615 return(~(crc >> 26) & 0x0000003F); 616} 617 618/* 619 * Program the 64-bit multicast hash filter. 620 */ 621static void wb_setmulti(sc) 622 struct wb_softc *sc; 623{ 624 struct ifnet *ifp; 625 int h = 0; 626 u_int32_t hashes[2] = { 0, 0 }; 627 struct ifmultiaddr *ifma; 628 u_int32_t rxfilt; 629 int mcnt = 0; 630 631 ifp = &sc->arpcom.ac_if; 632 633 rxfilt = CSR_READ_4(sc, WB_NETCFG); 634 635 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 636 rxfilt |= WB_NETCFG_RX_MULTI; 637 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 638 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 639 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 640 return; 641 } 642 643 /* first, zot all the existing hash bits */ 644 CSR_WRITE_4(sc, WB_MAR0, 0); 645 CSR_WRITE_4(sc, WB_MAR1, 0); 646 647 /* now program new ones */ 648 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 649 ifma = ifma->ifma_link.le_next) { 650 if (ifma->ifma_addr->sa_family != AF_LINK) 651 continue; 652 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 653 if (h < 32) 654 hashes[0] |= (1 << h); 655 else 656 hashes[1] |= (1 << (h - 32)); 657 mcnt++; 658 } 659 660 if (mcnt) 661 rxfilt |= WB_NETCFG_RX_MULTI; 662 else 663 rxfilt &= ~WB_NETCFG_RX_MULTI; 664 665 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 666 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 667 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 668 669 return; 670} 671 672/* 673 * The Winbond manual states that in order to fiddle with the 674 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 675 * first have to put the transmit and/or receive logic in the idle state. 676 */ 677static void wb_setcfg(sc, media) 678 struct wb_softc *sc; 679 u_int32_t media; 680{ 681 int i, restart = 0; 682 683 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 684 restart = 1; 685 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 686 687 for (i = 0; i < WB_TIMEOUT; i++) { 688 DELAY(10); 689 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 690 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 691 break; 692 } 693 694 if (i == WB_TIMEOUT) 695 printf("wb%d: failed to force tx and " 696 "rx to idle state\n", sc->wb_unit); 697 } 698 699 if (IFM_SUBTYPE(media) == IFM_10_T) 700 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 701 else 702 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 703 704 if ((media & IFM_GMASK) == IFM_FDX) 705 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 706 else 707 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 708 709 if (restart) 710 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 711 712 return; 713} 714 715static void wb_reset(sc) 716 struct wb_softc *sc; 717{ 718 register int i; 719 struct mii_data *mii; 720 721 CSR_WRITE_4(sc, WB_NETCFG, 0); 722 CSR_WRITE_4(sc, WB_BUSCTL, 0); 723 CSR_WRITE_4(sc, WB_TXADDR, 0); 724 CSR_WRITE_4(sc, WB_RXADDR, 0); 725 726 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 727 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 728 729 for (i = 0; i < WB_TIMEOUT; i++) { 730 DELAY(10); 731 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 732 break; 733 } 734 if (i == WB_TIMEOUT) 735 printf("wb%d: reset never completed!\n", sc->wb_unit); 736 737 /* Wait a little while for the chip to get its brains in order. */ 738 DELAY(1000); 739 740 if (sc->wb_miibus == NULL) 741 return; 742 743 mii = device_get_softc(sc->wb_miibus); 744 if (mii == NULL) 745 return; 746 747 if (mii->mii_instance) { 748 struct mii_softc *miisc; 749 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 750 miisc = LIST_NEXT(miisc, mii_list)) 751 mii_phy_reset(miisc); 752 } 753 754 return; 755} 756 757static void wb_fixmedia(sc) 758 struct wb_softc *sc; 759{ 760 struct mii_data *mii = NULL; 761 struct ifnet *ifp; 762 u_int32_t media; 763 764 if (sc->wb_miibus == NULL) 765 return; 766 767 mii = device_get_softc(sc->wb_miibus); 768 ifp = &sc->arpcom.ac_if; 769 770 mii_pollstat(mii); 771 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 772 media = mii->mii_media_active & ~IFM_10_T; 773 media |= IFM_100_TX; 774 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 775 media = mii->mii_media_active & ~IFM_100_TX; 776 media |= IFM_10_T; 777 } else 778 return; 779 780 ifmedia_set(&mii->mii_media, media); 781 782 return; 783} 784 785/* 786 * Probe for a Winbond chip. Check the PCI vendor and device 787 * IDs against our list and return a device name if we find a match. 788 */ 789static int wb_probe(dev) 790 device_t dev; 791{ 792 struct wb_type *t; 793 794 t = wb_devs; 795 796 while(t->wb_name != NULL) { 797 if ((pci_get_vendor(dev) == t->wb_vid) && 798 (pci_get_device(dev) == t->wb_did)) { 799 device_set_desc(dev, t->wb_name); 800 return(0); 801 } 802 t++; 803 } 804 805 return(ENXIO); 806} 807 808/* 809 * Attach the interface. Allocate softc structures, do ifmedia 810 * setup and ethernet/BPF attach. 811 */ 812static int wb_attach(dev) 813 device_t dev; 814{ 815 int s; 816 u_char eaddr[ETHER_ADDR_LEN]; 817 u_int32_t command; 818 struct wb_softc *sc; 819 struct ifnet *ifp; 820 int unit, error = 0, rid; 821 822 s = splimp(); 823 824 sc = device_get_softc(dev); 825 unit = device_get_unit(dev); 826 827 /* 828 * Handle power management nonsense. 829 */ 830 831 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF; 832 if (command == 0x01) { 833 834 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4); 835 if (command & WB_PSTATE_MASK) { 836 u_int32_t iobase, membase, irq; 837 838 /* Save important PCI config data. */ 839 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 840 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 841 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 842 843 /* Reset the power state. */ 844 printf("wb%d: chip is in D%d power mode " 845 "-- setting to D0\n", unit, command & WB_PSTATE_MASK); 846 command &= 0xFFFFFFFC; 847 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4); 848 849 /* Restore PCI config data. */ 850 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 851 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 852 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 853 } 854 } 855 856 /* 857 * Map control/status registers. 858 */ 859 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 860 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 861 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 862 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 863 864#ifdef WB_USEIOSPACE 865 if (!(command & PCIM_CMD_PORTEN)) { 866 printf("wb%d: failed to enable I/O ports!\n", unit); 867 error = ENXIO; 868 goto fail; 869 } 870#else 871 if (!(command & PCIM_CMD_MEMEN)) { 872 printf("wb%d: failed to enable memory mapping!\n", unit); 873 error = ENXIO; 874 goto fail; 875 } 876#endif 877 878 rid = WB_RID; 879 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 880 0, ~0, 1, RF_ACTIVE); 881 882 if (sc->wb_res == NULL) { 883 printf("wb%d: couldn't map ports/memory\n", unit); 884 error = ENXIO; 885 goto fail; 886 } 887 888 sc->wb_btag = rman_get_bustag(sc->wb_res); 889 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 890 891 /* Allocate interrupt */ 892 rid = 0; 893 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 894 RF_SHAREABLE | RF_ACTIVE); 895 896 if (sc->wb_irq == NULL) { 897 printf("wb%d: couldn't map interrupt\n", unit); 898 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 899 error = ENXIO; 900 goto fail; 901 } 902 903 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 904 wb_intr, sc, &sc->wb_intrhand); 905 906 if (error) { 907 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 908 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 909 printf("wb%d: couldn't set up irq\n", unit); 910 goto fail; 911 } 912 913 /* Save the cache line size. */ 914 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 915 916 /* Reset the adapter. */ 917 wb_reset(sc); 918 919 /* 920 * Get station address from the EEPROM. 921 */ 922 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 923 924 /* 925 * A Winbond chip was detected. Inform the world. 926 */ 927 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 928 929 sc->wb_unit = unit; 930 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 931 932 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 933 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 934 935 if (sc->wb_ldata == NULL) { 936 printf("wb%d: no memory for list buffers!\n", unit); 937 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 938 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 939 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 940 error = ENXIO; 941 goto fail; 942 } 943 944 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 945 946 ifp = &sc->arpcom.ac_if; 947 ifp->if_softc = sc; 948 ifp->if_unit = unit; 949 ifp->if_name = "wb"; 950 ifp->if_mtu = ETHERMTU; 951 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 952 ifp->if_ioctl = wb_ioctl; 953 ifp->if_output = ether_output; 954 ifp->if_start = wb_start; 955 ifp->if_watchdog = wb_watchdog; 956 ifp->if_init = wb_init; 957 ifp->if_baudrate = 10000000; 958 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 959 960 /* 961 * Do MII setup. 962 */ 963 if (mii_phy_probe(dev, &sc->wb_miibus, 964 wb_ifmedia_upd, wb_ifmedia_sts)) { 965 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 966 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 967 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 968 free(sc->wb_ldata_ptr, M_DEVBUF); 969 error = ENXIO; 970 goto fail; 971 } 972 973 /* 974 * Call MI attach routines. 975 */ 976 if_attach(ifp); 977 ether_ifattach(ifp); 978 979#if NBPF > 0 980 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 981#endif 982 983fail: 984 if (error) 985 device_delete_child(dev, sc->wb_miibus); 986 splx(s); 987 988 return(error); 989} 990 991static int wb_detach(dev) 992 device_t dev; 993{ 994 struct wb_softc *sc; 995 struct ifnet *ifp; 996 int s; 997 998 s = splimp(); 999 1000 sc = device_get_softc(dev); 1001 ifp = &sc->arpcom.ac_if; 1002 1003 wb_stop(sc); 1004 if_detach(ifp); 1005 1006 /* Delete any miibus and phy devices attached to this interface */ 1007 bus_generic_detach(dev); 1008 device_delete_child(dev, sc->wb_miibus); 1009 1010 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 1011 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 1012 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 1013 1014 free(sc->wb_ldata_ptr, M_DEVBUF); 1015 1016 splx(s); 1017 1018 return(0); 1019} 1020 1021/* 1022 * Initialize the transmit descriptors. 1023 */ 1024static int wb_list_tx_init(sc) 1025 struct wb_softc *sc; 1026{ 1027 struct wb_chain_data *cd; 1028 struct wb_list_data *ld; 1029 int i; 1030 1031 cd = &sc->wb_cdata; 1032 ld = sc->wb_ldata; 1033 1034 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1035 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1036 if (i == (WB_TX_LIST_CNT - 1)) { 1037 cd->wb_tx_chain[i].wb_nextdesc = 1038 &cd->wb_tx_chain[0]; 1039 } else { 1040 cd->wb_tx_chain[i].wb_nextdesc = 1041 &cd->wb_tx_chain[i + 1]; 1042 } 1043 } 1044 1045 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1046 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1047 1048 return(0); 1049} 1050 1051 1052/* 1053 * Initialize the RX descriptors and allocate mbufs for them. Note that 1054 * we arrange the descriptors in a closed ring, so that the last descriptor 1055 * points back to the first. 1056 */ 1057static int wb_list_rx_init(sc) 1058 struct wb_softc *sc; 1059{ 1060 struct wb_chain_data *cd; 1061 struct wb_list_data *ld; 1062 int i; 1063 1064 cd = &sc->wb_cdata; 1065 ld = sc->wb_ldata; 1066 1067 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1068 cd->wb_rx_chain[i].wb_ptr = 1069 (struct wb_desc *)&ld->wb_rx_list[i]; 1070 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1071 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1072 return(ENOBUFS); 1073 if (i == (WB_RX_LIST_CNT - 1)) { 1074 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1075 ld->wb_rx_list[i].wb_next = 1076 vtophys(&ld->wb_rx_list[0]); 1077 } else { 1078 cd->wb_rx_chain[i].wb_nextdesc = 1079 &cd->wb_rx_chain[i + 1]; 1080 ld->wb_rx_list[i].wb_next = 1081 vtophys(&ld->wb_rx_list[i + 1]); 1082 } 1083 } 1084 1085 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1086 1087 return(0); 1088} 1089 1090static void wb_bfree(buf, size) 1091 caddr_t buf; 1092 u_int size; 1093{ 1094 return; 1095} 1096 1097/* 1098 * Initialize an RX descriptor and attach an MBUF cluster. 1099 */ 1100static int wb_newbuf(sc, c, m) 1101 struct wb_softc *sc; 1102 struct wb_chain_onefrag *c; 1103 struct mbuf *m; 1104{ 1105 struct mbuf *m_new = NULL; 1106 1107 if (m == NULL) { 1108 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1109 if (m_new == NULL) { 1110 printf("wb%d: no memory for rx " 1111 "list -- packet dropped!\n", sc->wb_unit); 1112 return(ENOBUFS); 1113 } 1114 1115 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 1116 m_new->m_flags |= M_EXT; 1117 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 1118 m_new->m_len = WB_BUFBYTES; 1119 m_new->m_ext.ext_free = wb_bfree; 1120 m_new->m_ext.ext_ref = wb_bfree; 1121 } else { 1122 m_new = m; 1123 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1124 m_new->m_data = m_new->m_ext.ext_buf; 1125 } 1126 1127 m_adj(m_new, sizeof(u_int64_t)); 1128 1129 c->wb_mbuf = m_new; 1130 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1131 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1132 c->wb_ptr->wb_status = WB_RXSTAT; 1133 1134 return(0); 1135} 1136 1137/* 1138 * A frame has been uploaded: pass the resulting mbuf chain up to 1139 * the higher level protocols. 1140 */ 1141static void wb_rxeof(sc) 1142 struct wb_softc *sc; 1143{ 1144 struct ether_header *eh; 1145 struct mbuf *m = NULL; 1146 struct ifnet *ifp; 1147 struct wb_chain_onefrag *cur_rx; 1148 int total_len = 0; 1149 u_int32_t rxstat; 1150 1151 ifp = &sc->arpcom.ac_if; 1152 1153 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1154 WB_RXSTAT_OWN)) { 1155 struct mbuf *m0 = NULL; 1156 1157 cur_rx = sc->wb_cdata.wb_rx_head; 1158 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1159 1160 m = cur_rx->wb_mbuf; 1161 1162 if ((rxstat & WB_RXSTAT_MIIERR) || 1163 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1164 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1165 !(rxstat & WB_RXSTAT_LASTFRAG) || 1166 !(rxstat & WB_RXSTAT_RXCMP)) { 1167 ifp->if_ierrors++; 1168 wb_newbuf(sc, cur_rx, m); 1169 printf("wb%x: receiver babbling: possible chip " 1170 "bug, forcing reset\n", sc->wb_unit); 1171 wb_fixmedia(sc); 1172 wb_reset(sc); 1173 wb_init(sc); 1174 return; 1175 } 1176 1177 if (rxstat & WB_RXSTAT_RXERR) { 1178 ifp->if_ierrors++; 1179 wb_newbuf(sc, cur_rx, m); 1180 break; 1181 } 1182 1183 /* No errors; receive the packet. */ 1184 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1185 1186 /* 1187 * XXX The Winbond chip includes the CRC with every 1188 * received frame, and there's no way to turn this 1189 * behavior off (at least, I can't find anything in 1190 * the manual that explains how to do it) so we have 1191 * to trim off the CRC manually. 1192 */ 1193 total_len -= ETHER_CRC_LEN; 1194 1195 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1196 total_len + ETHER_ALIGN, 0, ifp, NULL); 1197 wb_newbuf(sc, cur_rx, m); 1198 if (m0 == NULL) { 1199 ifp->if_ierrors++; 1200 break; 1201 } 1202 m_adj(m0, ETHER_ALIGN); 1203 m = m0; 1204 1205 ifp->if_ipackets++; 1206 eh = mtod(m, struct ether_header *); 1207 1208#ifdef BRIDGE 1209 if (do_bridge) { 1210 struct ifnet *bdg_ifp; 1211 bdg_ifp = bridge_in(m); 1212 if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP) 1213 bdg_forward(&m, bdg_ifp); 1214 if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) && 1215 (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) { 1216 m_freem(m); 1217 break; 1218 } 1219 } 1220#endif 1221 1222#if NBPF > 0 1223 /* 1224 * Handle BPF listeners. Let the BPF user see the packet, but 1225 * don't pass it up to the ether_input() layer unless it's 1226 * a broadcast packet, multicast packet, matches our ethernet 1227 * address or the interface is in promiscuous mode. 1228 */ 1229 if (ifp->if_bpf) { 1230 bpf_mtap(ifp, m); 1231 if (ifp->if_flags & IFF_PROMISC && 1232 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1233 ETHER_ADDR_LEN) && 1234 (eh->ether_dhost[0] & 1) == 0)) { 1235 m_freem(m); 1236 break; 1237 } 1238 } 1239#endif 1240 /* Remove header from mbuf and pass it on. */ 1241 m_adj(m, sizeof(struct ether_header)); 1242 ether_input(ifp, eh, m); 1243 } 1244 1245 return; 1246} 1247 1248void wb_rxeoc(sc) 1249 struct wb_softc *sc; 1250{ 1251 wb_rxeof(sc); 1252 1253 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1254 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1255 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1256 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1257 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1258 1259 return; 1260} 1261 1262/* 1263 * A frame was downloaded to the chip. It's safe for us to clean up 1264 * the list buffers. 1265 */ 1266static void wb_txeof(sc) 1267 struct wb_softc *sc; 1268{ 1269 struct wb_chain *cur_tx; 1270 struct ifnet *ifp; 1271 1272 ifp = &sc->arpcom.ac_if; 1273 1274 /* Clear the timeout timer. */ 1275 ifp->if_timer = 0; 1276 1277 if (sc->wb_cdata.wb_tx_head == NULL) 1278 return; 1279 1280 /* 1281 * Go through our tx list and free mbufs for those 1282 * frames that have been transmitted. 1283 */ 1284 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1285 u_int32_t txstat; 1286 1287 cur_tx = sc->wb_cdata.wb_tx_head; 1288 txstat = WB_TXSTATUS(cur_tx); 1289 1290 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1291 break; 1292 1293 if (txstat & WB_TXSTAT_TXERR) { 1294 ifp->if_oerrors++; 1295 if (txstat & WB_TXSTAT_ABORT) 1296 ifp->if_collisions++; 1297 if (txstat & WB_TXSTAT_LATECOLL) 1298 ifp->if_collisions++; 1299 } 1300 1301 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1302 1303 ifp->if_opackets++; 1304 m_freem(cur_tx->wb_mbuf); 1305 cur_tx->wb_mbuf = NULL; 1306 1307 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1308 sc->wb_cdata.wb_tx_head = NULL; 1309 sc->wb_cdata.wb_tx_tail = NULL; 1310 break; 1311 } 1312 1313 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1314 } 1315 1316 return; 1317} 1318 1319/* 1320 * TX 'end of channel' interrupt handler. 1321 */ 1322static void wb_txeoc(sc) 1323 struct wb_softc *sc; 1324{ 1325 struct ifnet *ifp; 1326 1327 ifp = &sc->arpcom.ac_if; 1328 1329 ifp->if_timer = 0; 1330 1331 if (sc->wb_cdata.wb_tx_head == NULL) { 1332 ifp->if_flags &= ~IFF_OACTIVE; 1333 sc->wb_cdata.wb_tx_tail = NULL; 1334 } else { 1335 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1336 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1337 ifp->if_timer = 5; 1338 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1339 } 1340 } 1341 1342 return; 1343} 1344 1345static void wb_intr(arg) 1346 void *arg; 1347{ 1348 struct wb_softc *sc; 1349 struct ifnet *ifp; 1350 u_int32_t status; 1351 1352 sc = arg; 1353 ifp = &sc->arpcom.ac_if; 1354 1355 if (!(ifp->if_flags & IFF_UP)) 1356 return; 1357 1358 /* Disable interrupts. */ 1359 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1360 1361 for (;;) { 1362 1363 status = CSR_READ_4(sc, WB_ISR); 1364 if (status) 1365 CSR_WRITE_4(sc, WB_ISR, status); 1366 1367 if ((status & WB_INTRS) == 0) 1368 break; 1369 1370 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1371 ifp->if_ierrors++; 1372 wb_reset(sc); 1373 if (status & WB_ISR_RX_ERR) 1374 wb_fixmedia(sc); 1375 wb_init(sc); 1376 continue; 1377 } 1378 1379 if (status & WB_ISR_RX_OK) 1380 wb_rxeof(sc); 1381 1382 if (status & WB_ISR_RX_IDLE) 1383 wb_rxeoc(sc); 1384 1385 if (status & WB_ISR_TX_OK) 1386 wb_txeof(sc); 1387 1388 if (status & WB_ISR_TX_NOBUF) 1389 wb_txeoc(sc); 1390 1391 if (status & WB_ISR_TX_IDLE) { 1392 wb_txeof(sc); 1393 if (sc->wb_cdata.wb_tx_head != NULL) { 1394 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1395 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1396 } 1397 } 1398 1399 if (status & WB_ISR_TX_UNDERRUN) { 1400 ifp->if_oerrors++; 1401 wb_txeof(sc); 1402 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1403 /* Jack up TX threshold */ 1404 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1405 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1406 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1407 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1408 } 1409 1410 if (status & WB_ISR_BUS_ERR) { 1411 wb_reset(sc); 1412 wb_init(sc); 1413 } 1414 1415 } 1416 1417 /* Re-enable interrupts. */ 1418 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1419 1420 if (ifp->if_snd.ifq_head != NULL) { 1421 wb_start(ifp); 1422 } 1423 1424 return; 1425} 1426 1427static void wb_tick(xsc) 1428 void *xsc; 1429{ 1430 struct wb_softc *sc; 1431 struct mii_data *mii; 1432 int s; 1433 1434 s = splimp(); 1435 1436 sc = xsc; 1437 mii = device_get_softc(sc->wb_miibus); 1438 1439 mii_tick(mii); 1440 1441 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1442 1443 splx(s); 1444 1445 return; 1446} 1447 1448/* 1449 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1450 * pointers to the fragment pointers. 1451 */ 1452static int wb_encap(sc, c, m_head) 1453 struct wb_softc *sc; 1454 struct wb_chain *c; 1455 struct mbuf *m_head; 1456{ 1457 int frag = 0; 1458 struct wb_desc *f = NULL; 1459 int total_len; 1460 struct mbuf *m; 1461 1462 /* 1463 * Start packing the mbufs in this chain into 1464 * the fragment pointers. Stop when we run out 1465 * of fragments or hit the end of the mbuf chain. 1466 */ 1467 m = m_head; 1468 total_len = 0; 1469 1470 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1471 if (m->m_len != 0) { 1472 if (frag == WB_MAXFRAGS) 1473 break; 1474 total_len += m->m_len; 1475 f = &c->wb_ptr->wb_frag[frag]; 1476 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1477 if (frag == 0) { 1478 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1479 f->wb_status = 0; 1480 } else 1481 f->wb_status = WB_TXSTAT_OWN; 1482 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1483 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1484 frag++; 1485 } 1486 } 1487 1488 /* 1489 * Handle special case: we used up all 16 fragments, 1490 * but we have more mbufs left in the chain. Copy the 1491 * data into an mbuf cluster. Note that we don't 1492 * bother clearing the values in the other fragment 1493 * pointers/counters; it wouldn't gain us anything, 1494 * and would waste cycles. 1495 */ 1496 if (m != NULL) { 1497 struct mbuf *m_new = NULL; 1498 1499 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1500 if (m_new == NULL) { 1501 printf("wb%d: no memory for tx list", sc->wb_unit); 1502 return(1); 1503 } 1504 if (m_head->m_pkthdr.len > MHLEN) { 1505 MCLGET(m_new, M_DONTWAIT); 1506 if (!(m_new->m_flags & M_EXT)) { 1507 m_freem(m_new); 1508 printf("wb%d: no memory for tx list", 1509 sc->wb_unit); 1510 return(1); 1511 } 1512 } 1513 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1514 mtod(m_new, caddr_t)); 1515 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1516 m_freem(m_head); 1517 m_head = m_new; 1518 f = &c->wb_ptr->wb_frag[0]; 1519 f->wb_status = 0; 1520 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1521 f->wb_ctl = total_len = m_new->m_len; 1522 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1523 frag = 1; 1524 } 1525 1526 if (total_len < WB_MIN_FRAMELEN) { 1527 f = &c->wb_ptr->wb_frag[frag]; 1528 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1529 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1530 f->wb_ctl |= WB_TXCTL_TLINK; 1531 f->wb_status = WB_TXSTAT_OWN; 1532 frag++; 1533 } 1534 1535 c->wb_mbuf = m_head; 1536 c->wb_lastdesc = frag - 1; 1537 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1538 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1539 1540 return(0); 1541} 1542 1543/* 1544 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1545 * to the mbuf data regions directly in the transmit lists. We also save a 1546 * copy of the pointers since the transmit list fragment pointers are 1547 * physical addresses. 1548 */ 1549 1550static void wb_start(ifp) 1551 struct ifnet *ifp; 1552{ 1553 struct wb_softc *sc; 1554 struct mbuf *m_head = NULL; 1555 struct wb_chain *cur_tx = NULL, *start_tx; 1556 1557 sc = ifp->if_softc; 1558 1559 /* 1560 * Check for an available queue slot. If there are none, 1561 * punt. 1562 */ 1563 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1564 ifp->if_flags |= IFF_OACTIVE; 1565 return; 1566 } 1567 1568 start_tx = sc->wb_cdata.wb_tx_free; 1569 1570 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1571 IF_DEQUEUE(&ifp->if_snd, m_head); 1572 if (m_head == NULL) 1573 break; 1574 1575 /* Pick a descriptor off the free list. */ 1576 cur_tx = sc->wb_cdata.wb_tx_free; 1577 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1578 1579 /* Pack the data into the descriptor. */ 1580 wb_encap(sc, cur_tx, m_head); 1581 1582 if (cur_tx != start_tx) 1583 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1584 1585#if NBPF > 0 1586 /* 1587 * If there's a BPF listener, bounce a copy of this frame 1588 * to him. 1589 */ 1590 if (ifp->if_bpf) 1591 bpf_mtap(ifp, cur_tx->wb_mbuf); 1592#endif 1593 } 1594 1595 /* 1596 * If there are no packets queued, bail. 1597 */ 1598 if (cur_tx == NULL) 1599 return; 1600 1601 /* 1602 * Place the request for the upload interrupt 1603 * in the last descriptor in the chain. This way, if 1604 * we're chaining several packets at once, we'll only 1605 * get an interupt once for the whole chain rather than 1606 * once for each packet. 1607 */ 1608 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1609 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1610 sc->wb_cdata.wb_tx_tail = cur_tx; 1611 1612 if (sc->wb_cdata.wb_tx_head == NULL) { 1613 sc->wb_cdata.wb_tx_head = start_tx; 1614 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1615 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1616 } else { 1617 /* 1618 * We need to distinguish between the case where 1619 * the own bit is clear because the chip cleared it 1620 * and where the own bit is clear because we haven't 1621 * set it yet. The magic value WB_UNSET is just some 1622 * ramdomly chosen number which doesn't have the own 1623 * bit set. When we actually transmit the frame, the 1624 * status word will have _only_ the own bit set, so 1625 * the txeoc handler will be able to tell if it needs 1626 * to initiate another transmission to flush out pending 1627 * frames. 1628 */ 1629 WB_TXOWN(start_tx) = WB_UNSENT; 1630 } 1631 1632 /* 1633 * Set a timeout in case the chip goes out to lunch. 1634 */ 1635 ifp->if_timer = 5; 1636 1637 return; 1638} 1639 1640static void wb_init(xsc) 1641 void *xsc; 1642{ 1643 struct wb_softc *sc = xsc; 1644 struct ifnet *ifp = &sc->arpcom.ac_if; 1645 int s, i; 1646 struct mii_data *mii; 1647 1648 s = splimp(); 1649 1650 mii = device_get_softc(sc->wb_miibus); 1651 1652 /* 1653 * Cancel pending I/O and free all RX/TX buffers. 1654 */ 1655 wb_stop(sc); 1656 wb_reset(sc); 1657 1658 sc->wb_txthresh = WB_TXTHRESH_INIT; 1659 1660 /* 1661 * Set cache alignment and burst length. 1662 */ 1663#ifdef foo 1664 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1665 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1666 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1667#endif 1668 1669 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1670 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1671 switch(sc->wb_cachesize) { 1672 case 32: 1673 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1674 break; 1675 case 16: 1676 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1677 break; 1678 case 8: 1679 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1680 break; 1681 case 0: 1682 default: 1683 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1684 break; 1685 } 1686 1687 /* This doesn't tend to work too well at 100Mbps. */ 1688 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1689 1690 /* Init our MAC address */ 1691 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1692 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1693 } 1694 1695 /* Init circular RX list. */ 1696 if (wb_list_rx_init(sc) == ENOBUFS) { 1697 printf("wb%d: initialization failed: no " 1698 "memory for rx buffers\n", sc->wb_unit); 1699 wb_stop(sc); 1700 (void)splx(s); 1701 return; 1702 } 1703 1704 /* Init TX descriptors. */ 1705 wb_list_tx_init(sc); 1706 1707 /* If we want promiscuous mode, set the allframes bit. */ 1708 if (ifp->if_flags & IFF_PROMISC) { 1709 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1710 } else { 1711 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1712 } 1713 1714 /* 1715 * Set capture broadcast bit to capture broadcast frames. 1716 */ 1717 if (ifp->if_flags & IFF_BROADCAST) { 1718 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1719 } else { 1720 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1721 } 1722 1723 /* 1724 * Program the multicast filter, if necessary. 1725 */ 1726 wb_setmulti(sc); 1727 1728 /* 1729 * Load the address of the RX list. 1730 */ 1731 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1732 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1733 1734 /* 1735 * Enable interrupts. 1736 */ 1737 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1738 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1739 1740 /* Enable receiver and transmitter. */ 1741 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1742 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1743 1744 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1745 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1746 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1747 1748 mii_mediachg(mii); 1749 1750 ifp->if_flags |= IFF_RUNNING; 1751 ifp->if_flags &= ~IFF_OACTIVE; 1752 1753 (void)splx(s); 1754 1755 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1756 1757 return; 1758} 1759 1760/* 1761 * Set media options. 1762 */ 1763static int wb_ifmedia_upd(ifp) 1764 struct ifnet *ifp; 1765{ 1766 struct wb_softc *sc; 1767 1768 sc = ifp->if_softc; 1769 1770 if (ifp->if_flags & IFF_UP) 1771 wb_init(sc); 1772 1773 return(0); 1774} 1775 1776/* 1777 * Report current media status. 1778 */ 1779static void wb_ifmedia_sts(ifp, ifmr) 1780 struct ifnet *ifp; 1781 struct ifmediareq *ifmr; 1782{ 1783 struct wb_softc *sc; 1784 struct mii_data *mii; 1785 1786 sc = ifp->if_softc; 1787 1788 mii = device_get_softc(sc->wb_miibus); 1789 1790 mii_pollstat(mii); 1791 ifmr->ifm_active = mii->mii_media_active; 1792 ifmr->ifm_status = mii->mii_media_status; 1793 1794 return; 1795} 1796 1797static int wb_ioctl(ifp, command, data) 1798 struct ifnet *ifp; 1799 u_long command; 1800 caddr_t data; 1801{ 1802 struct wb_softc *sc = ifp->if_softc; 1803 struct mii_data *mii; 1804 struct ifreq *ifr = (struct ifreq *) data; 1805 int s, error = 0; 1806 1807 s = splimp(); 1808 1809 switch(command) { 1810 case SIOCSIFADDR: 1811 case SIOCGIFADDR: 1812 case SIOCSIFMTU: 1813 error = ether_ioctl(ifp, command, data); 1814 break; 1815 case SIOCSIFFLAGS: 1816 if (ifp->if_flags & IFF_UP) { 1817 wb_init(sc); 1818 } else { 1819 if (ifp->if_flags & IFF_RUNNING) 1820 wb_stop(sc); 1821 } 1822 error = 0; 1823 break; 1824 case SIOCADDMULTI: 1825 case SIOCDELMULTI: 1826 wb_setmulti(sc); 1827 error = 0; 1828 break; 1829 case SIOCGIFMEDIA: 1830 case SIOCSIFMEDIA: 1831 mii = device_get_softc(sc->wb_miibus); 1832 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1833 break; 1834 default: 1835 error = EINVAL; 1836 break; 1837 } 1838 1839 (void)splx(s); 1840 1841 return(error); 1842} 1843 1844static void wb_watchdog(ifp) 1845 struct ifnet *ifp; 1846{ 1847 struct wb_softc *sc; 1848 1849 sc = ifp->if_softc; 1850 1851 ifp->if_oerrors++; 1852 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1853#ifdef foo 1854 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1855 printf("wb%d: no carrier - transceiver cable problem?\n", 1856 sc->wb_unit); 1857#endif 1858 wb_stop(sc); 1859 wb_reset(sc); 1860 wb_init(sc); 1861 1862 if (ifp->if_snd.ifq_head != NULL) 1863 wb_start(ifp); 1864 1865 return; 1866} 1867 1868/* 1869 * Stop the adapter and free any mbufs allocated to the 1870 * RX and TX lists. 1871 */ 1872static void wb_stop(sc) 1873 struct wb_softc *sc; 1874{ 1875 register int i; 1876 struct ifnet *ifp; 1877 1878 ifp = &sc->arpcom.ac_if; 1879 ifp->if_timer = 0; 1880 1881 untimeout(wb_tick, sc, sc->wb_stat_ch); 1882 1883 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1884 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1885 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1886 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1887 1888 /* 1889 * Free data in the RX lists. 1890 */ 1891 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1892 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1893 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1894 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1895 } 1896 } 1897 bzero((char *)&sc->wb_ldata->wb_rx_list, 1898 sizeof(sc->wb_ldata->wb_rx_list)); 1899 1900 /* 1901 * Free the TX list buffers. 1902 */ 1903 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1904 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1905 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1906 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1907 } 1908 } 1909 1910 bzero((char *)&sc->wb_ldata->wb_tx_list, 1911 sizeof(sc->wb_ldata->wb_tx_list)); 1912 1913 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1914 1915 return; 1916} 1917 1918/* 1919 * Stop all chip I/O so that the kernel's probe routines don't 1920 * get confused by errant DMAs when rebooting. 1921 */ 1922static void wb_shutdown(dev) 1923 device_t dev; 1924{ 1925 struct wb_softc *sc; 1926 1927 sc = device_get_softc(dev); 1928 wb_stop(sc); 1929 1930 return; 1931} 1932