if_wb.c revision 41934
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $Id: if_wb.c,v 1.4 1998/12/14 06:32:56 dillon Exp $ 33 */ 34 35/* 36 * Winbond fast ethernet PCI NIC driver 37 * 38 * Supports various cheap network adapters based on the Winbond W89C840F 39 * fast ethernet controller chip. This includes adapters manufactured by 40 * Winbond itself and some made by Linksys. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "bpfilter.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101 102#if NBPFILTER > 0 103#include <net/bpf.h> 104#endif 105 106#include <vm/vm.h> /* for vtophys */ 107#include <vm/pmap.h> /* for vtophys */ 108#include <machine/clock.h> /* for DELAY */ 109#include <machine/bus_memio.h> 110#include <machine/bus_pio.h> 111#include <machine/bus.h> 112 113#include <pci/pcireg.h> 114#include <pci/pcivar.h> 115 116#define WB_USEIOSPACE 117 118/* #define WB_BACKGROUND_AUTONEG */ 119 120#include <pci/if_wbreg.h> 121 122#ifndef lint 123static const char rcsid[] = 124 "$Id: if_wb.c,v 1.4 1998/12/14 06:32:56 dillon Exp $"; 125#endif 126 127/* 128 * Various supported device vendors/types and their names. 129 */ 130static struct wb_type wb_devs[] = { 131 { WB_VENDORID, WB_DEVICEID_840F, 132 "Winbond W89C840F 10/100BaseTX" }, 133 { CP_VENDORID, CP_DEVICEID_RL100, 134 "Compex RL100-ATX 10/100baseTX" }, 135 { 0, 0, NULL } 136}; 137 138/* 139 * Various supported PHY vendors/types and their names. Note that 140 * this driver will work with pretty much any MII-compliant PHY, 141 * so failure to positively identify the chip is not a fatal error. 142 */ 143 144static struct wb_type wb_phys[] = { 145 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" }, 146 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" }, 147 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"}, 148 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 149 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" }, 150 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" }, 151 { 0, 0, "<MII-compliant physical interface>" } 152}; 153 154static unsigned long wb_count = 0; 155static const char *wb_probe __P((pcici_t, pcidi_t)); 156static void wb_attach __P((pcici_t, int)); 157 158static int wb_newbuf __P((struct wb_softc *, 159 struct wb_chain_onefrag *)); 160static int wb_encap __P((struct wb_softc *, struct wb_chain *, 161 struct mbuf *)); 162 163static void wb_rxeof __P((struct wb_softc *)); 164static void wb_rxeoc __P((struct wb_softc *)); 165static void wb_txeof __P((struct wb_softc *)); 166static void wb_txeoc __P((struct wb_softc *)); 167static void wb_intr __P((void *)); 168static void wb_start __P((struct ifnet *)); 169static int wb_ioctl __P((struct ifnet *, u_long, caddr_t)); 170static void wb_init __P((void *)); 171static void wb_stop __P((struct wb_softc *)); 172static void wb_watchdog __P((struct ifnet *)); 173static void wb_shutdown __P((int, void *)); 174static int wb_ifmedia_upd __P((struct ifnet *)); 175static void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 176 177static void wb_eeprom_putbyte __P((struct wb_softc *, u_int8_t)); 178static void wb_eeprom_getword __P((struct wb_softc *, u_int8_t, u_int16_t *)); 179static void wb_read_eeprom __P((struct wb_softc *, caddr_t, int, 180 int, int)); 181static void wb_mii_sync __P((struct wb_softc *)); 182static void wb_mii_send __P((struct wb_softc *, u_int32_t, int)); 183static int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *)); 184static int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *)); 185static u_int16_t wb_phy_readreg __P((struct wb_softc *, int)); 186static void wb_phy_writereg __P((struct wb_softc *, u_int16_t, u_int16_t)); 187 188static void wb_autoneg_xmit __P((struct wb_softc *)); 189static void wb_autoneg_mii __P((struct wb_softc *, int, int)); 190static void wb_setmode_mii __P((struct wb_softc *, int)); 191static void wb_getmode_mii __P((struct wb_softc *)); 192static void wb_setcfg __P((struct wb_softc *, u_int16_t)); 193static u_int8_t wb_calchash __P((u_int8_t *)); 194static void wb_setmulti __P((struct wb_softc *)); 195static void wb_reset __P((struct wb_softc *)); 196static int wb_list_rx_init __P((struct wb_softc *)); 197static int wb_list_tx_init __P((struct wb_softc *)); 198 199#define WB_SETBIT(sc, reg, x) \ 200 CSR_WRITE_4(sc, reg, \ 201 CSR_READ_4(sc, reg) | x) 202 203#define WB_CLRBIT(sc, reg, x) \ 204 CSR_WRITE_4(sc, reg, \ 205 CSR_READ_4(sc, reg) & ~x) 206 207#define SIO_SET(x) \ 208 CSR_WRITE_4(sc, WB_SIO, \ 209 CSR_READ_4(sc, WB_SIO) | x) 210 211#define SIO_CLR(x) \ 212 CSR_WRITE_4(sc, WB_SIO, \ 213 CSR_READ_4(sc, WB_SIO) & ~x) 214 215/* 216 * Send a read command and address to the EEPROM, check for ACK. 217 */ 218static void wb_eeprom_putbyte(sc, addr) 219 struct wb_softc *sc; 220 u_int8_t addr; 221{ 222 register int d, i; 223 224 d = addr | WB_EECMD_READ; 225 226 /* 227 * Feed in each bit and stobe the clock. 228 */ 229 for (i = 0x400; i; i >>= 1) { 230 if (d & i) { 231 SIO_SET(WB_SIO_EE_DATAIN); 232 } else { 233 SIO_CLR(WB_SIO_EE_DATAIN); 234 } 235 DELAY(100); 236 SIO_SET(WB_SIO_EE_CLK); 237 DELAY(150); 238 SIO_CLR(WB_SIO_EE_CLK); 239 DELAY(100); 240 } 241 242 return; 243} 244 245/* 246 * Read a word of data stored in the EEPROM at address 'addr.' 247 */ 248static void wb_eeprom_getword(sc, addr, dest) 249 struct wb_softc *sc; 250 u_int8_t addr; 251 u_int16_t *dest; 252{ 253 register int i; 254 u_int16_t word = 0; 255 256 /* Enter EEPROM access mode. */ 257 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 258 259 /* 260 * Send address of word we want to read. 261 */ 262 wb_eeprom_putbyte(sc, addr); 263 264 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 265 266 /* 267 * Start reading bits from EEPROM. 268 */ 269 for (i = 0x8000; i; i >>= 1) { 270 SIO_SET(WB_SIO_EE_CLK); 271 DELAY(100); 272 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 273 word |= i; 274 SIO_CLR(WB_SIO_EE_CLK); 275 DELAY(100); 276 } 277 278 /* Turn off EEPROM access mode. */ 279 CSR_WRITE_4(sc, WB_SIO, 0); 280 281 *dest = word; 282 283 return; 284} 285 286/* 287 * Read a sequence of words from the EEPROM. 288 */ 289static void wb_read_eeprom(sc, dest, off, cnt, swap) 290 struct wb_softc *sc; 291 caddr_t dest; 292 int off; 293 int cnt; 294 int swap; 295{ 296 int i; 297 u_int16_t word = 0, *ptr; 298 299 for (i = 0; i < cnt; i++) { 300 wb_eeprom_getword(sc, off + i, &word); 301 ptr = (u_int16_t *)(dest + (i * 2)); 302 if (swap) 303 *ptr = ntohs(word); 304 else 305 *ptr = word; 306 } 307 308 return; 309} 310 311/* 312 * Sync the PHYs by setting data bit and strobing the clock 32 times. 313 */ 314static void wb_mii_sync(sc) 315 struct wb_softc *sc; 316{ 317 register int i; 318 319 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 320 321 for (i = 0; i < 32; i++) { 322 SIO_SET(WB_SIO_MII_CLK); 323 DELAY(1); 324 SIO_CLR(WB_SIO_MII_CLK); 325 DELAY(1); 326 } 327 328 return; 329} 330 331/* 332 * Clock a series of bits through the MII. 333 */ 334static void wb_mii_send(sc, bits, cnt) 335 struct wb_softc *sc; 336 u_int32_t bits; 337 int cnt; 338{ 339 int i; 340 341 SIO_CLR(WB_SIO_MII_CLK); 342 343 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 344 if (bits & i) { 345 SIO_SET(WB_SIO_MII_DATAIN); 346 } else { 347 SIO_CLR(WB_SIO_MII_DATAIN); 348 } 349 DELAY(1); 350 SIO_CLR(WB_SIO_MII_CLK); 351 DELAY(1); 352 SIO_SET(WB_SIO_MII_CLK); 353 } 354} 355 356/* 357 * Read an PHY register through the MII. 358 */ 359static int wb_mii_readreg(sc, frame) 360 struct wb_softc *sc; 361 struct wb_mii_frame *frame; 362 363{ 364 int i, ack, s; 365 366 s = splimp(); 367 368 /* 369 * Set up frame for RX. 370 */ 371 frame->mii_stdelim = WB_MII_STARTDELIM; 372 frame->mii_opcode = WB_MII_READOP; 373 frame->mii_turnaround = 0; 374 frame->mii_data = 0; 375 376 CSR_WRITE_4(sc, WB_SIO, 0); 377 378 /* 379 * Turn on data xmit. 380 */ 381 SIO_SET(WB_SIO_MII_DIR); 382 383 wb_mii_sync(sc); 384 385 /* 386 * Send command/address info. 387 */ 388 wb_mii_send(sc, frame->mii_stdelim, 2); 389 wb_mii_send(sc, frame->mii_opcode, 2); 390 wb_mii_send(sc, frame->mii_phyaddr, 5); 391 wb_mii_send(sc, frame->mii_regaddr, 5); 392 393 /* Idle bit */ 394 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 395 DELAY(1); 396 SIO_SET(WB_SIO_MII_CLK); 397 DELAY(1); 398 399 /* Turn off xmit. */ 400 SIO_CLR(WB_SIO_MII_DIR); 401 /* Check for ack */ 402 SIO_CLR(WB_SIO_MII_CLK); 403 DELAY(1); 404 SIO_SET(WB_SIO_MII_CLK); 405 DELAY(1); 406 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 407 SIO_CLR(WB_SIO_MII_CLK); 408 DELAY(1); 409 SIO_SET(WB_SIO_MII_CLK); 410 DELAY(1); 411 412 /* 413 * Now try reading data bits. If the ack failed, we still 414 * need to clock through 16 cycles to keep the PHY(s) in sync. 415 */ 416 if (ack) { 417 for(i = 0; i < 16; i++) { 418 SIO_CLR(WB_SIO_MII_CLK); 419 DELAY(1); 420 SIO_SET(WB_SIO_MII_CLK); 421 DELAY(1); 422 } 423 goto fail; 424 } 425 426 for (i = 0x8000; i; i >>= 1) { 427 SIO_CLR(WB_SIO_MII_CLK); 428 DELAY(1); 429 if (!ack) { 430 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 431 frame->mii_data |= i; 432 DELAY(1); 433 } 434 SIO_SET(WB_SIO_MII_CLK); 435 DELAY(1); 436 } 437 438fail: 439 440 SIO_CLR(WB_SIO_MII_CLK); 441 DELAY(1); 442 SIO_SET(WB_SIO_MII_CLK); 443 DELAY(1); 444 445 splx(s); 446 447 if (ack) 448 return(1); 449 return(0); 450} 451 452/* 453 * Write to a PHY register through the MII. 454 */ 455static int wb_mii_writereg(sc, frame) 456 struct wb_softc *sc; 457 struct wb_mii_frame *frame; 458 459{ 460 int s; 461 462 s = splimp(); 463 /* 464 * Set up frame for TX. 465 */ 466 467 frame->mii_stdelim = WB_MII_STARTDELIM; 468 frame->mii_opcode = WB_MII_WRITEOP; 469 frame->mii_turnaround = WB_MII_TURNAROUND; 470 471 /* 472 * Turn on data output. 473 */ 474 SIO_SET(WB_SIO_MII_DIR); 475 476 wb_mii_sync(sc); 477 478 wb_mii_send(sc, frame->mii_stdelim, 2); 479 wb_mii_send(sc, frame->mii_opcode, 2); 480 wb_mii_send(sc, frame->mii_phyaddr, 5); 481 wb_mii_send(sc, frame->mii_regaddr, 5); 482 wb_mii_send(sc, frame->mii_turnaround, 2); 483 wb_mii_send(sc, frame->mii_data, 16); 484 485 /* Idle bit. */ 486 SIO_SET(WB_SIO_MII_CLK); 487 DELAY(1); 488 SIO_CLR(WB_SIO_MII_CLK); 489 DELAY(1); 490 491 /* 492 * Turn off xmit. 493 */ 494 SIO_CLR(WB_SIO_MII_DIR); 495 496 splx(s); 497 498 return(0); 499} 500 501static u_int16_t wb_phy_readreg(sc, reg) 502 struct wb_softc *sc; 503 int reg; 504{ 505 struct wb_mii_frame frame; 506 507 bzero((char *)&frame, sizeof(frame)); 508 509 frame.mii_phyaddr = sc->wb_phy_addr; 510 frame.mii_regaddr = reg; 511 wb_mii_readreg(sc, &frame); 512 513 return(frame.mii_data); 514} 515 516static void wb_phy_writereg(sc, reg, data) 517 struct wb_softc *sc; 518 u_int16_t reg; 519 u_int16_t data; 520{ 521 struct wb_mii_frame frame; 522 523 bzero((char *)&frame, sizeof(frame)); 524 525 frame.mii_phyaddr = sc->wb_phy_addr; 526 frame.mii_regaddr = reg; 527 frame.mii_data = data; 528 529 wb_mii_writereg(sc, &frame); 530 531 return; 532} 533 534static u_int8_t wb_calchash(addr) 535 u_int8_t *addr; 536{ 537 u_int32_t crc, carry; 538 int i, j; 539 u_int8_t c; 540 541 /* Compute CRC for the address value. */ 542 crc = 0xFFFFFFFF; /* initial value */ 543 544 for (i = 0; i < 6; i++) { 545 c = *(addr + i); 546 for (j = 0; j < 8; j++) { 547 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 548 crc <<= 1; 549 c >>= 1; 550 if (carry) 551 crc = (crc ^ 0x04c11db6) | carry; 552 } 553 } 554 555 /* 556 * return the filter bit position 557 * Note: I arrived at the following nonsense 558 * through experimentation. It's not the usual way to 559 * generate the bit position but it's the only thing 560 * I could come up with that works. 561 */ 562 return(~(crc >> 26) & 0x0000003F); 563} 564 565/* 566 * Program the 64-bit multicast hash filter. 567 */ 568static void wb_setmulti(sc) 569 struct wb_softc *sc; 570{ 571 struct ifnet *ifp; 572 int h = 0; 573 u_int32_t hashes[2] = { 0, 0 }; 574 struct ifmultiaddr *ifma; 575 u_int32_t rxfilt; 576 int mcnt = 0; 577 578 ifp = &sc->arpcom.ac_if; 579 580 rxfilt = CSR_READ_4(sc, WB_NETCFG); 581 582 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 583 rxfilt |= WB_NETCFG_RX_MULTI; 584 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 585 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 586 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 587 return; 588 } 589 590 /* first, zot all the existing hash bits */ 591 CSR_WRITE_4(sc, WB_MAR0, 0); 592 CSR_WRITE_4(sc, WB_MAR1, 0); 593 594 /* now program new ones */ 595 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 596 ifma = ifma->ifma_link.le_next) { 597 if (ifma->ifma_addr->sa_family != AF_LINK) 598 continue; 599 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 600 if (h < 32) 601 hashes[0] |= (1 << h); 602 else 603 hashes[1] |= (1 << (h - 32)); 604 mcnt++; 605 } 606 607 if (mcnt) 608 rxfilt |= WB_NETCFG_RX_MULTI; 609 else 610 rxfilt &= ~WB_NETCFG_RX_MULTI; 611 612 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 613 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 614 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 615 616 return; 617} 618 619/* 620 * Initiate an autonegotiation session. 621 */ 622static void wb_autoneg_xmit(sc) 623 struct wb_softc *sc; 624{ 625 u_int16_t phy_sts; 626 627 wb_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 628 DELAY(500); 629 while(wb_phy_readreg(sc, PHY_BMCR) 630 & PHY_BMCR_RESET); 631 632 phy_sts = wb_phy_readreg(sc, PHY_BMCR); 633 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 634 wb_phy_writereg(sc, PHY_BMCR, phy_sts); 635 636 return; 637} 638 639/* 640 * Invoke autonegotiation on a PHY. 641 */ 642static void wb_autoneg_mii(sc, flag, verbose) 643 struct wb_softc *sc; 644 int flag; 645 int verbose; 646{ 647 u_int16_t phy_sts = 0, media, advert, ability; 648 struct ifnet *ifp; 649 struct ifmedia *ifm; 650 651 ifm = &sc->ifmedia; 652 ifp = &sc->arpcom.ac_if; 653 654 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 655 656 /* 657 * The 100baseT4 PHY on the 3c905-T4 has the 'autoneg supported' 658 * bit cleared in the status register, but has the 'autoneg enabled' 659 * bit set in the control register. This is a contradiction, and 660 * I'm not sure how to handle it. If you want to force an attempt 661 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR 662 * and see what happens. 663 */ 664#ifndef FORCE_AUTONEG_TFOUR 665 /* 666 * First, see if autoneg is supported. If not, there's 667 * no point in continuing. 668 */ 669 phy_sts = wb_phy_readreg(sc, PHY_BMSR); 670 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 671 if (verbose) 672 printf("wb%d: autonegotiation not supported\n", 673 sc->wb_unit); 674 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 675 return; 676 } 677#endif 678 679 switch (flag) { 680 case WB_FLAG_FORCEDELAY: 681 /* 682 * XXX Never use this option anywhere but in the probe 683 * routine: making the kernel stop dead in its tracks 684 * for three whole seconds after we've gone multi-user 685 * is really bad manners. 686 */ 687 wb_autoneg_xmit(sc); 688 DELAY(5000000); 689 break; 690 case WB_FLAG_SCHEDDELAY: 691 /* 692 * Wait for the transmitter to go idle before starting 693 * an autoneg session, otherwise wb_start() may clobber 694 * our timeout, and we don't want to allow transmission 695 * during an autoneg session since that can screw it up. 696 */ 697 if (sc->wb_cdata.wb_tx_head != NULL) { 698 sc->wb_want_auto = 1; 699 return; 700 } 701 wb_autoneg_xmit(sc); 702 ifp->if_timer = 5; 703 sc->wb_autoneg = 1; 704 sc->wb_want_auto = 0; 705 return; 706 break; 707 case WB_FLAG_DELAYTIMEO: 708 ifp->if_timer = 0; 709 sc->wb_autoneg = 0; 710 break; 711 default: 712 printf("wb%d: invalid autoneg flag: %d\n", sc->wb_unit, flag); 713 return; 714 } 715 716 if (wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 717 if (verbose) 718 printf("wb%d: autoneg complete, ", sc->wb_unit); 719 phy_sts = wb_phy_readreg(sc, PHY_BMSR); 720 } else { 721 if (verbose) 722 printf("wb%d: autoneg not complete, ", sc->wb_unit); 723 } 724 725 media = wb_phy_readreg(sc, PHY_BMCR); 726 727 /* Link is good. Report modes and set duplex mode. */ 728 if (wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 729 if (verbose) 730 printf("link status good "); 731 advert = wb_phy_readreg(sc, PHY_ANAR); 732 ability = wb_phy_readreg(sc, PHY_LPAR); 733 734 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 735 ifm->ifm_media = IFM_ETHER|IFM_100_T4; 736 media |= PHY_BMCR_SPEEDSEL; 737 media &= ~PHY_BMCR_DUPLEX; 738 printf("(100baseT4)\n"); 739 } else if (advert & PHY_ANAR_100BTXFULL && 740 ability & PHY_ANAR_100BTXFULL) { 741 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 742 media |= PHY_BMCR_SPEEDSEL; 743 media |= PHY_BMCR_DUPLEX; 744 printf("(full-duplex, 100Mbps)\n"); 745 } else if (advert & PHY_ANAR_100BTXHALF && 746 ability & PHY_ANAR_100BTXHALF) { 747 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 748 media |= PHY_BMCR_SPEEDSEL; 749 media &= ~PHY_BMCR_DUPLEX; 750 printf("(half-duplex, 100Mbps)\n"); 751 } else if (advert & PHY_ANAR_10BTFULL && 752 ability & PHY_ANAR_10BTFULL) { 753 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 754 media &= ~PHY_BMCR_SPEEDSEL; 755 media |= PHY_BMCR_DUPLEX; 756 printf("(full-duplex, 10Mbps)\n"); 757 } else /* if (advert & PHY_ANAR_10BTHALF && 758 ability & PHY_ANAR_10BTHALF) */ { 759 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 760 media &= ~PHY_BMCR_SPEEDSEL; 761 media &= ~PHY_BMCR_DUPLEX; 762 printf("(half-duplex, 10Mbps)\n"); 763 } 764 765 media &= ~PHY_BMCR_AUTONEGENBL; 766 767 /* Set ASIC's duplex mode to match the PHY. */ 768 wb_setcfg(sc, media); 769 wb_phy_writereg(sc, PHY_BMCR, media); 770 } else { 771 if (verbose) 772 printf("no carrier\n"); 773 } 774 775 wb_init(sc); 776 777 if (sc->wb_tx_pend) { 778 sc->wb_autoneg = 0; 779 sc->wb_tx_pend = 0; 780 wb_start(ifp); 781 } 782 783 return; 784} 785 786static void wb_getmode_mii(sc) 787 struct wb_softc *sc; 788{ 789 u_int16_t bmsr; 790 struct ifnet *ifp; 791 792 ifp = &sc->arpcom.ac_if; 793 794 bmsr = wb_phy_readreg(sc, PHY_BMSR); 795 if (bootverbose) 796 printf("wb%d: PHY status word: %x\n", sc->wb_unit, bmsr); 797 798 /* fallback */ 799 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 800 801 if (bmsr & PHY_BMSR_10BTHALF) { 802 if (bootverbose) 803 printf("wb%d: 10Mbps half-duplex mode supported\n", 804 sc->wb_unit); 805 ifmedia_add(&sc->ifmedia, 806 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 807 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 808 } 809 810 if (bmsr & PHY_BMSR_10BTFULL) { 811 if (bootverbose) 812 printf("wb%d: 10Mbps full-duplex mode supported\n", 813 sc->wb_unit); 814 ifmedia_add(&sc->ifmedia, 815 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 816 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 817 } 818 819 if (bmsr & PHY_BMSR_100BTXHALF) { 820 if (bootverbose) 821 printf("wb%d: 100Mbps half-duplex mode supported\n", 822 sc->wb_unit); 823 ifp->if_baudrate = 100000000; 824 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 825 ifmedia_add(&sc->ifmedia, 826 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 827 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 828 } 829 830 if (bmsr & PHY_BMSR_100BTXFULL) { 831 if (bootverbose) 832 printf("wb%d: 100Mbps full-duplex mode supported\n", 833 sc->wb_unit); 834 ifp->if_baudrate = 100000000; 835 ifmedia_add(&sc->ifmedia, 836 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 837 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 838 } 839 840 /* Some also support 100BaseT4. */ 841 if (bmsr & PHY_BMSR_100BT4) { 842 if (bootverbose) 843 printf("wb%d: 100baseT4 mode supported\n", sc->wb_unit); 844 ifp->if_baudrate = 100000000; 845 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); 846 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4; 847#ifdef FORCE_AUTONEG_TFOUR 848 if (bootverbose) 849 printf("wb%d: forcing on autoneg support for BT4\n", 850 sc->wb_unit); 851 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL): 852 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 853#endif 854 } 855 856 if (bmsr & PHY_BMSR_CANAUTONEG) { 857 if (bootverbose) 858 printf("wb%d: autoneg supported\n", sc->wb_unit); 859 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 860 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 861 } 862 863 return; 864} 865 866/* 867 * Set speed and duplex mode. 868 */ 869static void wb_setmode_mii(sc, media) 870 struct wb_softc *sc; 871 int media; 872{ 873 u_int16_t bmcr; 874 struct ifnet *ifp; 875 876 ifp = &sc->arpcom.ac_if; 877 878 /* 879 * If an autoneg session is in progress, stop it. 880 */ 881 if (sc->wb_autoneg) { 882 printf("wb%d: canceling autoneg session\n", sc->wb_unit); 883 ifp->if_timer = sc->wb_autoneg = sc->wb_want_auto = 0; 884 bmcr = wb_phy_readreg(sc, PHY_BMCR); 885 bmcr &= ~PHY_BMCR_AUTONEGENBL; 886 wb_phy_writereg(sc, PHY_BMCR, bmcr); 887 } 888 889 printf("wb%d: selecting MII, ", sc->wb_unit); 890 891 bmcr = wb_phy_readreg(sc, PHY_BMCR); 892 893 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL| 894 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK); 895 896 if (IFM_SUBTYPE(media) == IFM_100_T4) { 897 printf("100Mbps/T4, half-duplex\n"); 898 bmcr |= PHY_BMCR_SPEEDSEL; 899 bmcr &= ~PHY_BMCR_DUPLEX; 900 } 901 902 if (IFM_SUBTYPE(media) == IFM_100_TX) { 903 printf("100Mbps, "); 904 bmcr |= PHY_BMCR_SPEEDSEL; 905 } 906 907 if (IFM_SUBTYPE(media) == IFM_10_T) { 908 printf("10Mbps, "); 909 bmcr &= ~PHY_BMCR_SPEEDSEL; 910 } 911 912 if ((media & IFM_GMASK) == IFM_FDX) { 913 printf("full duplex\n"); 914 bmcr |= PHY_BMCR_DUPLEX; 915 } else { 916 printf("half duplex\n"); 917 bmcr &= ~PHY_BMCR_DUPLEX; 918 } 919 920 wb_setcfg(sc, bmcr); 921 wb_phy_writereg(sc, PHY_BMCR, bmcr); 922 923 return; 924} 925 926/* 927 * The Winbond manual states that in order to fiddle with the 928 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 929 * first have to put the transmit and/or receive logic in the idle state. 930 */ 931static void wb_setcfg(sc, bmcr) 932 struct wb_softc *sc; 933 u_int16_t bmcr; 934{ 935 int i, restart = 0; 936 937 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 938 restart = 1; 939 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 940 941 for (i = 0; i < WB_TIMEOUT; i++) { 942 DELAY(10); 943 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 944 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 945 break; 946 } 947 948 if (i == WB_TIMEOUT) 949 printf("wb%d: failed to force tx and " 950 "rx to idle state\n", sc->wb_unit); 951 } 952 953 if (bmcr & PHY_BMCR_SPEEDSEL) 954 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 955 else 956 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 957 958 if (bmcr & PHY_BMCR_DUPLEX) 959 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 960 else 961 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 962 963 if (restart) 964 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 965 966 return; 967} 968 969static void wb_reset(sc) 970 struct wb_softc *sc; 971{ 972 register int i; 973 974 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 975 976 for (i = 0; i < WB_TIMEOUT; i++) { 977 DELAY(10); 978 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 979 break; 980 } 981 if (i == WB_TIMEOUT) 982 printf("wb%d: reset never completed!\n", sc->wb_unit); 983 984 /* Wait a little while for the chip to get its brains in order. */ 985 DELAY(1000); 986 987 /* Reset the damn PHY too. */ 988 if (sc->wb_pinfo != NULL) 989 wb_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 990 991 return; 992} 993 994/* 995 * Probe for a Winbond chip. Check the PCI vendor and device 996 * IDs against our list and return a device name if we find a match. 997 */ 998static const char * 999wb_probe(config_id, device_id) 1000 pcici_t config_id; 1001 pcidi_t device_id; 1002{ 1003 struct wb_type *t; 1004 1005 t = wb_devs; 1006 1007 while(t->wb_name != NULL) { 1008 if ((device_id & 0xFFFF) == t->wb_vid && 1009 ((device_id >> 16) & 0xFFFF) == t->wb_did) { 1010 return(t->wb_name); 1011 } 1012 t++; 1013 } 1014 1015 return(NULL); 1016} 1017 1018/* 1019 * Attach the interface. Allocate softc structures, do ifmedia 1020 * setup and ethernet/BPF attach. 1021 */ 1022static void 1023wb_attach(config_id, unit) 1024 pcici_t config_id; 1025 int unit; 1026{ 1027 int s, i; 1028#ifndef WB_USEIOSPACE 1029 vm_offset_t pbase, vbase; 1030#endif 1031 u_char eaddr[ETHER_ADDR_LEN]; 1032 u_int32_t command; 1033 struct wb_softc *sc; 1034 struct ifnet *ifp; 1035 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1036 unsigned int round; 1037 caddr_t roundptr; 1038 struct wb_type *p; 1039 u_int16_t phy_vid, phy_did, phy_sts; 1040 1041 s = splimp(); 1042 1043 sc = malloc(sizeof(struct wb_softc), M_DEVBUF, M_NOWAIT); 1044 if (sc == NULL) { 1045 printf("wb%d: no memory for softc struct!\n", unit); 1046 return; 1047 } 1048 bzero(sc, sizeof(struct wb_softc)); 1049 1050 /* 1051 * Handle power management nonsense. 1052 */ 1053 1054 command = pci_conf_read(config_id, WB_PCI_CAPID) & 0x000000FF; 1055 if (command == 0x01) { 1056 1057 command = pci_conf_read(config_id, WB_PCI_PWRMGMTCTRL); 1058 if (command & WB_PSTATE_MASK) { 1059 u_int32_t iobase, membase, irq; 1060 1061 /* Save important PCI config data. */ 1062 iobase = pci_conf_read(config_id, WB_PCI_LOIO); 1063 membase = pci_conf_read(config_id, WB_PCI_LOMEM); 1064 irq = pci_conf_read(config_id, WB_PCI_INTLINE); 1065 1066 /* Reset the power state. */ 1067 printf("wb%d: chip is in D%d power mode " 1068 "-- setting to D0\n", unit, command & WB_PSTATE_MASK); 1069 command &= 0xFFFFFFFC; 1070 pci_conf_write(config_id, WB_PCI_PWRMGMTCTRL, command); 1071 1072 /* Restore PCI config data. */ 1073 pci_conf_write(config_id, WB_PCI_LOIO, iobase); 1074 pci_conf_write(config_id, WB_PCI_LOMEM, membase); 1075 pci_conf_write(config_id, WB_PCI_INTLINE, irq); 1076 } 1077 } 1078 1079 /* 1080 * Map control/status registers. 1081 */ 1082 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1083 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1084 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); 1085 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1086 1087#ifdef WB_USEIOSPACE 1088 if (!(command & PCIM_CMD_PORTEN)) { 1089 printf("wb%d: failed to enable I/O ports!\n", unit); 1090 free(sc, M_DEVBUF); 1091 goto fail; 1092 } 1093 1094 if (!pci_map_port(config_id, WB_PCI_LOIO, 1095 (u_int16_t *)&(sc->wb_bhandle))) { 1096 printf ("wb%d: couldn't map ports\n", unit); 1097 goto fail; 1098 } 1099 sc->wb_btag = I386_BUS_SPACE_IO; 1100#else 1101 if (!(command & PCIM_CMD_MEMEN)) { 1102 printf("wb%d: failed to enable memory mapping!\n", unit); 1103 goto fail; 1104 } 1105 1106 if (!pci_map_mem(config_id, WB_PCI_LOMEM, &vbase, &pbase)) { 1107 printf ("wb%d: couldn't map memory\n", unit); 1108 goto fail; 1109 } 1110 sc->csr = (volatile caddr_t)vbase; 1111 sc->wb_btag = I386_BUS_SPACE_MEM; 1112 sc->wb_bhandle = vbase; 1113#endif 1114 1115 /* Allocate interrupt */ 1116 if (!pci_map_int(config_id, wb_intr, sc, &net_imask)) { 1117 printf("wb%d: couldn't map interrupt\n", unit); 1118 goto fail; 1119 } 1120 1121 /* Reset the adapter. */ 1122 wb_reset(sc); 1123 1124 /* 1125 * Get station address from the EEPROM. 1126 */ 1127 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 1128 1129 /* 1130 * A Winbond chip was detected. Inform the world. 1131 */ 1132 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1133 1134 sc->wb_unit = unit; 1135 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1136 1137 sc->wb_ldata_ptr = malloc(sizeof(struct wb_list_data) + 8, 1138 M_DEVBUF, M_NOWAIT); 1139 if (sc->wb_ldata_ptr == NULL) { 1140 free(sc, M_DEVBUF); 1141 printf("wb%d: no memory for list buffers!\n", unit); 1142 return; 1143 } 1144 1145 sc->wb_ldata = (struct wb_list_data *)sc->wb_ldata_ptr; 1146 round = (unsigned int)sc->wb_ldata_ptr & 0xF; 1147 roundptr = sc->wb_ldata_ptr; 1148 for (i = 0; i < 8; i++) { 1149 if (round % 8) { 1150 round++; 1151 roundptr++; 1152 } else 1153 break; 1154 } 1155 sc->wb_ldata = (struct wb_list_data *)roundptr; 1156 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 1157 1158 ifp = &sc->arpcom.ac_if; 1159 ifp->if_softc = sc; 1160 ifp->if_unit = unit; 1161 ifp->if_name = "wb"; 1162 ifp->if_mtu = ETHERMTU; 1163 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1164 ifp->if_ioctl = wb_ioctl; 1165 ifp->if_output = ether_output; 1166 ifp->if_start = wb_start; 1167 ifp->if_watchdog = wb_watchdog; 1168 ifp->if_init = wb_init; 1169 ifp->if_baudrate = 10000000; 1170 1171 if (bootverbose) 1172 printf("wb%d: probing for a PHY\n", sc->wb_unit); 1173 for (i = WB_PHYADDR_MIN; i < WB_PHYADDR_MAX + 1; i++) { 1174 if (bootverbose) 1175 printf("wb%d: checking address: %d\n", 1176 sc->wb_unit, i); 1177 sc->wb_phy_addr = i; 1178 wb_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 1179 DELAY(500); 1180 while(wb_phy_readreg(sc, PHY_BMCR) 1181 & PHY_BMCR_RESET); 1182 if ((phy_sts = wb_phy_readreg(sc, PHY_BMSR))) 1183 break; 1184 } 1185 if (phy_sts) { 1186 phy_vid = wb_phy_readreg(sc, PHY_VENID); 1187 phy_did = wb_phy_readreg(sc, PHY_DEVID); 1188 if (bootverbose) 1189 printf("wb%d: found PHY at address %d, ", 1190 sc->wb_unit, sc->wb_phy_addr); 1191 if (bootverbose) 1192 printf("vendor id: %x device id: %x\n", 1193 phy_vid, phy_did); 1194 p = wb_phys; 1195 while(p->wb_vid) { 1196 if (phy_vid == p->wb_vid && 1197 (phy_did | 0x000F) == p->wb_did) { 1198 sc->wb_pinfo = p; 1199 break; 1200 } 1201 p++; 1202 } 1203 if (sc->wb_pinfo == NULL) 1204 sc->wb_pinfo = &wb_phys[PHY_UNKNOWN]; 1205 if (bootverbose) 1206 printf("wb%d: PHY type: %s\n", 1207 sc->wb_unit, sc->wb_pinfo->wb_name); 1208 } else { 1209 printf("wb%d: MII without any phy!\n", sc->wb_unit); 1210 goto fail; 1211 } 1212 1213 /* 1214 * Do ifmedia setup. 1215 */ 1216 ifmedia_init(&sc->ifmedia, 0, wb_ifmedia_upd, wb_ifmedia_sts); 1217 1218 wb_getmode_mii(sc); 1219 wb_autoneg_mii(sc, WB_FLAG_FORCEDELAY, 1); 1220 media = sc->ifmedia.ifm_media; 1221 wb_stop(sc); 1222 1223 ifmedia_set(&sc->ifmedia, media); 1224 1225 /* 1226 * Call MI attach routines. 1227 */ 1228 if_attach(ifp); 1229 ether_ifattach(ifp); 1230 1231#if NBPFILTER > 0 1232 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1233#endif 1234 at_shutdown(wb_shutdown, sc, SHUTDOWN_POST_SYNC); 1235 1236fail: 1237 splx(s); 1238 return; 1239} 1240 1241/* 1242 * Initialize the transmit descriptors. 1243 */ 1244static int wb_list_tx_init(sc) 1245 struct wb_softc *sc; 1246{ 1247 struct wb_chain_data *cd; 1248 struct wb_list_data *ld; 1249 int i; 1250 1251 cd = &sc->wb_cdata; 1252 ld = sc->wb_ldata; 1253 1254 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1255 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1256 if (i == (WB_TX_LIST_CNT - 1)) { 1257 cd->wb_tx_chain[i].wb_nextdesc = 1258 &cd->wb_tx_chain[0]; 1259 } else { 1260 cd->wb_tx_chain[i].wb_nextdesc = 1261 &cd->wb_tx_chain[i + 1]; 1262 } 1263 } 1264 1265 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1266 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1267 1268 return(0); 1269} 1270 1271 1272/* 1273 * Initialize the RX descriptors and allocate mbufs for them. Note that 1274 * we arrange the descriptors in a closed ring, so that the last descriptor 1275 * points back to the first. 1276 */ 1277static int wb_list_rx_init(sc) 1278 struct wb_softc *sc; 1279{ 1280 struct wb_chain_data *cd; 1281 struct wb_list_data *ld; 1282 int i; 1283 1284 cd = &sc->wb_cdata; 1285 ld = sc->wb_ldata; 1286 1287 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1288 cd->wb_rx_chain[i].wb_ptr = 1289 (struct wb_desc *)&ld->wb_rx_list[i]; 1290 if (wb_newbuf(sc, &cd->wb_rx_chain[i]) == ENOBUFS) 1291 return(ENOBUFS); 1292 if (i == (WB_RX_LIST_CNT - 1)) { 1293 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1294 ld->wb_rx_list[i].wb_next = 1295 vtophys(&ld->wb_rx_list[0]); 1296 } else { 1297 cd->wb_rx_chain[i].wb_nextdesc = 1298 &cd->wb_rx_chain[i + 1]; 1299 ld->wb_rx_list[i].wb_next = 1300 vtophys(&ld->wb_rx_list[i + 1]); 1301 } 1302 } 1303 1304 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1305 1306 return(0); 1307} 1308 1309/* 1310 * Initialize an RX descriptor and attach an MBUF cluster. 1311 */ 1312static int wb_newbuf(sc, c) 1313 struct wb_softc *sc; 1314 struct wb_chain_onefrag *c; 1315{ 1316 struct mbuf *m_new = NULL; 1317 1318 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1319 if (m_new == NULL) { 1320 printf("wb%d: no memory for rx list -- packet dropped!\n", 1321 sc->wb_unit); 1322 return(ENOBUFS); 1323 } 1324 1325 MCLGET(m_new, M_DONTWAIT); 1326 if (!(m_new->m_flags & M_EXT)) { 1327 printf("wb%d: no memory for rx list -- packet dropped!\n", 1328 sc->wb_unit); 1329 m_freem(m_new); 1330 return(ENOBUFS); 1331 } 1332 1333 c->wb_mbuf = m_new; 1334 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1335 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | (MCLBYTES - 1); 1336 c->wb_ptr->wb_status = WB_RXSTAT; 1337 1338 return(0); 1339} 1340 1341/* 1342 * A frame has been uploaded: pass the resulting mbuf chain up to 1343 * the higher level protocols. 1344 */ 1345static void wb_rxeof(sc) 1346 struct wb_softc *sc; 1347{ 1348 struct ether_header *eh; 1349 struct mbuf *m; 1350 struct ifnet *ifp; 1351 struct wb_chain_onefrag *cur_rx; 1352 int total_len = 0; 1353 u_int32_t rxstat; 1354 1355 ifp = &sc->arpcom.ac_if; 1356 1357 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1358 WB_RXSTAT_OWN)) { 1359 cur_rx = sc->wb_cdata.wb_rx_head; 1360 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1361 1362 if ((rxstat & WB_RXSTAT_RXERR) || (rxstat & WB_RXSTAT_MIIERR) 1363 || WB_RXBYTES(cur_rx->wb_ptr->wb_status) == 0) { 1364 ifp->if_ierrors++; 1365 wb_reset(sc); 1366 printf("wb%x: receiver babbling: possible chip " 1367 "bug, forcing reset\n", sc->wb_unit); 1368 ifp->if_flags |= IFF_OACTIVE; 1369 ifp->if_timer = 2; 1370 return; 1371 } 1372 1373 /* No errors; receive the packet. */ 1374 m = cur_rx->wb_mbuf; 1375 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1376 1377 /* 1378 * XXX The Winbond chip includes the CRC with every 1379 * received frame, and there's no way to turn this 1380 * behavior off (at least, I can't find anything in 1381 * the manual that explains how to do it) so we have 1382 * to trim off the CRC manually. 1383 */ 1384 total_len -= ETHER_CRC_LEN; 1385 1386 /* 1387 * Try to conjure up a new mbuf cluster. If that 1388 * fails, it means we have an out of memory condition and 1389 * should leave the buffer in place and continue. This will 1390 * result in a lost packet, but there's little else we 1391 * can do in this situation. 1392 */ 1393 if (wb_newbuf(sc, cur_rx) == ENOBUFS) { 1394 ifp->if_ierrors++; 1395 cur_rx->wb_ptr->wb_ctl = 1396 WB_RXCTL_RLINK | (MCLBYTES - 1); 1397 cur_rx->wb_ptr->wb_status = WB_RXSTAT; 1398 continue; 1399 } 1400 1401 ifp->if_ipackets++; 1402 eh = mtod(m, struct ether_header *); 1403 m->m_pkthdr.rcvif = ifp; 1404 m->m_pkthdr.len = m->m_len = total_len; 1405 1406#if NBPFILTER > 0 1407 /* 1408 * Handle BPF listeners. Let the BPF user see the packet, but 1409 * don't pass it up to the ether_input() layer unless it's 1410 * a broadcast packet, multicast packet, matches our ethernet 1411 * address or the interface is in promiscuous mode. 1412 */ 1413 if (ifp->if_bpf) { 1414 bpf_mtap(ifp, m); 1415 if (ifp->if_flags & IFF_PROMISC && 1416 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1417 ETHER_ADDR_LEN) && 1418 (eh->ether_dhost[0] & 1) == 0)) { 1419 m_freem(m); 1420 continue; 1421 } 1422 } 1423#endif 1424 /* Remove header from mbuf and pass it on. */ 1425 m_adj(m, sizeof(struct ether_header)); 1426 ether_input(ifp, eh, m); 1427 } 1428 1429 return; 1430} 1431 1432void wb_rxeoc(sc) 1433 struct wb_softc *sc; 1434{ 1435 wb_rxeof(sc); 1436 1437 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1438 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1439 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1440 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1441 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1442 1443 return; 1444} 1445 1446/* 1447 * A frame was downloaded to the chip. It's safe for us to clean up 1448 * the list buffers. 1449 */ 1450static void wb_txeof(sc) 1451 struct wb_softc *sc; 1452{ 1453 struct wb_chain *cur_tx; 1454 struct ifnet *ifp; 1455 1456 ifp = &sc->arpcom.ac_if; 1457 1458 /* Clear the timeout timer. */ 1459 ifp->if_timer = 0; 1460 1461 if (sc->wb_cdata.wb_tx_head == NULL) 1462 return; 1463 1464 /* 1465 * Go through our tx list and free mbufs for those 1466 * frames that have been transmitted. 1467 */ 1468 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1469 u_int32_t txstat; 1470 1471 cur_tx = sc->wb_cdata.wb_tx_head; 1472 txstat = WB_TXSTATUS(cur_tx); 1473 1474 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1475 break; 1476 1477 if (txstat & WB_TXSTAT_TXERR) { 1478 ifp->if_oerrors++; 1479 if (txstat & WB_TXSTAT_ABORT) 1480 ifp->if_collisions++; 1481 if (txstat & WB_TXSTAT_LATECOLL) 1482 ifp->if_collisions++; 1483 } 1484 1485 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1486 1487 ifp->if_opackets++; 1488 m_freem(cur_tx->wb_mbuf); 1489 cur_tx->wb_mbuf = NULL; 1490 1491 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1492 sc->wb_cdata.wb_tx_head = NULL; 1493 sc->wb_cdata.wb_tx_tail = NULL; 1494 break; 1495 } 1496 1497 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1498 } 1499 1500 return; 1501} 1502 1503/* 1504 * TX 'end of channel' interrupt handler. 1505 */ 1506static void wb_txeoc(sc) 1507 struct wb_softc *sc; 1508{ 1509 struct ifnet *ifp; 1510 1511 ifp = &sc->arpcom.ac_if; 1512 1513 ifp->if_timer = 0; 1514 1515 if (sc->wb_cdata.wb_tx_head == NULL) { 1516 ifp->if_flags &= ~IFF_OACTIVE; 1517 sc->wb_cdata.wb_tx_tail = NULL; 1518 if (sc->wb_want_auto) 1519 wb_autoneg_mii(sc, WB_FLAG_SCHEDDELAY, 1); 1520 } else { 1521 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1522 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1523 ifp->if_timer = 5; 1524 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1525 } 1526 } 1527 1528 return; 1529} 1530 1531static void wb_intr(arg) 1532 void *arg; 1533{ 1534 struct wb_softc *sc; 1535 struct ifnet *ifp; 1536 u_int32_t status; 1537 1538 sc = arg; 1539 ifp = &sc->arpcom.ac_if; 1540 1541 if (!(ifp->if_flags & IFF_UP)) 1542 return; 1543 1544 /* Disable interrupts. */ 1545 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1546 1547 for (;;) { 1548 1549 status = CSR_READ_4(sc, WB_ISR); 1550 if (status) 1551 CSR_WRITE_4(sc, WB_ISR, status); 1552 1553 if ((status & WB_INTRS) == 0) 1554 break; 1555 1556 if (status & WB_ISR_RX_OK) 1557 wb_rxeof(sc); 1558 1559 if (status & WB_ISR_RX_IDLE) 1560 wb_rxeoc(sc); 1561 1562 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1563 ifp->if_ierrors++; 1564 wb_stop(sc); 1565 wb_reset(sc); 1566 wb_init(sc); 1567 } 1568 1569 if (status & WB_ISR_TX_OK) 1570 wb_txeof(sc); 1571 1572 if (status & WB_ISR_TX_NOBUF) 1573 wb_txeoc(sc); 1574 1575 if (status & WB_ISR_TX_IDLE) { 1576 wb_txeof(sc); 1577 if (sc->wb_cdata.wb_tx_head != NULL) { 1578 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1579 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1580 } 1581 } 1582 1583 if (status & WB_ISR_TX_UNDERRUN) { 1584 ifp->if_oerrors++; 1585 wb_txeof(sc); 1586 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1587 /* Jack up TX threshold */ 1588 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1589 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1590 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1591 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1592 } 1593 1594 if (status & WB_ISR_BUS_ERR) { 1595 wb_reset(sc); 1596 wb_init(sc); 1597 } 1598 1599 } 1600 1601 /* Re-enable interrupts. */ 1602 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1603 1604 if (ifp->if_snd.ifq_head != NULL) { 1605 wb_start(ifp); 1606 } 1607 1608 return; 1609} 1610 1611/* 1612 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1613 * pointers to the fragment pointers. 1614 */ 1615static int wb_encap(sc, c, m_head) 1616 struct wb_softc *sc; 1617 struct wb_chain *c; 1618 struct mbuf *m_head; 1619{ 1620 int frag = 0; 1621 struct wb_desc *f = NULL; 1622 int total_len; 1623 struct mbuf *m; 1624 1625 /* 1626 * Start packing the mbufs in this chain into 1627 * the fragment pointers. Stop when we run out 1628 * of fragments or hit the end of the mbuf chain. 1629 */ 1630 m = m_head; 1631 total_len = 0; 1632 1633 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1634 if (m->m_len != 0) { 1635 if (frag == WB_MAXFRAGS) 1636 break; 1637 total_len += m->m_len; 1638 f = &c->wb_ptr->wb_frag[frag]; 1639 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1640 if (frag == 0) { 1641 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1642 f->wb_status = 0; 1643 } else 1644 f->wb_status = WB_TXSTAT_OWN; 1645 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1646 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1647 frag++; 1648 } 1649 } 1650 1651 /* 1652 * Handle special case: we used up all 16 fragments, 1653 * but we have more mbufs left in the chain. Copy the 1654 * data into an mbuf cluster. Note that we don't 1655 * bother clearing the values in the other fragment 1656 * pointers/counters; it wouldn't gain us anything, 1657 * and would waste cycles. 1658 */ 1659 if (m != NULL) { 1660 struct mbuf *m_new = NULL; 1661 1662 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1663 if (m_new == NULL) { 1664 printf("wb%d: no memory for tx list", sc->wb_unit); 1665 return(1); 1666 } 1667 if (m_head->m_pkthdr.len > MHLEN) { 1668 MCLGET(m_new, M_DONTWAIT); 1669 if (!(m_new->m_flags & M_EXT)) { 1670 m_freem(m_new); 1671 printf("wb%d: no memory for tx list", 1672 sc->wb_unit); 1673 return(1); 1674 } 1675 } 1676 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1677 mtod(m_new, caddr_t)); 1678 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1679 m_freem(m_head); 1680 m_head = m_new; 1681 f = &c->wb_ptr->wb_frag[0]; 1682 f->wb_status = 0; 1683 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1684 f->wb_ctl = total_len = m_new->m_len; 1685 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1686 frag = 1; 1687 } 1688 1689 if (total_len < WB_MIN_FRAMELEN) { 1690 f = &c->wb_ptr->wb_frag[frag]; 1691 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1692 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1693 f->wb_ctl |= WB_TXCTL_TLINK; 1694 f->wb_status = WB_TXSTAT_OWN; 1695 frag++; 1696 } 1697 1698 c->wb_mbuf = m_head; 1699 c->wb_lastdesc = frag - 1; 1700 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1701 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1702 1703 return(0); 1704} 1705 1706/* 1707 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1708 * to the mbuf data regions directly in the transmit lists. We also save a 1709 * copy of the pointers since the transmit list fragment pointers are 1710 * physical addresses. 1711 */ 1712 1713static void wb_start(ifp) 1714 struct ifnet *ifp; 1715{ 1716 struct wb_softc *sc; 1717 struct mbuf *m_head = NULL; 1718 struct wb_chain *cur_tx = NULL, *start_tx; 1719 1720 sc = ifp->if_softc; 1721 1722 if (sc->wb_autoneg) { 1723 sc->wb_tx_pend = 1; 1724 return; 1725 } 1726 1727 /* 1728 * Check for an available queue slot. If there are none, 1729 * punt. 1730 */ 1731 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1732 ifp->if_flags |= IFF_OACTIVE; 1733 return; 1734 } 1735 1736 start_tx = sc->wb_cdata.wb_tx_free; 1737 1738 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1739 IF_DEQUEUE(&ifp->if_snd, m_head); 1740 if (m_head == NULL) 1741 break; 1742 1743 /* Pick a descriptor off the free list. */ 1744 cur_tx = sc->wb_cdata.wb_tx_free; 1745 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1746 1747 /* Pack the data into the descriptor. */ 1748 wb_encap(sc, cur_tx, m_head); 1749 1750 if (cur_tx != start_tx) 1751 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1752 1753#if NBPFILTER > 0 1754 /* 1755 * If there's a BPF listener, bounce a copy of this frame 1756 * to him. 1757 */ 1758 if (ifp->if_bpf) 1759 bpf_mtap(ifp, cur_tx->wb_mbuf); 1760#endif 1761 } 1762 1763 /* 1764 * If there are no packets queued, bail. 1765 */ 1766 if (cur_tx == NULL) 1767 return; 1768 1769 /* 1770 * Place the request for the upload interrupt 1771 * in the last descriptor in the chain. This way, if 1772 * we're chaining several packets at once, we'll only 1773 * get an interupt once for the whole chain rather than 1774 * once for each packet. 1775 */ 1776 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1777 sc->wb_cdata.wb_tx_tail = cur_tx; 1778 1779 if (sc->wb_cdata.wb_tx_head == NULL) { 1780 sc->wb_cdata.wb_tx_head = start_tx; 1781 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1782 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1783 } else { 1784 /* 1785 * We need to distinguish between the case where 1786 * the own bit is clear because the chip cleared it 1787 * and where the own bit is clear because we haven't 1788 * set it yet. The magic value WB_UNSET is just some 1789 * ramdomly chosen number which doesn't have the own 1790 * bit set. When we actually transmit the frame, the 1791 * status word will have _only_ the own bit set, so 1792 * the txeoc handler will be able to tell if it needs 1793 * to initiate another transmission to flush out pending 1794 * frames. 1795 */ 1796 WB_TXOWN(start_tx) = WB_UNSENT; 1797 } 1798 1799 /* 1800 * Set a timeout in case the chip goes out to lunch. 1801 */ 1802 ifp->if_timer = 5; 1803 1804 return; 1805} 1806 1807static void wb_init(xsc) 1808 void *xsc; 1809{ 1810 struct wb_softc *sc = xsc; 1811 struct ifnet *ifp = &sc->arpcom.ac_if; 1812 int s, i; 1813 u_int16_t phy_bmcr = 0; 1814 1815 if (sc->wb_autoneg) 1816 return; 1817 1818 s = splimp(); 1819 1820 if (sc->wb_pinfo != NULL) 1821 phy_bmcr = wb_phy_readreg(sc, PHY_BMCR); 1822 1823 /* 1824 * Cancel pending I/O and free all RX/TX buffers. 1825 */ 1826 wb_stop(sc); 1827 wb_reset(sc); 1828 1829 sc->wb_txthresh = WB_TXTHRESH_INIT; 1830 1831 /* 1832 * Set cache alignment and burst length. 1833 */ 1834 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1835 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1836 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1837 1838 /* This doesn't tend to work too well at 100Mbps. */ 1839 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1840 1841 wb_setcfg(sc, phy_bmcr); 1842 1843 /* Init our MAC address */ 1844 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1845 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1846 } 1847 1848 /* Init circular RX list. */ 1849 if (wb_list_rx_init(sc) == ENOBUFS) { 1850 printf("wb%d: initialization failed: no " 1851 "memory for rx buffers\n", sc->wb_unit); 1852 wb_stop(sc); 1853 (void)splx(s); 1854 return; 1855 } 1856 1857 /* Init TX descriptors. */ 1858 wb_list_tx_init(sc); 1859 1860 /* If we want promiscuous mode, set the allframes bit. */ 1861 if (ifp->if_flags & IFF_PROMISC) { 1862 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1863 } else { 1864 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1865 } 1866 1867 /* 1868 * Set capture broadcast bit to capture broadcast frames. 1869 */ 1870 if (ifp->if_flags & IFF_BROADCAST) { 1871 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1872 } else { 1873 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1874 } 1875 1876 /* 1877 * Program the multicast filter, if necessary. 1878 */ 1879 wb_setmulti(sc); 1880 1881 /* 1882 * Load the address of the RX list. 1883 */ 1884 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1885 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1886 1887 /* 1888 * Enable interrupts. 1889 */ 1890 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1891 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1892 1893 /* Enable receiver and transmitter. */ 1894 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1895 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1896 1897 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1898 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1899 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1900 1901 /* Restore state of BMCR */ 1902 if (sc->wb_pinfo != NULL) 1903 wb_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1904 1905 ifp->if_flags |= IFF_RUNNING; 1906 ifp->if_flags &= ~IFF_OACTIVE; 1907 1908 (void)splx(s); 1909 1910 return; 1911} 1912 1913/* 1914 * Set media options. 1915 */ 1916static int wb_ifmedia_upd(ifp) 1917 struct ifnet *ifp; 1918{ 1919 struct wb_softc *sc; 1920 struct ifmedia *ifm; 1921 1922 sc = ifp->if_softc; 1923 ifm = &sc->ifmedia; 1924 1925 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1926 return(EINVAL); 1927 1928 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1929 wb_autoneg_mii(sc, WB_FLAG_SCHEDDELAY, 1); 1930 else 1931 wb_setmode_mii(sc, ifm->ifm_media); 1932 1933 return(0); 1934} 1935 1936/* 1937 * Report current media status. 1938 */ 1939static void wb_ifmedia_sts(ifp, ifmr) 1940 struct ifnet *ifp; 1941 struct ifmediareq *ifmr; 1942{ 1943 struct wb_softc *sc; 1944 u_int16_t advert = 0, ability = 0; 1945 1946 sc = ifp->if_softc; 1947 1948 ifmr->ifm_active = IFM_ETHER; 1949 1950 if (!(wb_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1951 if (wb_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1952 ifmr->ifm_active = IFM_ETHER|IFM_100_TX; 1953 else 1954 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 1955 if (wb_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1956 ifmr->ifm_active |= IFM_FDX; 1957 else 1958 ifmr->ifm_active |= IFM_HDX; 1959 return; 1960 } 1961 1962 ability = wb_phy_readreg(sc, PHY_LPAR); 1963 advert = wb_phy_readreg(sc, PHY_ANAR); 1964 if (advert & PHY_ANAR_100BT4 && 1965 ability & PHY_ANAR_100BT4) { 1966 ifmr->ifm_active = IFM_ETHER|IFM_100_T4; 1967 } else if (advert & PHY_ANAR_100BTXFULL && 1968 ability & PHY_ANAR_100BTXFULL) { 1969 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX; 1970 } else if (advert & PHY_ANAR_100BTXHALF && 1971 ability & PHY_ANAR_100BTXHALF) { 1972 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX; 1973 } else if (advert & PHY_ANAR_10BTFULL && 1974 ability & PHY_ANAR_10BTFULL) { 1975 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX; 1976 } else if (advert & PHY_ANAR_10BTHALF && 1977 ability & PHY_ANAR_10BTHALF) { 1978 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX; 1979 } 1980 1981 return; 1982} 1983 1984static int wb_ioctl(ifp, command, data) 1985 struct ifnet *ifp; 1986 u_long command; 1987 caddr_t data; 1988{ 1989 struct wb_softc *sc = ifp->if_softc; 1990 struct ifreq *ifr = (struct ifreq *) data; 1991 int s, error = 0; 1992 1993 s = splimp(); 1994 1995 switch(command) { 1996 case SIOCSIFADDR: 1997 case SIOCGIFADDR: 1998 case SIOCSIFMTU: 1999 error = ether_ioctl(ifp, command, data); 2000 break; 2001 case SIOCSIFFLAGS: 2002 if (ifp->if_flags & IFF_UP) { 2003 wb_init(sc); 2004 } else { 2005 if (ifp->if_flags & IFF_RUNNING) 2006 wb_stop(sc); 2007 } 2008 error = 0; 2009 break; 2010 case SIOCADDMULTI: 2011 case SIOCDELMULTI: 2012 wb_setmulti(sc); 2013 error = 0; 2014 break; 2015 case SIOCGIFMEDIA: 2016 case SIOCSIFMEDIA: 2017 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2018 break; 2019 default: 2020 error = EINVAL; 2021 break; 2022 } 2023 2024 (void)splx(s); 2025 2026 return(error); 2027} 2028 2029static void wb_watchdog(ifp) 2030 struct ifnet *ifp; 2031{ 2032 struct wb_softc *sc; 2033 2034 sc = ifp->if_softc; 2035 2036 if (sc->wb_autoneg) { 2037 wb_autoneg_mii(sc, WB_FLAG_DELAYTIMEO, 1); 2038 return; 2039 } 2040 2041 ifp->if_oerrors++; 2042 printf("wb%d: watchdog timeout\n", sc->wb_unit); 2043 2044 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 2045 printf("wb%d: no carrier - transceiver cable problem?\n", 2046 sc->wb_unit); 2047 2048 wb_stop(sc); 2049 wb_reset(sc); 2050 wb_init(sc); 2051 2052 if (ifp->if_snd.ifq_head != NULL) 2053 wb_start(ifp); 2054 2055 return; 2056} 2057 2058/* 2059 * Stop the adapter and free any mbufs allocated to the 2060 * RX and TX lists. 2061 */ 2062static void wb_stop(sc) 2063 struct wb_softc *sc; 2064{ 2065 register int i; 2066 struct ifnet *ifp; 2067 2068 ifp = &sc->arpcom.ac_if; 2069 ifp->if_timer = 0; 2070 2071 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 2072 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 2073 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 2074 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 2075 2076 /* 2077 * Free data in the RX lists. 2078 */ 2079 for (i = 0; i < WB_RX_LIST_CNT; i++) { 2080 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 2081 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 2082 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 2083 } 2084 } 2085 bzero((char *)&sc->wb_ldata->wb_rx_list, 2086 sizeof(sc->wb_ldata->wb_rx_list)); 2087 2088 /* 2089 * Free the TX list buffers. 2090 */ 2091 for (i = 0; i < WB_TX_LIST_CNT; i++) { 2092 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 2093 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 2094 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 2095 } 2096 } 2097 2098 bzero((char *)&sc->wb_ldata->wb_tx_list, 2099 sizeof(sc->wb_ldata->wb_tx_list)); 2100 2101 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2102 2103 return; 2104} 2105 2106/* 2107 * Stop all chip I/O so that the kernel's probe routines don't 2108 * get confused by errant DMAs when rebooting. 2109 */ 2110static void wb_shutdown(howto, arg) 2111 int howto; 2112 void *arg; 2113{ 2114 struct wb_softc *sc = (struct wb_softc *)arg; 2115 2116 wb_stop(sc); 2117 2118 return; 2119} 2120 2121static struct pci_device wb_device = { 2122 "wb", 2123 wb_probe, 2124 wb_attach, 2125 &wb_count, 2126 NULL 2127}; 2128DATA_SET(pcidevice_set, wb_device); 2129