if_wb.c revision 229767
1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/wb/if_wb.c 229767 2012-01-07 09:41:57Z kevlo $"); 35 36/* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include <sys/param.h> 87#include <sys/systm.h> 88#include <sys/sockio.h> 89#include <sys/mbuf.h> 90#include <sys/malloc.h> 91#include <sys/module.h> 92#include <sys/kernel.h> 93#include <sys/socket.h> 94#include <sys/queue.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_types.h> 102 103#include <net/bpf.h> 104 105#include <vm/vm.h> /* for vtophys */ 106#include <vm/pmap.h> /* for vtophys */ 107#include <machine/bus.h> 108#include <machine/resource.h> 109#include <sys/bus.h> 110#include <sys/rman.h> 111 112#include <dev/pci/pcireg.h> 113#include <dev/pci/pcivar.h> 114 115#include <dev/mii/mii.h> 116#include <dev/mii/mii_bitbang.h> 117#include <dev/mii/miivar.h> 118 119/* "device miibus" required. See GENERIC if you get errors here. */ 120#include "miibus_if.h" 121 122#define WB_USEIOSPACE 123 124#include <dev/wb/if_wbreg.h> 125 126MODULE_DEPEND(wb, pci, 1, 1, 1); 127MODULE_DEPEND(wb, ether, 1, 1, 1); 128MODULE_DEPEND(wb, miibus, 1, 1, 1); 129 130/* 131 * Various supported device vendors/types and their names. 132 */ 133static const struct wb_type const wb_devs[] = { 134 { WB_VENDORID, WB_DEVICEID_840F, 135 "Winbond W89C840F 10/100BaseTX" }, 136 { CP_VENDORID, CP_DEVICEID_RL100, 137 "Compex RL100-ATX 10/100baseTX" }, 138 { 0, 0, NULL } 139}; 140 141static int wb_probe(device_t); 142static int wb_attach(device_t); 143static int wb_detach(device_t); 144 145static void wb_bfree(void *addr, void *args); 146static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 147 struct mbuf *); 148static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 149 150static void wb_rxeof(struct wb_softc *); 151static void wb_rxeoc(struct wb_softc *); 152static void wb_txeof(struct wb_softc *); 153static void wb_txeoc(struct wb_softc *); 154static void wb_intr(void *); 155static void wb_tick(void *); 156static void wb_start(struct ifnet *); 157static void wb_start_locked(struct ifnet *); 158static int wb_ioctl(struct ifnet *, u_long, caddr_t); 159static void wb_init(void *); 160static void wb_init_locked(struct wb_softc *); 161static void wb_stop(struct wb_softc *); 162static void wb_watchdog(struct wb_softc *); 163static int wb_shutdown(device_t); 164static int wb_ifmedia_upd(struct ifnet *); 165static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 166 167static void wb_eeprom_putbyte(struct wb_softc *, int); 168static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 169static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 170 171static void wb_setcfg(struct wb_softc *, u_int32_t); 172static void wb_setmulti(struct wb_softc *); 173static void wb_reset(struct wb_softc *); 174static void wb_fixmedia(struct wb_softc *); 175static int wb_list_rx_init(struct wb_softc *); 176static int wb_list_tx_init(struct wb_softc *); 177 178static int wb_miibus_readreg(device_t, int, int); 179static int wb_miibus_writereg(device_t, int, int, int); 180static void wb_miibus_statchg(device_t); 181 182/* 183 * MII bit-bang glue 184 */ 185static uint32_t wb_mii_bitbang_read(device_t); 186static void wb_mii_bitbang_write(device_t, uint32_t); 187 188static const struct mii_bitbang_ops wb_mii_bitbang_ops = { 189 wb_mii_bitbang_read, 190 wb_mii_bitbang_write, 191 { 192 WB_SIO_MII_DATAOUT, /* MII_BIT_MDO */ 193 WB_SIO_MII_DATAIN, /* MII_BIT_MDI */ 194 WB_SIO_MII_CLK, /* MII_BIT_MDC */ 195 WB_SIO_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 196 0, /* MII_BIT_DIR_PHY_HOST */ 197 } 198}; 199 200#ifdef WB_USEIOSPACE 201#define WB_RES SYS_RES_IOPORT 202#define WB_RID WB_PCI_LOIO 203#else 204#define WB_RES SYS_RES_MEMORY 205#define WB_RID WB_PCI_LOMEM 206#endif 207 208static device_method_t wb_methods[] = { 209 /* Device interface */ 210 DEVMETHOD(device_probe, wb_probe), 211 DEVMETHOD(device_attach, wb_attach), 212 DEVMETHOD(device_detach, wb_detach), 213 DEVMETHOD(device_shutdown, wb_shutdown), 214 215 /* MII interface */ 216 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 217 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 218 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 219 220 DEVMETHOD_END 221}; 222 223static driver_t wb_driver = { 224 "wb", 225 wb_methods, 226 sizeof(struct wb_softc) 227}; 228 229static devclass_t wb_devclass; 230 231DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 232DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 233 234#define WB_SETBIT(sc, reg, x) \ 235 CSR_WRITE_4(sc, reg, \ 236 CSR_READ_4(sc, reg) | (x)) 237 238#define WB_CLRBIT(sc, reg, x) \ 239 CSR_WRITE_4(sc, reg, \ 240 CSR_READ_4(sc, reg) & ~(x)) 241 242#define SIO_SET(x) \ 243 CSR_WRITE_4(sc, WB_SIO, \ 244 CSR_READ_4(sc, WB_SIO) | (x)) 245 246#define SIO_CLR(x) \ 247 CSR_WRITE_4(sc, WB_SIO, \ 248 CSR_READ_4(sc, WB_SIO) & ~(x)) 249 250/* 251 * Send a read command and address to the EEPROM, check for ACK. 252 */ 253static void 254wb_eeprom_putbyte(sc, addr) 255 struct wb_softc *sc; 256 int addr; 257{ 258 register int d, i; 259 260 d = addr | WB_EECMD_READ; 261 262 /* 263 * Feed in each bit and stobe the clock. 264 */ 265 for (i = 0x400; i; i >>= 1) { 266 if (d & i) { 267 SIO_SET(WB_SIO_EE_DATAIN); 268 } else { 269 SIO_CLR(WB_SIO_EE_DATAIN); 270 } 271 DELAY(100); 272 SIO_SET(WB_SIO_EE_CLK); 273 DELAY(150); 274 SIO_CLR(WB_SIO_EE_CLK); 275 DELAY(100); 276 } 277} 278 279/* 280 * Read a word of data stored in the EEPROM at address 'addr.' 281 */ 282static void 283wb_eeprom_getword(sc, addr, dest) 284 struct wb_softc *sc; 285 int addr; 286 u_int16_t *dest; 287{ 288 register int i; 289 u_int16_t word = 0; 290 291 /* Enter EEPROM access mode. */ 292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 293 294 /* 295 * Send address of word we want to read. 296 */ 297 wb_eeprom_putbyte(sc, addr); 298 299 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 300 301 /* 302 * Start reading bits from EEPROM. 303 */ 304 for (i = 0x8000; i; i >>= 1) { 305 SIO_SET(WB_SIO_EE_CLK); 306 DELAY(100); 307 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 308 word |= i; 309 SIO_CLR(WB_SIO_EE_CLK); 310 DELAY(100); 311 } 312 313 /* Turn off EEPROM access mode. */ 314 CSR_WRITE_4(sc, WB_SIO, 0); 315 316 *dest = word; 317} 318 319/* 320 * Read a sequence of words from the EEPROM. 321 */ 322static void 323wb_read_eeprom(sc, dest, off, cnt, swap) 324 struct wb_softc *sc; 325 caddr_t dest; 326 int off; 327 int cnt; 328 int swap; 329{ 330 int i; 331 u_int16_t word = 0, *ptr; 332 333 for (i = 0; i < cnt; i++) { 334 wb_eeprom_getword(sc, off + i, &word); 335 ptr = (u_int16_t *)(dest + (i * 2)); 336 if (swap) 337 *ptr = ntohs(word); 338 else 339 *ptr = word; 340 } 341} 342 343/* 344 * Read the MII serial port for the MII bit-bang module. 345 */ 346static uint32_t 347wb_mii_bitbang_read(device_t dev) 348{ 349 struct wb_softc *sc; 350 uint32_t val; 351 352 sc = device_get_softc(dev); 353 354 val = CSR_READ_4(sc, WB_SIO); 355 CSR_BARRIER(sc, WB_SIO, 4, 356 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 357 358 return (val); 359} 360 361/* 362 * Write the MII serial port for the MII bit-bang module. 363 */ 364static void 365wb_mii_bitbang_write(device_t dev, uint32_t val) 366{ 367 struct wb_softc *sc; 368 369 sc = device_get_softc(dev); 370 371 CSR_WRITE_4(sc, WB_SIO, val); 372 CSR_BARRIER(sc, WB_SIO, 4, 373 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 374} 375 376static int 377wb_miibus_readreg(dev, phy, reg) 378 device_t dev; 379 int phy, reg; 380{ 381 382 return (mii_bitbang_readreg(dev, &wb_mii_bitbang_ops, phy, reg)); 383} 384 385static int 386wb_miibus_writereg(dev, phy, reg, data) 387 device_t dev; 388 int phy, reg, data; 389{ 390 391 mii_bitbang_writereg(dev, &wb_mii_bitbang_ops, phy, reg, data); 392 393 return(0); 394} 395 396static void 397wb_miibus_statchg(dev) 398 device_t dev; 399{ 400 struct wb_softc *sc; 401 struct mii_data *mii; 402 403 sc = device_get_softc(dev); 404 mii = device_get_softc(sc->wb_miibus); 405 wb_setcfg(sc, mii->mii_media_active); 406} 407 408/* 409 * Program the 64-bit multicast hash filter. 410 */ 411static void 412wb_setmulti(sc) 413 struct wb_softc *sc; 414{ 415 struct ifnet *ifp; 416 int h = 0; 417 u_int32_t hashes[2] = { 0, 0 }; 418 struct ifmultiaddr *ifma; 419 u_int32_t rxfilt; 420 int mcnt = 0; 421 422 ifp = sc->wb_ifp; 423 424 rxfilt = CSR_READ_4(sc, WB_NETCFG); 425 426 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 427 rxfilt |= WB_NETCFG_RX_MULTI; 428 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 429 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 430 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 431 return; 432 } 433 434 /* first, zot all the existing hash bits */ 435 CSR_WRITE_4(sc, WB_MAR0, 0); 436 CSR_WRITE_4(sc, WB_MAR1, 0); 437 438 /* now program new ones */ 439 if_maddr_rlock(ifp); 440 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 441 if (ifma->ifma_addr->sa_family != AF_LINK) 442 continue; 443 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 444 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 445 if (h < 32) 446 hashes[0] |= (1 << h); 447 else 448 hashes[1] |= (1 << (h - 32)); 449 mcnt++; 450 } 451 if_maddr_runlock(ifp); 452 453 if (mcnt) 454 rxfilt |= WB_NETCFG_RX_MULTI; 455 else 456 rxfilt &= ~WB_NETCFG_RX_MULTI; 457 458 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 459 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 460 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 461} 462 463/* 464 * The Winbond manual states that in order to fiddle with the 465 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 466 * first have to put the transmit and/or receive logic in the idle state. 467 */ 468static void 469wb_setcfg(sc, media) 470 struct wb_softc *sc; 471 u_int32_t media; 472{ 473 int i, restart = 0; 474 475 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 476 restart = 1; 477 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 478 479 for (i = 0; i < WB_TIMEOUT; i++) { 480 DELAY(10); 481 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 482 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 483 break; 484 } 485 486 if (i == WB_TIMEOUT) 487 device_printf(sc->wb_dev, 488 "failed to force tx and rx to idle state\n"); 489 } 490 491 if (IFM_SUBTYPE(media) == IFM_10_T) 492 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 493 else 494 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 495 496 if ((media & IFM_GMASK) == IFM_FDX) 497 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 498 else 499 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 500 501 if (restart) 502 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 503} 504 505static void 506wb_reset(sc) 507 struct wb_softc *sc; 508{ 509 register int i; 510 struct mii_data *mii; 511 struct mii_softc *miisc; 512 513 CSR_WRITE_4(sc, WB_NETCFG, 0); 514 CSR_WRITE_4(sc, WB_BUSCTL, 0); 515 CSR_WRITE_4(sc, WB_TXADDR, 0); 516 CSR_WRITE_4(sc, WB_RXADDR, 0); 517 518 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 519 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 520 521 for (i = 0; i < WB_TIMEOUT; i++) { 522 DELAY(10); 523 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 524 break; 525 } 526 if (i == WB_TIMEOUT) 527 device_printf(sc->wb_dev, "reset never completed!\n"); 528 529 /* Wait a little while for the chip to get its brains in order. */ 530 DELAY(1000); 531 532 if (sc->wb_miibus == NULL) 533 return; 534 535 mii = device_get_softc(sc->wb_miibus); 536 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 537 PHY_RESET(miisc); 538} 539 540static void 541wb_fixmedia(sc) 542 struct wb_softc *sc; 543{ 544 struct mii_data *mii = NULL; 545 struct ifnet *ifp; 546 u_int32_t media; 547 548 mii = device_get_softc(sc->wb_miibus); 549 ifp = sc->wb_ifp; 550 551 mii_pollstat(mii); 552 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 553 media = mii->mii_media_active & ~IFM_10_T; 554 media |= IFM_100_TX; 555 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 556 media = mii->mii_media_active & ~IFM_100_TX; 557 media |= IFM_10_T; 558 } else 559 return; 560 561 ifmedia_set(&mii->mii_media, media); 562} 563 564/* 565 * Probe for a Winbond chip. Check the PCI vendor and device 566 * IDs against our list and return a device name if we find a match. 567 */ 568static int 569wb_probe(dev) 570 device_t dev; 571{ 572 const struct wb_type *t; 573 574 t = wb_devs; 575 576 while(t->wb_name != NULL) { 577 if ((pci_get_vendor(dev) == t->wb_vid) && 578 (pci_get_device(dev) == t->wb_did)) { 579 device_set_desc(dev, t->wb_name); 580 return (BUS_PROBE_DEFAULT); 581 } 582 t++; 583 } 584 585 return(ENXIO); 586} 587 588/* 589 * Attach the interface. Allocate softc structures, do ifmedia 590 * setup and ethernet/BPF attach. 591 */ 592static int 593wb_attach(dev) 594 device_t dev; 595{ 596 u_char eaddr[ETHER_ADDR_LEN]; 597 struct wb_softc *sc; 598 struct ifnet *ifp; 599 int error = 0, rid; 600 601 sc = device_get_softc(dev); 602 sc->wb_dev = dev; 603 604 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 605 MTX_DEF); 606 callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0); 607 608 /* 609 * Map control/status registers. 610 */ 611 pci_enable_busmaster(dev); 612 613 rid = WB_RID; 614 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 615 616 if (sc->wb_res == NULL) { 617 device_printf(dev, "couldn't map ports/memory\n"); 618 error = ENXIO; 619 goto fail; 620 } 621 622 /* Allocate interrupt */ 623 rid = 0; 624 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 625 RF_SHAREABLE | RF_ACTIVE); 626 627 if (sc->wb_irq == NULL) { 628 device_printf(dev, "couldn't map interrupt\n"); 629 error = ENXIO; 630 goto fail; 631 } 632 633 /* Save the cache line size. */ 634 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 635 636 /* Reset the adapter. */ 637 wb_reset(sc); 638 639 /* 640 * Get station address from the EEPROM. 641 */ 642 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 643 644 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 645 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 646 647 if (sc->wb_ldata == NULL) { 648 device_printf(dev, "no memory for list buffers!\n"); 649 error = ENXIO; 650 goto fail; 651 } 652 653 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 654 655 ifp = sc->wb_ifp = if_alloc(IFT_ETHER); 656 if (ifp == NULL) { 657 device_printf(dev, "can not if_alloc()\n"); 658 error = ENOSPC; 659 goto fail; 660 } 661 ifp->if_softc = sc; 662 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 663 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 664 ifp->if_ioctl = wb_ioctl; 665 ifp->if_start = wb_start; 666 ifp->if_init = wb_init; 667 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 668 669 /* 670 * Do MII setup. 671 */ 672 error = mii_attach(dev, &sc->wb_miibus, ifp, wb_ifmedia_upd, 673 wb_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 674 if (error != 0) { 675 device_printf(dev, "attaching PHYs failed\n"); 676 goto fail; 677 } 678 679 /* 680 * Call MI attach routine. 681 */ 682 ether_ifattach(ifp, eaddr); 683 684 /* Hook interrupt last to avoid having to lock softc */ 685 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE, 686 NULL, wb_intr, sc, &sc->wb_intrhand); 687 688 if (error) { 689 device_printf(dev, "couldn't set up irq\n"); 690 ether_ifdetach(ifp); 691 goto fail; 692 } 693 694fail: 695 if (error) 696 wb_detach(dev); 697 698 return(error); 699} 700 701/* 702 * Shutdown hardware and free up resources. This can be called any 703 * time after the mutex has been initialized. It is called in both 704 * the error case in attach and the normal detach case so it needs 705 * to be careful about only freeing resources that have actually been 706 * allocated. 707 */ 708static int 709wb_detach(dev) 710 device_t dev; 711{ 712 struct wb_softc *sc; 713 struct ifnet *ifp; 714 715 sc = device_get_softc(dev); 716 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 717 ifp = sc->wb_ifp; 718 719 /* 720 * Delete any miibus and phy devices attached to this interface. 721 * This should only be done if attach succeeded. 722 */ 723 if (device_is_attached(dev)) { 724 ether_ifdetach(ifp); 725 WB_LOCK(sc); 726 wb_stop(sc); 727 WB_UNLOCK(sc); 728 callout_drain(&sc->wb_stat_callout); 729 } 730 if (sc->wb_miibus) 731 device_delete_child(dev, sc->wb_miibus); 732 bus_generic_detach(dev); 733 734 if (sc->wb_intrhand) 735 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 736 if (sc->wb_irq) 737 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 738 if (sc->wb_res) 739 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 740 741 if (ifp) 742 if_free(ifp); 743 744 if (sc->wb_ldata) { 745 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 746 M_DEVBUF); 747 } 748 749 mtx_destroy(&sc->wb_mtx); 750 751 return(0); 752} 753 754/* 755 * Initialize the transmit descriptors. 756 */ 757static int 758wb_list_tx_init(sc) 759 struct wb_softc *sc; 760{ 761 struct wb_chain_data *cd; 762 struct wb_list_data *ld; 763 int i; 764 765 cd = &sc->wb_cdata; 766 ld = sc->wb_ldata; 767 768 for (i = 0; i < WB_TX_LIST_CNT; i++) { 769 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 770 if (i == (WB_TX_LIST_CNT - 1)) { 771 cd->wb_tx_chain[i].wb_nextdesc = 772 &cd->wb_tx_chain[0]; 773 } else { 774 cd->wb_tx_chain[i].wb_nextdesc = 775 &cd->wb_tx_chain[i + 1]; 776 } 777 } 778 779 cd->wb_tx_free = &cd->wb_tx_chain[0]; 780 cd->wb_tx_tail = cd->wb_tx_head = NULL; 781 782 return(0); 783} 784 785 786/* 787 * Initialize the RX descriptors and allocate mbufs for them. Note that 788 * we arrange the descriptors in a closed ring, so that the last descriptor 789 * points back to the first. 790 */ 791static int 792wb_list_rx_init(sc) 793 struct wb_softc *sc; 794{ 795 struct wb_chain_data *cd; 796 struct wb_list_data *ld; 797 int i; 798 799 cd = &sc->wb_cdata; 800 ld = sc->wb_ldata; 801 802 for (i = 0; i < WB_RX_LIST_CNT; i++) { 803 cd->wb_rx_chain[i].wb_ptr = 804 (struct wb_desc *)&ld->wb_rx_list[i]; 805 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 806 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 807 return(ENOBUFS); 808 if (i == (WB_RX_LIST_CNT - 1)) { 809 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 810 ld->wb_rx_list[i].wb_next = 811 vtophys(&ld->wb_rx_list[0]); 812 } else { 813 cd->wb_rx_chain[i].wb_nextdesc = 814 &cd->wb_rx_chain[i + 1]; 815 ld->wb_rx_list[i].wb_next = 816 vtophys(&ld->wb_rx_list[i + 1]); 817 } 818 } 819 820 cd->wb_rx_head = &cd->wb_rx_chain[0]; 821 822 return(0); 823} 824 825static void 826wb_bfree(buf, args) 827 void *buf; 828 void *args; 829{ 830 831} 832 833/* 834 * Initialize an RX descriptor and attach an MBUF cluster. 835 */ 836static int 837wb_newbuf(sc, c, m) 838 struct wb_softc *sc; 839 struct wb_chain_onefrag *c; 840 struct mbuf *m; 841{ 842 struct mbuf *m_new = NULL; 843 844 if (m == NULL) { 845 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 846 if (m_new == NULL) 847 return(ENOBUFS); 848 m_new->m_data = c->wb_buf; 849 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 850 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, c->wb_buf, 851 NULL, 0, EXT_NET_DRV); 852 } else { 853 m_new = m; 854 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 855 m_new->m_data = m_new->m_ext.ext_buf; 856 } 857 858 m_adj(m_new, sizeof(u_int64_t)); 859 860 c->wb_mbuf = m_new; 861 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 862 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 863 c->wb_ptr->wb_status = WB_RXSTAT; 864 865 return(0); 866} 867 868/* 869 * A frame has been uploaded: pass the resulting mbuf chain up to 870 * the higher level protocols. 871 */ 872static void 873wb_rxeof(sc) 874 struct wb_softc *sc; 875{ 876 struct mbuf *m = NULL; 877 struct ifnet *ifp; 878 struct wb_chain_onefrag *cur_rx; 879 int total_len = 0; 880 u_int32_t rxstat; 881 882 WB_LOCK_ASSERT(sc); 883 884 ifp = sc->wb_ifp; 885 886 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 887 WB_RXSTAT_OWN)) { 888 struct mbuf *m0 = NULL; 889 890 cur_rx = sc->wb_cdata.wb_rx_head; 891 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 892 893 m = cur_rx->wb_mbuf; 894 895 if ((rxstat & WB_RXSTAT_MIIERR) || 896 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 897 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 898 !(rxstat & WB_RXSTAT_LASTFRAG) || 899 !(rxstat & WB_RXSTAT_RXCMP)) { 900 ifp->if_ierrors++; 901 wb_newbuf(sc, cur_rx, m); 902 device_printf(sc->wb_dev, 903 "receiver babbling: possible chip bug," 904 " forcing reset\n"); 905 wb_fixmedia(sc); 906 wb_reset(sc); 907 wb_init_locked(sc); 908 return; 909 } 910 911 if (rxstat & WB_RXSTAT_RXERR) { 912 ifp->if_ierrors++; 913 wb_newbuf(sc, cur_rx, m); 914 break; 915 } 916 917 /* No errors; receive the packet. */ 918 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 919 920 /* 921 * XXX The Winbond chip includes the CRC with every 922 * received frame, and there's no way to turn this 923 * behavior off (at least, I can't find anything in 924 * the manual that explains how to do it) so we have 925 * to trim off the CRC manually. 926 */ 927 total_len -= ETHER_CRC_LEN; 928 929 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 930 NULL); 931 wb_newbuf(sc, cur_rx, m); 932 if (m0 == NULL) { 933 ifp->if_ierrors++; 934 break; 935 } 936 m = m0; 937 938 ifp->if_ipackets++; 939 WB_UNLOCK(sc); 940 (*ifp->if_input)(ifp, m); 941 WB_LOCK(sc); 942 } 943} 944 945static void 946wb_rxeoc(sc) 947 struct wb_softc *sc; 948{ 949 wb_rxeof(sc); 950 951 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 952 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 953 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 954 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 955 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 956} 957 958/* 959 * A frame was downloaded to the chip. It's safe for us to clean up 960 * the list buffers. 961 */ 962static void 963wb_txeof(sc) 964 struct wb_softc *sc; 965{ 966 struct wb_chain *cur_tx; 967 struct ifnet *ifp; 968 969 ifp = sc->wb_ifp; 970 971 /* Clear the timeout timer. */ 972 sc->wb_timer = 0; 973 974 if (sc->wb_cdata.wb_tx_head == NULL) 975 return; 976 977 /* 978 * Go through our tx list and free mbufs for those 979 * frames that have been transmitted. 980 */ 981 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 982 u_int32_t txstat; 983 984 cur_tx = sc->wb_cdata.wb_tx_head; 985 txstat = WB_TXSTATUS(cur_tx); 986 987 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 988 break; 989 990 if (txstat & WB_TXSTAT_TXERR) { 991 ifp->if_oerrors++; 992 if (txstat & WB_TXSTAT_ABORT) 993 ifp->if_collisions++; 994 if (txstat & WB_TXSTAT_LATECOLL) 995 ifp->if_collisions++; 996 } 997 998 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 999 1000 ifp->if_opackets++; 1001 m_freem(cur_tx->wb_mbuf); 1002 cur_tx->wb_mbuf = NULL; 1003 1004 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1005 sc->wb_cdata.wb_tx_head = NULL; 1006 sc->wb_cdata.wb_tx_tail = NULL; 1007 break; 1008 } 1009 1010 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1011 } 1012} 1013 1014/* 1015 * TX 'end of channel' interrupt handler. 1016 */ 1017static void 1018wb_txeoc(sc) 1019 struct wb_softc *sc; 1020{ 1021 struct ifnet *ifp; 1022 1023 ifp = sc->wb_ifp; 1024 1025 sc->wb_timer = 0; 1026 1027 if (sc->wb_cdata.wb_tx_head == NULL) { 1028 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1029 sc->wb_cdata.wb_tx_tail = NULL; 1030 } else { 1031 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1032 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1033 sc->wb_timer = 5; 1034 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1035 } 1036 } 1037} 1038 1039static void 1040wb_intr(arg) 1041 void *arg; 1042{ 1043 struct wb_softc *sc; 1044 struct ifnet *ifp; 1045 u_int32_t status; 1046 1047 sc = arg; 1048 WB_LOCK(sc); 1049 ifp = sc->wb_ifp; 1050 1051 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1052 WB_UNLOCK(sc); 1053 return; 1054 } 1055 1056 /* Disable interrupts. */ 1057 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1058 1059 for (;;) { 1060 1061 status = CSR_READ_4(sc, WB_ISR); 1062 if (status) 1063 CSR_WRITE_4(sc, WB_ISR, status); 1064 1065 if ((status & WB_INTRS) == 0) 1066 break; 1067 1068 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1069 ifp->if_ierrors++; 1070 wb_reset(sc); 1071 if (status & WB_ISR_RX_ERR) 1072 wb_fixmedia(sc); 1073 wb_init_locked(sc); 1074 continue; 1075 } 1076 1077 if (status & WB_ISR_RX_OK) 1078 wb_rxeof(sc); 1079 1080 if (status & WB_ISR_RX_IDLE) 1081 wb_rxeoc(sc); 1082 1083 if (status & WB_ISR_TX_OK) 1084 wb_txeof(sc); 1085 1086 if (status & WB_ISR_TX_NOBUF) 1087 wb_txeoc(sc); 1088 1089 if (status & WB_ISR_TX_IDLE) { 1090 wb_txeof(sc); 1091 if (sc->wb_cdata.wb_tx_head != NULL) { 1092 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1093 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1094 } 1095 } 1096 1097 if (status & WB_ISR_TX_UNDERRUN) { 1098 ifp->if_oerrors++; 1099 wb_txeof(sc); 1100 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1101 /* Jack up TX threshold */ 1102 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1103 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1104 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1105 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1106 } 1107 1108 if (status & WB_ISR_BUS_ERR) { 1109 wb_reset(sc); 1110 wb_init_locked(sc); 1111 } 1112 1113 } 1114 1115 /* Re-enable interrupts. */ 1116 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1117 1118 if (ifp->if_snd.ifq_head != NULL) { 1119 wb_start_locked(ifp); 1120 } 1121 1122 WB_UNLOCK(sc); 1123} 1124 1125static void 1126wb_tick(xsc) 1127 void *xsc; 1128{ 1129 struct wb_softc *sc; 1130 struct mii_data *mii; 1131 1132 sc = xsc; 1133 WB_LOCK_ASSERT(sc); 1134 mii = device_get_softc(sc->wb_miibus); 1135 1136 mii_tick(mii); 1137 1138 if (sc->wb_timer > 0 && --sc->wb_timer == 0) 1139 wb_watchdog(sc); 1140 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 1141} 1142 1143/* 1144 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1145 * pointers to the fragment pointers. 1146 */ 1147static int 1148wb_encap(sc, c, m_head) 1149 struct wb_softc *sc; 1150 struct wb_chain *c; 1151 struct mbuf *m_head; 1152{ 1153 int frag = 0; 1154 struct wb_desc *f = NULL; 1155 int total_len; 1156 struct mbuf *m; 1157 1158 /* 1159 * Start packing the mbufs in this chain into 1160 * the fragment pointers. Stop when we run out 1161 * of fragments or hit the end of the mbuf chain. 1162 */ 1163 m = m_head; 1164 total_len = 0; 1165 1166 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1167 if (m->m_len != 0) { 1168 if (frag == WB_MAXFRAGS) 1169 break; 1170 total_len += m->m_len; 1171 f = &c->wb_ptr->wb_frag[frag]; 1172 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1173 if (frag == 0) { 1174 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1175 f->wb_status = 0; 1176 } else 1177 f->wb_status = WB_TXSTAT_OWN; 1178 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1179 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1180 frag++; 1181 } 1182 } 1183 1184 /* 1185 * Handle special case: we used up all 16 fragments, 1186 * but we have more mbufs left in the chain. Copy the 1187 * data into an mbuf cluster. Note that we don't 1188 * bother clearing the values in the other fragment 1189 * pointers/counters; it wouldn't gain us anything, 1190 * and would waste cycles. 1191 */ 1192 if (m != NULL) { 1193 struct mbuf *m_new = NULL; 1194 1195 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1196 if (m_new == NULL) 1197 return(1); 1198 if (m_head->m_pkthdr.len > MHLEN) { 1199 MCLGET(m_new, M_DONTWAIT); 1200 if (!(m_new->m_flags & M_EXT)) { 1201 m_freem(m_new); 1202 return(1); 1203 } 1204 } 1205 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1206 mtod(m_new, caddr_t)); 1207 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1208 m_freem(m_head); 1209 m_head = m_new; 1210 f = &c->wb_ptr->wb_frag[0]; 1211 f->wb_status = 0; 1212 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1213 f->wb_ctl = total_len = m_new->m_len; 1214 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1215 frag = 1; 1216 } 1217 1218 if (total_len < WB_MIN_FRAMELEN) { 1219 f = &c->wb_ptr->wb_frag[frag]; 1220 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1221 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1222 f->wb_ctl |= WB_TXCTL_TLINK; 1223 f->wb_status = WB_TXSTAT_OWN; 1224 frag++; 1225 } 1226 1227 c->wb_mbuf = m_head; 1228 c->wb_lastdesc = frag - 1; 1229 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1230 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1231 1232 return(0); 1233} 1234 1235/* 1236 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1237 * to the mbuf data regions directly in the transmit lists. We also save a 1238 * copy of the pointers since the transmit list fragment pointers are 1239 * physical addresses. 1240 */ 1241 1242static void 1243wb_start(ifp) 1244 struct ifnet *ifp; 1245{ 1246 struct wb_softc *sc; 1247 1248 sc = ifp->if_softc; 1249 WB_LOCK(sc); 1250 wb_start_locked(ifp); 1251 WB_UNLOCK(sc); 1252} 1253 1254static void 1255wb_start_locked(ifp) 1256 struct ifnet *ifp; 1257{ 1258 struct wb_softc *sc; 1259 struct mbuf *m_head = NULL; 1260 struct wb_chain *cur_tx = NULL, *start_tx; 1261 1262 sc = ifp->if_softc; 1263 WB_LOCK_ASSERT(sc); 1264 1265 /* 1266 * Check for an available queue slot. If there are none, 1267 * punt. 1268 */ 1269 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1270 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1271 return; 1272 } 1273 1274 start_tx = sc->wb_cdata.wb_tx_free; 1275 1276 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1277 IF_DEQUEUE(&ifp->if_snd, m_head); 1278 if (m_head == NULL) 1279 break; 1280 1281 /* Pick a descriptor off the free list. */ 1282 cur_tx = sc->wb_cdata.wb_tx_free; 1283 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1284 1285 /* Pack the data into the descriptor. */ 1286 wb_encap(sc, cur_tx, m_head); 1287 1288 if (cur_tx != start_tx) 1289 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1290 1291 /* 1292 * If there's a BPF listener, bounce a copy of this frame 1293 * to him. 1294 */ 1295 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1296 } 1297 1298 /* 1299 * If there are no packets queued, bail. 1300 */ 1301 if (cur_tx == NULL) 1302 return; 1303 1304 /* 1305 * Place the request for the upload interrupt 1306 * in the last descriptor in the chain. This way, if 1307 * we're chaining several packets at once, we'll only 1308 * get an interrupt once for the whole chain rather than 1309 * once for each packet. 1310 */ 1311 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1312 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1313 sc->wb_cdata.wb_tx_tail = cur_tx; 1314 1315 if (sc->wb_cdata.wb_tx_head == NULL) { 1316 sc->wb_cdata.wb_tx_head = start_tx; 1317 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1318 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1319 } else { 1320 /* 1321 * We need to distinguish between the case where 1322 * the own bit is clear because the chip cleared it 1323 * and where the own bit is clear because we haven't 1324 * set it yet. The magic value WB_UNSET is just some 1325 * ramdomly chosen number which doesn't have the own 1326 * bit set. When we actually transmit the frame, the 1327 * status word will have _only_ the own bit set, so 1328 * the txeoc handler will be able to tell if it needs 1329 * to initiate another transmission to flush out pending 1330 * frames. 1331 */ 1332 WB_TXOWN(start_tx) = WB_UNSENT; 1333 } 1334 1335 /* 1336 * Set a timeout in case the chip goes out to lunch. 1337 */ 1338 sc->wb_timer = 5; 1339} 1340 1341static void 1342wb_init(xsc) 1343 void *xsc; 1344{ 1345 struct wb_softc *sc = xsc; 1346 1347 WB_LOCK(sc); 1348 wb_init_locked(sc); 1349 WB_UNLOCK(sc); 1350} 1351 1352static void 1353wb_init_locked(sc) 1354 struct wb_softc *sc; 1355{ 1356 struct ifnet *ifp = sc->wb_ifp; 1357 int i; 1358 struct mii_data *mii; 1359 1360 WB_LOCK_ASSERT(sc); 1361 mii = device_get_softc(sc->wb_miibus); 1362 1363 /* 1364 * Cancel pending I/O and free all RX/TX buffers. 1365 */ 1366 wb_stop(sc); 1367 wb_reset(sc); 1368 1369 sc->wb_txthresh = WB_TXTHRESH_INIT; 1370 1371 /* 1372 * Set cache alignment and burst length. 1373 */ 1374#ifdef foo 1375 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1376 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1377 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1378#endif 1379 1380 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1381 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1382 switch(sc->wb_cachesize) { 1383 case 32: 1384 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1385 break; 1386 case 16: 1387 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1388 break; 1389 case 8: 1390 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1391 break; 1392 case 0: 1393 default: 1394 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1395 break; 1396 } 1397 1398 /* This doesn't tend to work too well at 100Mbps. */ 1399 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1400 1401 /* Init our MAC address */ 1402 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1403 CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]); 1404 } 1405 1406 /* Init circular RX list. */ 1407 if (wb_list_rx_init(sc) == ENOBUFS) { 1408 device_printf(sc->wb_dev, 1409 "initialization failed: no memory for rx buffers\n"); 1410 wb_stop(sc); 1411 return; 1412 } 1413 1414 /* Init TX descriptors. */ 1415 wb_list_tx_init(sc); 1416 1417 /* If we want promiscuous mode, set the allframes bit. */ 1418 if (ifp->if_flags & IFF_PROMISC) { 1419 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1420 } else { 1421 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1422 } 1423 1424 /* 1425 * Set capture broadcast bit to capture broadcast frames. 1426 */ 1427 if (ifp->if_flags & IFF_BROADCAST) { 1428 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1429 } else { 1430 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1431 } 1432 1433 /* 1434 * Program the multicast filter, if necessary. 1435 */ 1436 wb_setmulti(sc); 1437 1438 /* 1439 * Load the address of the RX list. 1440 */ 1441 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1442 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1443 1444 /* 1445 * Enable interrupts. 1446 */ 1447 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1448 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1449 1450 /* Enable receiver and transmitter. */ 1451 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1452 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1453 1454 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1455 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1456 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1457 1458 mii_mediachg(mii); 1459 1460 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1461 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1462 1463 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 1464} 1465 1466/* 1467 * Set media options. 1468 */ 1469static int 1470wb_ifmedia_upd(ifp) 1471 struct ifnet *ifp; 1472{ 1473 struct wb_softc *sc; 1474 1475 sc = ifp->if_softc; 1476 1477 WB_LOCK(sc); 1478 if (ifp->if_flags & IFF_UP) 1479 wb_init_locked(sc); 1480 WB_UNLOCK(sc); 1481 1482 return(0); 1483} 1484 1485/* 1486 * Report current media status. 1487 */ 1488static void 1489wb_ifmedia_sts(ifp, ifmr) 1490 struct ifnet *ifp; 1491 struct ifmediareq *ifmr; 1492{ 1493 struct wb_softc *sc; 1494 struct mii_data *mii; 1495 1496 sc = ifp->if_softc; 1497 1498 WB_LOCK(sc); 1499 mii = device_get_softc(sc->wb_miibus); 1500 1501 mii_pollstat(mii); 1502 ifmr->ifm_active = mii->mii_media_active; 1503 ifmr->ifm_status = mii->mii_media_status; 1504 WB_UNLOCK(sc); 1505} 1506 1507static int 1508wb_ioctl(ifp, command, data) 1509 struct ifnet *ifp; 1510 u_long command; 1511 caddr_t data; 1512{ 1513 struct wb_softc *sc = ifp->if_softc; 1514 struct mii_data *mii; 1515 struct ifreq *ifr = (struct ifreq *) data; 1516 int error = 0; 1517 1518 switch(command) { 1519 case SIOCSIFFLAGS: 1520 WB_LOCK(sc); 1521 if (ifp->if_flags & IFF_UP) { 1522 wb_init_locked(sc); 1523 } else { 1524 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1525 wb_stop(sc); 1526 } 1527 WB_UNLOCK(sc); 1528 error = 0; 1529 break; 1530 case SIOCADDMULTI: 1531 case SIOCDELMULTI: 1532 WB_LOCK(sc); 1533 wb_setmulti(sc); 1534 WB_UNLOCK(sc); 1535 error = 0; 1536 break; 1537 case SIOCGIFMEDIA: 1538 case SIOCSIFMEDIA: 1539 mii = device_get_softc(sc->wb_miibus); 1540 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1541 break; 1542 default: 1543 error = ether_ioctl(ifp, command, data); 1544 break; 1545 } 1546 1547 return(error); 1548} 1549 1550static void 1551wb_watchdog(sc) 1552 struct wb_softc *sc; 1553{ 1554 struct ifnet *ifp; 1555 1556 WB_LOCK_ASSERT(sc); 1557 ifp = sc->wb_ifp; 1558 ifp->if_oerrors++; 1559 if_printf(ifp, "watchdog timeout\n"); 1560#ifdef foo 1561 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1562 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 1563#endif 1564 wb_stop(sc); 1565 wb_reset(sc); 1566 wb_init_locked(sc); 1567 1568 if (ifp->if_snd.ifq_head != NULL) 1569 wb_start_locked(ifp); 1570} 1571 1572/* 1573 * Stop the adapter and free any mbufs allocated to the 1574 * RX and TX lists. 1575 */ 1576static void 1577wb_stop(sc) 1578 struct wb_softc *sc; 1579{ 1580 register int i; 1581 struct ifnet *ifp; 1582 1583 WB_LOCK_ASSERT(sc); 1584 ifp = sc->wb_ifp; 1585 sc->wb_timer = 0; 1586 1587 callout_stop(&sc->wb_stat_callout); 1588 1589 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1590 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1591 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1592 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1593 1594 /* 1595 * Free data in the RX lists. 1596 */ 1597 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1598 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1599 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1600 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1601 } 1602 } 1603 bzero((char *)&sc->wb_ldata->wb_rx_list, 1604 sizeof(sc->wb_ldata->wb_rx_list)); 1605 1606 /* 1607 * Free the TX list buffers. 1608 */ 1609 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1610 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1611 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1612 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1613 } 1614 } 1615 1616 bzero((char *)&sc->wb_ldata->wb_tx_list, 1617 sizeof(sc->wb_ldata->wb_tx_list)); 1618 1619 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1620} 1621 1622/* 1623 * Stop all chip I/O so that the kernel's probe routines don't 1624 * get confused by errant DMAs when rebooting. 1625 */ 1626static int 1627wb_shutdown(dev) 1628 device_t dev; 1629{ 1630 struct wb_softc *sc; 1631 1632 sc = device_get_softc(dev); 1633 1634 WB_LOCK(sc); 1635 wb_stop(sc); 1636 WB_UNLOCK(sc); 1637 1638 return (0); 1639} 1640