if_wb.c revision 199560
1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/wb/if_wb.c 199560 2009-11-19 22:14:23Z jhb $"); 35 36/* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include <sys/param.h> 87#include <sys/systm.h> 88#include <sys/sockio.h> 89#include <sys/mbuf.h> 90#include <sys/malloc.h> 91#include <sys/module.h> 92#include <sys/kernel.h> 93#include <sys/socket.h> 94#include <sys/queue.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_types.h> 102 103#include <net/bpf.h> 104 105#include <vm/vm.h> /* for vtophys */ 106#include <vm/pmap.h> /* for vtophys */ 107#include <machine/bus.h> 108#include <machine/resource.h> 109#include <sys/bus.h> 110#include <sys/rman.h> 111 112#include <dev/pci/pcireg.h> 113#include <dev/pci/pcivar.h> 114 115#include <dev/mii/mii.h> 116#include <dev/mii/miivar.h> 117 118/* "device miibus" required. See GENERIC if you get errors here. */ 119#include "miibus_if.h" 120 121#define WB_USEIOSPACE 122 123#include <dev/wb/if_wbreg.h> 124 125MODULE_DEPEND(wb, pci, 1, 1, 1); 126MODULE_DEPEND(wb, ether, 1, 1, 1); 127MODULE_DEPEND(wb, miibus, 1, 1, 1); 128 129/* 130 * Various supported device vendors/types and their names. 131 */ 132static struct wb_type wb_devs[] = { 133 { WB_VENDORID, WB_DEVICEID_840F, 134 "Winbond W89C840F 10/100BaseTX" }, 135 { CP_VENDORID, CP_DEVICEID_RL100, 136 "Compex RL100-ATX 10/100baseTX" }, 137 { 0, 0, NULL } 138}; 139 140static int wb_probe(device_t); 141static int wb_attach(device_t); 142static int wb_detach(device_t); 143 144static void wb_bfree(void *addr, void *args); 145static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 146 struct mbuf *); 147static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 148 149static void wb_rxeof(struct wb_softc *); 150static void wb_rxeoc(struct wb_softc *); 151static void wb_txeof(struct wb_softc *); 152static void wb_txeoc(struct wb_softc *); 153static void wb_intr(void *); 154static void wb_tick(void *); 155static void wb_start(struct ifnet *); 156static void wb_start_locked(struct ifnet *); 157static int wb_ioctl(struct ifnet *, u_long, caddr_t); 158static void wb_init(void *); 159static void wb_init_locked(struct wb_softc *); 160static void wb_stop(struct wb_softc *); 161static void wb_watchdog(struct wb_softc *); 162static int wb_shutdown(device_t); 163static int wb_ifmedia_upd(struct ifnet *); 164static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 165 166static void wb_eeprom_putbyte(struct wb_softc *, int); 167static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 168static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 169static void wb_mii_sync(struct wb_softc *); 170static void wb_mii_send(struct wb_softc *, u_int32_t, int); 171static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 172static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 173 174static void wb_setcfg(struct wb_softc *, u_int32_t); 175static void wb_setmulti(struct wb_softc *); 176static void wb_reset(struct wb_softc *); 177static void wb_fixmedia(struct wb_softc *); 178static int wb_list_rx_init(struct wb_softc *); 179static int wb_list_tx_init(struct wb_softc *); 180 181static int wb_miibus_readreg(device_t, int, int); 182static int wb_miibus_writereg(device_t, int, int, int); 183static void wb_miibus_statchg(device_t); 184 185#ifdef WB_USEIOSPACE 186#define WB_RES SYS_RES_IOPORT 187#define WB_RID WB_PCI_LOIO 188#else 189#define WB_RES SYS_RES_MEMORY 190#define WB_RID WB_PCI_LOMEM 191#endif 192 193static device_method_t wb_methods[] = { 194 /* Device interface */ 195 DEVMETHOD(device_probe, wb_probe), 196 DEVMETHOD(device_attach, wb_attach), 197 DEVMETHOD(device_detach, wb_detach), 198 DEVMETHOD(device_shutdown, wb_shutdown), 199 200 /* bus interface, for miibus */ 201 DEVMETHOD(bus_print_child, bus_generic_print_child), 202 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 203 204 /* MII interface */ 205 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 206 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 207 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 208 { 0, 0 } 209}; 210 211static driver_t wb_driver = { 212 "wb", 213 wb_methods, 214 sizeof(struct wb_softc) 215}; 216 217static devclass_t wb_devclass; 218 219DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 220DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 221 222#define WB_SETBIT(sc, reg, x) \ 223 CSR_WRITE_4(sc, reg, \ 224 CSR_READ_4(sc, reg) | (x)) 225 226#define WB_CLRBIT(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) & ~(x)) 229 230#define SIO_SET(x) \ 231 CSR_WRITE_4(sc, WB_SIO, \ 232 CSR_READ_4(sc, WB_SIO) | (x)) 233 234#define SIO_CLR(x) \ 235 CSR_WRITE_4(sc, WB_SIO, \ 236 CSR_READ_4(sc, WB_SIO) & ~(x)) 237 238/* 239 * Send a read command and address to the EEPROM, check for ACK. 240 */ 241static void 242wb_eeprom_putbyte(sc, addr) 243 struct wb_softc *sc; 244 int addr; 245{ 246 register int d, i; 247 248 d = addr | WB_EECMD_READ; 249 250 /* 251 * Feed in each bit and stobe the clock. 252 */ 253 for (i = 0x400; i; i >>= 1) { 254 if (d & i) { 255 SIO_SET(WB_SIO_EE_DATAIN); 256 } else { 257 SIO_CLR(WB_SIO_EE_DATAIN); 258 } 259 DELAY(100); 260 SIO_SET(WB_SIO_EE_CLK); 261 DELAY(150); 262 SIO_CLR(WB_SIO_EE_CLK); 263 DELAY(100); 264 } 265 266 return; 267} 268 269/* 270 * Read a word of data stored in the EEPROM at address 'addr.' 271 */ 272static void 273wb_eeprom_getword(sc, addr, dest) 274 struct wb_softc *sc; 275 int addr; 276 u_int16_t *dest; 277{ 278 register int i; 279 u_int16_t word = 0; 280 281 /* Enter EEPROM access mode. */ 282 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 283 284 /* 285 * Send address of word we want to read. 286 */ 287 wb_eeprom_putbyte(sc, addr); 288 289 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 290 291 /* 292 * Start reading bits from EEPROM. 293 */ 294 for (i = 0x8000; i; i >>= 1) { 295 SIO_SET(WB_SIO_EE_CLK); 296 DELAY(100); 297 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 298 word |= i; 299 SIO_CLR(WB_SIO_EE_CLK); 300 DELAY(100); 301 } 302 303 /* Turn off EEPROM access mode. */ 304 CSR_WRITE_4(sc, WB_SIO, 0); 305 306 *dest = word; 307 308 return; 309} 310 311/* 312 * Read a sequence of words from the EEPROM. 313 */ 314static void 315wb_read_eeprom(sc, dest, off, cnt, swap) 316 struct wb_softc *sc; 317 caddr_t dest; 318 int off; 319 int cnt; 320 int swap; 321{ 322 int i; 323 u_int16_t word = 0, *ptr; 324 325 for (i = 0; i < cnt; i++) { 326 wb_eeprom_getword(sc, off + i, &word); 327 ptr = (u_int16_t *)(dest + (i * 2)); 328 if (swap) 329 *ptr = ntohs(word); 330 else 331 *ptr = word; 332 } 333 334 return; 335} 336 337/* 338 * Sync the PHYs by setting data bit and strobing the clock 32 times. 339 */ 340static void 341wb_mii_sync(sc) 342 struct wb_softc *sc; 343{ 344 register int i; 345 346 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 347 348 for (i = 0; i < 32; i++) { 349 SIO_SET(WB_SIO_MII_CLK); 350 DELAY(1); 351 SIO_CLR(WB_SIO_MII_CLK); 352 DELAY(1); 353 } 354 355 return; 356} 357 358/* 359 * Clock a series of bits through the MII. 360 */ 361static void 362wb_mii_send(sc, bits, cnt) 363 struct wb_softc *sc; 364 u_int32_t bits; 365 int cnt; 366{ 367 int i; 368 369 SIO_CLR(WB_SIO_MII_CLK); 370 371 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 372 if (bits & i) { 373 SIO_SET(WB_SIO_MII_DATAIN); 374 } else { 375 SIO_CLR(WB_SIO_MII_DATAIN); 376 } 377 DELAY(1); 378 SIO_CLR(WB_SIO_MII_CLK); 379 DELAY(1); 380 SIO_SET(WB_SIO_MII_CLK); 381 } 382} 383 384/* 385 * Read an PHY register through the MII. 386 */ 387static int 388wb_mii_readreg(sc, frame) 389 struct wb_softc *sc; 390 struct wb_mii_frame *frame; 391 392{ 393 int i, ack; 394 395 /* 396 * Set up frame for RX. 397 */ 398 frame->mii_stdelim = WB_MII_STARTDELIM; 399 frame->mii_opcode = WB_MII_READOP; 400 frame->mii_turnaround = 0; 401 frame->mii_data = 0; 402 403 CSR_WRITE_4(sc, WB_SIO, 0); 404 405 /* 406 * Turn on data xmit. 407 */ 408 SIO_SET(WB_SIO_MII_DIR); 409 410 wb_mii_sync(sc); 411 412 /* 413 * Send command/address info. 414 */ 415 wb_mii_send(sc, frame->mii_stdelim, 2); 416 wb_mii_send(sc, frame->mii_opcode, 2); 417 wb_mii_send(sc, frame->mii_phyaddr, 5); 418 wb_mii_send(sc, frame->mii_regaddr, 5); 419 420 /* Idle bit */ 421 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 422 DELAY(1); 423 SIO_SET(WB_SIO_MII_CLK); 424 DELAY(1); 425 426 /* Turn off xmit. */ 427 SIO_CLR(WB_SIO_MII_DIR); 428 /* Check for ack */ 429 SIO_CLR(WB_SIO_MII_CLK); 430 DELAY(1); 431 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 432 SIO_SET(WB_SIO_MII_CLK); 433 DELAY(1); 434 SIO_CLR(WB_SIO_MII_CLK); 435 DELAY(1); 436 SIO_SET(WB_SIO_MII_CLK); 437 DELAY(1); 438 439 /* 440 * Now try reading data bits. If the ack failed, we still 441 * need to clock through 16 cycles to keep the PHY(s) in sync. 442 */ 443 if (ack) { 444 for(i = 0; i < 16; i++) { 445 SIO_CLR(WB_SIO_MII_CLK); 446 DELAY(1); 447 SIO_SET(WB_SIO_MII_CLK); 448 DELAY(1); 449 } 450 goto fail; 451 } 452 453 for (i = 0x8000; i; i >>= 1) { 454 SIO_CLR(WB_SIO_MII_CLK); 455 DELAY(1); 456 if (!ack) { 457 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 458 frame->mii_data |= i; 459 DELAY(1); 460 } 461 SIO_SET(WB_SIO_MII_CLK); 462 DELAY(1); 463 } 464 465fail: 466 467 SIO_CLR(WB_SIO_MII_CLK); 468 DELAY(1); 469 SIO_SET(WB_SIO_MII_CLK); 470 DELAY(1); 471 472 if (ack) 473 return(1); 474 return(0); 475} 476 477/* 478 * Write to a PHY register through the MII. 479 */ 480static int 481wb_mii_writereg(sc, frame) 482 struct wb_softc *sc; 483 struct wb_mii_frame *frame; 484 485{ 486 487 /* 488 * Set up frame for TX. 489 */ 490 491 frame->mii_stdelim = WB_MII_STARTDELIM; 492 frame->mii_opcode = WB_MII_WRITEOP; 493 frame->mii_turnaround = WB_MII_TURNAROUND; 494 495 /* 496 * Turn on data output. 497 */ 498 SIO_SET(WB_SIO_MII_DIR); 499 500 wb_mii_sync(sc); 501 502 wb_mii_send(sc, frame->mii_stdelim, 2); 503 wb_mii_send(sc, frame->mii_opcode, 2); 504 wb_mii_send(sc, frame->mii_phyaddr, 5); 505 wb_mii_send(sc, frame->mii_regaddr, 5); 506 wb_mii_send(sc, frame->mii_turnaround, 2); 507 wb_mii_send(sc, frame->mii_data, 16); 508 509 /* Idle bit. */ 510 SIO_SET(WB_SIO_MII_CLK); 511 DELAY(1); 512 SIO_CLR(WB_SIO_MII_CLK); 513 DELAY(1); 514 515 /* 516 * Turn off xmit. 517 */ 518 SIO_CLR(WB_SIO_MII_DIR); 519 520 return(0); 521} 522 523static int 524wb_miibus_readreg(dev, phy, reg) 525 device_t dev; 526 int phy, reg; 527{ 528 struct wb_softc *sc; 529 struct wb_mii_frame frame; 530 531 sc = device_get_softc(dev); 532 533 bzero((char *)&frame, sizeof(frame)); 534 535 frame.mii_phyaddr = phy; 536 frame.mii_regaddr = reg; 537 wb_mii_readreg(sc, &frame); 538 539 return(frame.mii_data); 540} 541 542static int 543wb_miibus_writereg(dev, phy, reg, data) 544 device_t dev; 545 int phy, reg, data; 546{ 547 struct wb_softc *sc; 548 struct wb_mii_frame frame; 549 550 sc = device_get_softc(dev); 551 552 bzero((char *)&frame, sizeof(frame)); 553 554 frame.mii_phyaddr = phy; 555 frame.mii_regaddr = reg; 556 frame.mii_data = data; 557 558 wb_mii_writereg(sc, &frame); 559 560 return(0); 561} 562 563static void 564wb_miibus_statchg(dev) 565 device_t dev; 566{ 567 struct wb_softc *sc; 568 struct mii_data *mii; 569 570 sc = device_get_softc(dev); 571 mii = device_get_softc(sc->wb_miibus); 572 wb_setcfg(sc, mii->mii_media_active); 573 574 return; 575} 576 577/* 578 * Program the 64-bit multicast hash filter. 579 */ 580static void 581wb_setmulti(sc) 582 struct wb_softc *sc; 583{ 584 struct ifnet *ifp; 585 int h = 0; 586 u_int32_t hashes[2] = { 0, 0 }; 587 struct ifmultiaddr *ifma; 588 u_int32_t rxfilt; 589 int mcnt = 0; 590 591 ifp = sc->wb_ifp; 592 593 rxfilt = CSR_READ_4(sc, WB_NETCFG); 594 595 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 596 rxfilt |= WB_NETCFG_RX_MULTI; 597 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 598 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 599 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 600 return; 601 } 602 603 /* first, zot all the existing hash bits */ 604 CSR_WRITE_4(sc, WB_MAR0, 0); 605 CSR_WRITE_4(sc, WB_MAR1, 0); 606 607 /* now program new ones */ 608 if_maddr_rlock(ifp); 609 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 610 if (ifma->ifma_addr->sa_family != AF_LINK) 611 continue; 612 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 613 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 614 if (h < 32) 615 hashes[0] |= (1 << h); 616 else 617 hashes[1] |= (1 << (h - 32)); 618 mcnt++; 619 } 620 if_maddr_runlock(ifp); 621 622 if (mcnt) 623 rxfilt |= WB_NETCFG_RX_MULTI; 624 else 625 rxfilt &= ~WB_NETCFG_RX_MULTI; 626 627 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 628 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 629 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 630 631 return; 632} 633 634/* 635 * The Winbond manual states that in order to fiddle with the 636 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 637 * first have to put the transmit and/or receive logic in the idle state. 638 */ 639static void 640wb_setcfg(sc, media) 641 struct wb_softc *sc; 642 u_int32_t media; 643{ 644 int i, restart = 0; 645 646 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 647 restart = 1; 648 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 649 650 for (i = 0; i < WB_TIMEOUT; i++) { 651 DELAY(10); 652 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 653 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 654 break; 655 } 656 657 if (i == WB_TIMEOUT) 658 device_printf(sc->wb_dev, 659 "failed to force tx and rx to idle state\n"); 660 } 661 662 if (IFM_SUBTYPE(media) == IFM_10_T) 663 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 664 else 665 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 666 667 if ((media & IFM_GMASK) == IFM_FDX) 668 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 669 else 670 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 671 672 if (restart) 673 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 674 675 return; 676} 677 678static void 679wb_reset(sc) 680 struct wb_softc *sc; 681{ 682 register int i; 683 struct mii_data *mii; 684 685 CSR_WRITE_4(sc, WB_NETCFG, 0); 686 CSR_WRITE_4(sc, WB_BUSCTL, 0); 687 CSR_WRITE_4(sc, WB_TXADDR, 0); 688 CSR_WRITE_4(sc, WB_RXADDR, 0); 689 690 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 691 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 692 693 for (i = 0; i < WB_TIMEOUT; i++) { 694 DELAY(10); 695 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 696 break; 697 } 698 if (i == WB_TIMEOUT) 699 device_printf(sc->wb_dev, "reset never completed!\n"); 700 701 /* Wait a little while for the chip to get its brains in order. */ 702 DELAY(1000); 703 704 if (sc->wb_miibus == NULL) 705 return; 706 707 mii = device_get_softc(sc->wb_miibus); 708 if (mii == NULL) 709 return; 710 711 if (mii->mii_instance) { 712 struct mii_softc *miisc; 713 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 714 mii_phy_reset(miisc); 715 } 716 717 return; 718} 719 720static void 721wb_fixmedia(sc) 722 struct wb_softc *sc; 723{ 724 struct mii_data *mii = NULL; 725 struct ifnet *ifp; 726 u_int32_t media; 727 728 if (sc->wb_miibus == NULL) 729 return; 730 731 mii = device_get_softc(sc->wb_miibus); 732 ifp = sc->wb_ifp; 733 734 mii_pollstat(mii); 735 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 736 media = mii->mii_media_active & ~IFM_10_T; 737 media |= IFM_100_TX; 738 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 739 media = mii->mii_media_active & ~IFM_100_TX; 740 media |= IFM_10_T; 741 } else 742 return; 743 744 ifmedia_set(&mii->mii_media, media); 745 746 return; 747} 748 749/* 750 * Probe for a Winbond chip. Check the PCI vendor and device 751 * IDs against our list and return a device name if we find a match. 752 */ 753static int 754wb_probe(dev) 755 device_t dev; 756{ 757 struct wb_type *t; 758 759 t = wb_devs; 760 761 while(t->wb_name != NULL) { 762 if ((pci_get_vendor(dev) == t->wb_vid) && 763 (pci_get_device(dev) == t->wb_did)) { 764 device_set_desc(dev, t->wb_name); 765 return (BUS_PROBE_DEFAULT); 766 } 767 t++; 768 } 769 770 return(ENXIO); 771} 772 773/* 774 * Attach the interface. Allocate softc structures, do ifmedia 775 * setup and ethernet/BPF attach. 776 */ 777static int 778wb_attach(dev) 779 device_t dev; 780{ 781 u_char eaddr[ETHER_ADDR_LEN]; 782 struct wb_softc *sc; 783 struct ifnet *ifp; 784 int error = 0, rid; 785 786 sc = device_get_softc(dev); 787 sc->wb_dev = dev; 788 789 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 790 MTX_DEF); 791 callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0); 792 793 /* 794 * Map control/status registers. 795 */ 796 pci_enable_busmaster(dev); 797 798 rid = WB_RID; 799 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 800 801 if (sc->wb_res == NULL) { 802 device_printf(dev, "couldn't map ports/memory\n"); 803 error = ENXIO; 804 goto fail; 805 } 806 807 /* Allocate interrupt */ 808 rid = 0; 809 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 810 RF_SHAREABLE | RF_ACTIVE); 811 812 if (sc->wb_irq == NULL) { 813 device_printf(dev, "couldn't map interrupt\n"); 814 error = ENXIO; 815 goto fail; 816 } 817 818 /* Save the cache line size. */ 819 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 820 821 /* Reset the adapter. */ 822 wb_reset(sc); 823 824 /* 825 * Get station address from the EEPROM. 826 */ 827 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 828 829 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 830 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 831 832 if (sc->wb_ldata == NULL) { 833 device_printf(dev, "no memory for list buffers!\n"); 834 error = ENXIO; 835 goto fail; 836 } 837 838 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 839 840 ifp = sc->wb_ifp = if_alloc(IFT_ETHER); 841 if (ifp == NULL) { 842 device_printf(dev, "can not if_alloc()\n"); 843 error = ENOSPC; 844 goto fail; 845 } 846 ifp->if_softc = sc; 847 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 848 ifp->if_mtu = ETHERMTU; 849 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 850 ifp->if_ioctl = wb_ioctl; 851 ifp->if_start = wb_start; 852 ifp->if_init = wb_init; 853 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 854 855 /* 856 * Do MII setup. 857 */ 858 if (mii_phy_probe(dev, &sc->wb_miibus, 859 wb_ifmedia_upd, wb_ifmedia_sts)) { 860 error = ENXIO; 861 goto fail; 862 } 863 864 /* 865 * Call MI attach routine. 866 */ 867 ether_ifattach(ifp, eaddr); 868 869 /* Hook interrupt last to avoid having to lock softc */ 870 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE, 871 NULL, wb_intr, sc, &sc->wb_intrhand); 872 873 if (error) { 874 device_printf(dev, "couldn't set up irq\n"); 875 ether_ifdetach(ifp); 876 goto fail; 877 } 878 879fail: 880 if (error) 881 wb_detach(dev); 882 883 return(error); 884} 885 886/* 887 * Shutdown hardware and free up resources. This can be called any 888 * time after the mutex has been initialized. It is called in both 889 * the error case in attach and the normal detach case so it needs 890 * to be careful about only freeing resources that have actually been 891 * allocated. 892 */ 893static int 894wb_detach(dev) 895 device_t dev; 896{ 897 struct wb_softc *sc; 898 struct ifnet *ifp; 899 900 sc = device_get_softc(dev); 901 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 902 ifp = sc->wb_ifp; 903 904 /* 905 * Delete any miibus and phy devices attached to this interface. 906 * This should only be done if attach succeeded. 907 */ 908 if (device_is_attached(dev)) { 909 ether_ifdetach(ifp); 910 WB_LOCK(sc); 911 wb_stop(sc); 912 WB_UNLOCK(sc); 913 callout_drain(&sc->wb_stat_callout); 914 } 915 if (sc->wb_miibus) 916 device_delete_child(dev, sc->wb_miibus); 917 bus_generic_detach(dev); 918 919 if (sc->wb_intrhand) 920 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 921 if (sc->wb_irq) 922 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 923 if (sc->wb_res) 924 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 925 926 if (ifp) 927 if_free(ifp); 928 929 if (sc->wb_ldata) { 930 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 931 M_DEVBUF); 932 } 933 934 mtx_destroy(&sc->wb_mtx); 935 936 return(0); 937} 938 939/* 940 * Initialize the transmit descriptors. 941 */ 942static int 943wb_list_tx_init(sc) 944 struct wb_softc *sc; 945{ 946 struct wb_chain_data *cd; 947 struct wb_list_data *ld; 948 int i; 949 950 cd = &sc->wb_cdata; 951 ld = sc->wb_ldata; 952 953 for (i = 0; i < WB_TX_LIST_CNT; i++) { 954 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 955 if (i == (WB_TX_LIST_CNT - 1)) { 956 cd->wb_tx_chain[i].wb_nextdesc = 957 &cd->wb_tx_chain[0]; 958 } else { 959 cd->wb_tx_chain[i].wb_nextdesc = 960 &cd->wb_tx_chain[i + 1]; 961 } 962 } 963 964 cd->wb_tx_free = &cd->wb_tx_chain[0]; 965 cd->wb_tx_tail = cd->wb_tx_head = NULL; 966 967 return(0); 968} 969 970 971/* 972 * Initialize the RX descriptors and allocate mbufs for them. Note that 973 * we arrange the descriptors in a closed ring, so that the last descriptor 974 * points back to the first. 975 */ 976static int 977wb_list_rx_init(sc) 978 struct wb_softc *sc; 979{ 980 struct wb_chain_data *cd; 981 struct wb_list_data *ld; 982 int i; 983 984 cd = &sc->wb_cdata; 985 ld = sc->wb_ldata; 986 987 for (i = 0; i < WB_RX_LIST_CNT; i++) { 988 cd->wb_rx_chain[i].wb_ptr = 989 (struct wb_desc *)&ld->wb_rx_list[i]; 990 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 991 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 992 return(ENOBUFS); 993 if (i == (WB_RX_LIST_CNT - 1)) { 994 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 995 ld->wb_rx_list[i].wb_next = 996 vtophys(&ld->wb_rx_list[0]); 997 } else { 998 cd->wb_rx_chain[i].wb_nextdesc = 999 &cd->wb_rx_chain[i + 1]; 1000 ld->wb_rx_list[i].wb_next = 1001 vtophys(&ld->wb_rx_list[i + 1]); 1002 } 1003 } 1004 1005 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1006 1007 return(0); 1008} 1009 1010static void 1011wb_bfree(buf, args) 1012 void *buf; 1013 void *args; 1014{ 1015 return; 1016} 1017 1018/* 1019 * Initialize an RX descriptor and attach an MBUF cluster. 1020 */ 1021static int 1022wb_newbuf(sc, c, m) 1023 struct wb_softc *sc; 1024 struct wb_chain_onefrag *c; 1025 struct mbuf *m; 1026{ 1027 struct mbuf *m_new = NULL; 1028 1029 if (m == NULL) { 1030 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1031 if (m_new == NULL) 1032 return(ENOBUFS); 1033 m_new->m_data = c->wb_buf; 1034 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1035 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, c->wb_buf, 1036 NULL, 0, EXT_NET_DRV); 1037 } else { 1038 m_new = m; 1039 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1040 m_new->m_data = m_new->m_ext.ext_buf; 1041 } 1042 1043 m_adj(m_new, sizeof(u_int64_t)); 1044 1045 c->wb_mbuf = m_new; 1046 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1047 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1048 c->wb_ptr->wb_status = WB_RXSTAT; 1049 1050 return(0); 1051} 1052 1053/* 1054 * A frame has been uploaded: pass the resulting mbuf chain up to 1055 * the higher level protocols. 1056 */ 1057static void 1058wb_rxeof(sc) 1059 struct wb_softc *sc; 1060{ 1061 struct mbuf *m = NULL; 1062 struct ifnet *ifp; 1063 struct wb_chain_onefrag *cur_rx; 1064 int total_len = 0; 1065 u_int32_t rxstat; 1066 1067 WB_LOCK_ASSERT(sc); 1068 1069 ifp = sc->wb_ifp; 1070 1071 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1072 WB_RXSTAT_OWN)) { 1073 struct mbuf *m0 = NULL; 1074 1075 cur_rx = sc->wb_cdata.wb_rx_head; 1076 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1077 1078 m = cur_rx->wb_mbuf; 1079 1080 if ((rxstat & WB_RXSTAT_MIIERR) || 1081 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1082 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1083 !(rxstat & WB_RXSTAT_LASTFRAG) || 1084 !(rxstat & WB_RXSTAT_RXCMP)) { 1085 ifp->if_ierrors++; 1086 wb_newbuf(sc, cur_rx, m); 1087 device_printf(sc->wb_dev, 1088 "receiver babbling: possible chip bug," 1089 " forcing reset\n"); 1090 wb_fixmedia(sc); 1091 wb_reset(sc); 1092 wb_init_locked(sc); 1093 return; 1094 } 1095 1096 if (rxstat & WB_RXSTAT_RXERR) { 1097 ifp->if_ierrors++; 1098 wb_newbuf(sc, cur_rx, m); 1099 break; 1100 } 1101 1102 /* No errors; receive the packet. */ 1103 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1104 1105 /* 1106 * XXX The Winbond chip includes the CRC with every 1107 * received frame, and there's no way to turn this 1108 * behavior off (at least, I can't find anything in 1109 * the manual that explains how to do it) so we have 1110 * to trim off the CRC manually. 1111 */ 1112 total_len -= ETHER_CRC_LEN; 1113 1114 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1115 NULL); 1116 wb_newbuf(sc, cur_rx, m); 1117 if (m0 == NULL) { 1118 ifp->if_ierrors++; 1119 break; 1120 } 1121 m = m0; 1122 1123 ifp->if_ipackets++; 1124 WB_UNLOCK(sc); 1125 (*ifp->if_input)(ifp, m); 1126 WB_LOCK(sc); 1127 } 1128} 1129 1130static void 1131wb_rxeoc(sc) 1132 struct wb_softc *sc; 1133{ 1134 wb_rxeof(sc); 1135 1136 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1137 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1138 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1139 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1140 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1141 1142 return; 1143} 1144 1145/* 1146 * A frame was downloaded to the chip. It's safe for us to clean up 1147 * the list buffers. 1148 */ 1149static void 1150wb_txeof(sc) 1151 struct wb_softc *sc; 1152{ 1153 struct wb_chain *cur_tx; 1154 struct ifnet *ifp; 1155 1156 ifp = sc->wb_ifp; 1157 1158 /* Clear the timeout timer. */ 1159 sc->wb_timer = 0; 1160 1161 if (sc->wb_cdata.wb_tx_head == NULL) 1162 return; 1163 1164 /* 1165 * Go through our tx list and free mbufs for those 1166 * frames that have been transmitted. 1167 */ 1168 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1169 u_int32_t txstat; 1170 1171 cur_tx = sc->wb_cdata.wb_tx_head; 1172 txstat = WB_TXSTATUS(cur_tx); 1173 1174 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1175 break; 1176 1177 if (txstat & WB_TXSTAT_TXERR) { 1178 ifp->if_oerrors++; 1179 if (txstat & WB_TXSTAT_ABORT) 1180 ifp->if_collisions++; 1181 if (txstat & WB_TXSTAT_LATECOLL) 1182 ifp->if_collisions++; 1183 } 1184 1185 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1186 1187 ifp->if_opackets++; 1188 m_freem(cur_tx->wb_mbuf); 1189 cur_tx->wb_mbuf = NULL; 1190 1191 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1192 sc->wb_cdata.wb_tx_head = NULL; 1193 sc->wb_cdata.wb_tx_tail = NULL; 1194 break; 1195 } 1196 1197 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1198 } 1199 1200 return; 1201} 1202 1203/* 1204 * TX 'end of channel' interrupt handler. 1205 */ 1206static void 1207wb_txeoc(sc) 1208 struct wb_softc *sc; 1209{ 1210 struct ifnet *ifp; 1211 1212 ifp = sc->wb_ifp; 1213 1214 sc->wb_timer = 0; 1215 1216 if (sc->wb_cdata.wb_tx_head == NULL) { 1217 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1218 sc->wb_cdata.wb_tx_tail = NULL; 1219 } else { 1220 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1221 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1222 sc->wb_timer = 5; 1223 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1224 } 1225 } 1226 1227 return; 1228} 1229 1230static void 1231wb_intr(arg) 1232 void *arg; 1233{ 1234 struct wb_softc *sc; 1235 struct ifnet *ifp; 1236 u_int32_t status; 1237 1238 sc = arg; 1239 WB_LOCK(sc); 1240 ifp = sc->wb_ifp; 1241 1242 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1243 WB_UNLOCK(sc); 1244 return; 1245 } 1246 1247 /* Disable interrupts. */ 1248 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1249 1250 for (;;) { 1251 1252 status = CSR_READ_4(sc, WB_ISR); 1253 if (status) 1254 CSR_WRITE_4(sc, WB_ISR, status); 1255 1256 if ((status & WB_INTRS) == 0) 1257 break; 1258 1259 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1260 ifp->if_ierrors++; 1261 wb_reset(sc); 1262 if (status & WB_ISR_RX_ERR) 1263 wb_fixmedia(sc); 1264 wb_init_locked(sc); 1265 continue; 1266 } 1267 1268 if (status & WB_ISR_RX_OK) 1269 wb_rxeof(sc); 1270 1271 if (status & WB_ISR_RX_IDLE) 1272 wb_rxeoc(sc); 1273 1274 if (status & WB_ISR_TX_OK) 1275 wb_txeof(sc); 1276 1277 if (status & WB_ISR_TX_NOBUF) 1278 wb_txeoc(sc); 1279 1280 if (status & WB_ISR_TX_IDLE) { 1281 wb_txeof(sc); 1282 if (sc->wb_cdata.wb_tx_head != NULL) { 1283 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1284 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1285 } 1286 } 1287 1288 if (status & WB_ISR_TX_UNDERRUN) { 1289 ifp->if_oerrors++; 1290 wb_txeof(sc); 1291 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1292 /* Jack up TX threshold */ 1293 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1294 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1295 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1296 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1297 } 1298 1299 if (status & WB_ISR_BUS_ERR) { 1300 wb_reset(sc); 1301 wb_init_locked(sc); 1302 } 1303 1304 } 1305 1306 /* Re-enable interrupts. */ 1307 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1308 1309 if (ifp->if_snd.ifq_head != NULL) { 1310 wb_start_locked(ifp); 1311 } 1312 1313 WB_UNLOCK(sc); 1314 1315 return; 1316} 1317 1318static void 1319wb_tick(xsc) 1320 void *xsc; 1321{ 1322 struct wb_softc *sc; 1323 struct mii_data *mii; 1324 1325 sc = xsc; 1326 WB_LOCK_ASSERT(sc); 1327 mii = device_get_softc(sc->wb_miibus); 1328 1329 mii_tick(mii); 1330 1331 if (sc->wb_timer > 0 && --sc->wb_timer == 0) 1332 wb_watchdog(sc); 1333 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 1334 1335 return; 1336} 1337 1338/* 1339 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1340 * pointers to the fragment pointers. 1341 */ 1342static int 1343wb_encap(sc, c, m_head) 1344 struct wb_softc *sc; 1345 struct wb_chain *c; 1346 struct mbuf *m_head; 1347{ 1348 int frag = 0; 1349 struct wb_desc *f = NULL; 1350 int total_len; 1351 struct mbuf *m; 1352 1353 /* 1354 * Start packing the mbufs in this chain into 1355 * the fragment pointers. Stop when we run out 1356 * of fragments or hit the end of the mbuf chain. 1357 */ 1358 m = m_head; 1359 total_len = 0; 1360 1361 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1362 if (m->m_len != 0) { 1363 if (frag == WB_MAXFRAGS) 1364 break; 1365 total_len += m->m_len; 1366 f = &c->wb_ptr->wb_frag[frag]; 1367 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1368 if (frag == 0) { 1369 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1370 f->wb_status = 0; 1371 } else 1372 f->wb_status = WB_TXSTAT_OWN; 1373 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1374 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1375 frag++; 1376 } 1377 } 1378 1379 /* 1380 * Handle special case: we used up all 16 fragments, 1381 * but we have more mbufs left in the chain. Copy the 1382 * data into an mbuf cluster. Note that we don't 1383 * bother clearing the values in the other fragment 1384 * pointers/counters; it wouldn't gain us anything, 1385 * and would waste cycles. 1386 */ 1387 if (m != NULL) { 1388 struct mbuf *m_new = NULL; 1389 1390 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1391 if (m_new == NULL) 1392 return(1); 1393 if (m_head->m_pkthdr.len > MHLEN) { 1394 MCLGET(m_new, M_DONTWAIT); 1395 if (!(m_new->m_flags & M_EXT)) { 1396 m_freem(m_new); 1397 return(1); 1398 } 1399 } 1400 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1401 mtod(m_new, caddr_t)); 1402 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1403 m_freem(m_head); 1404 m_head = m_new; 1405 f = &c->wb_ptr->wb_frag[0]; 1406 f->wb_status = 0; 1407 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1408 f->wb_ctl = total_len = m_new->m_len; 1409 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1410 frag = 1; 1411 } 1412 1413 if (total_len < WB_MIN_FRAMELEN) { 1414 f = &c->wb_ptr->wb_frag[frag]; 1415 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1416 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1417 f->wb_ctl |= WB_TXCTL_TLINK; 1418 f->wb_status = WB_TXSTAT_OWN; 1419 frag++; 1420 } 1421 1422 c->wb_mbuf = m_head; 1423 c->wb_lastdesc = frag - 1; 1424 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1425 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1426 1427 return(0); 1428} 1429 1430/* 1431 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1432 * to the mbuf data regions directly in the transmit lists. We also save a 1433 * copy of the pointers since the transmit list fragment pointers are 1434 * physical addresses. 1435 */ 1436 1437static void 1438wb_start(ifp) 1439 struct ifnet *ifp; 1440{ 1441 struct wb_softc *sc; 1442 1443 sc = ifp->if_softc; 1444 WB_LOCK(sc); 1445 wb_start_locked(ifp); 1446 WB_UNLOCK(sc); 1447} 1448 1449static void 1450wb_start_locked(ifp) 1451 struct ifnet *ifp; 1452{ 1453 struct wb_softc *sc; 1454 struct mbuf *m_head = NULL; 1455 struct wb_chain *cur_tx = NULL, *start_tx; 1456 1457 sc = ifp->if_softc; 1458 WB_LOCK_ASSERT(sc); 1459 1460 /* 1461 * Check for an available queue slot. If there are none, 1462 * punt. 1463 */ 1464 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1465 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1466 return; 1467 } 1468 1469 start_tx = sc->wb_cdata.wb_tx_free; 1470 1471 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1472 IF_DEQUEUE(&ifp->if_snd, m_head); 1473 if (m_head == NULL) 1474 break; 1475 1476 /* Pick a descriptor off the free list. */ 1477 cur_tx = sc->wb_cdata.wb_tx_free; 1478 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1479 1480 /* Pack the data into the descriptor. */ 1481 wb_encap(sc, cur_tx, m_head); 1482 1483 if (cur_tx != start_tx) 1484 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1485 1486 /* 1487 * If there's a BPF listener, bounce a copy of this frame 1488 * to him. 1489 */ 1490 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1491 } 1492 1493 /* 1494 * If there are no packets queued, bail. 1495 */ 1496 if (cur_tx == NULL) 1497 return; 1498 1499 /* 1500 * Place the request for the upload interrupt 1501 * in the last descriptor in the chain. This way, if 1502 * we're chaining several packets at once, we'll only 1503 * get an interrupt once for the whole chain rather than 1504 * once for each packet. 1505 */ 1506 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1507 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1508 sc->wb_cdata.wb_tx_tail = cur_tx; 1509 1510 if (sc->wb_cdata.wb_tx_head == NULL) { 1511 sc->wb_cdata.wb_tx_head = start_tx; 1512 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1513 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1514 } else { 1515 /* 1516 * We need to distinguish between the case where 1517 * the own bit is clear because the chip cleared it 1518 * and where the own bit is clear because we haven't 1519 * set it yet. The magic value WB_UNSET is just some 1520 * ramdomly chosen number which doesn't have the own 1521 * bit set. When we actually transmit the frame, the 1522 * status word will have _only_ the own bit set, so 1523 * the txeoc handler will be able to tell if it needs 1524 * to initiate another transmission to flush out pending 1525 * frames. 1526 */ 1527 WB_TXOWN(start_tx) = WB_UNSENT; 1528 } 1529 1530 /* 1531 * Set a timeout in case the chip goes out to lunch. 1532 */ 1533 sc->wb_timer = 5; 1534 1535 return; 1536} 1537 1538static void 1539wb_init(xsc) 1540 void *xsc; 1541{ 1542 struct wb_softc *sc = xsc; 1543 1544 WB_LOCK(sc); 1545 wb_init_locked(sc); 1546 WB_UNLOCK(sc); 1547} 1548 1549static void 1550wb_init_locked(sc) 1551 struct wb_softc *sc; 1552{ 1553 struct ifnet *ifp = sc->wb_ifp; 1554 int i; 1555 struct mii_data *mii; 1556 1557 WB_LOCK_ASSERT(sc); 1558 mii = device_get_softc(sc->wb_miibus); 1559 1560 /* 1561 * Cancel pending I/O and free all RX/TX buffers. 1562 */ 1563 wb_stop(sc); 1564 wb_reset(sc); 1565 1566 sc->wb_txthresh = WB_TXTHRESH_INIT; 1567 1568 /* 1569 * Set cache alignment and burst length. 1570 */ 1571#ifdef foo 1572 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1573 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1574 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1575#endif 1576 1577 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1578 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1579 switch(sc->wb_cachesize) { 1580 case 32: 1581 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1582 break; 1583 case 16: 1584 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1585 break; 1586 case 8: 1587 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1588 break; 1589 case 0: 1590 default: 1591 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1592 break; 1593 } 1594 1595 /* This doesn't tend to work too well at 100Mbps. */ 1596 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1597 1598 /* Init our MAC address */ 1599 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1600 CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]); 1601 } 1602 1603 /* Init circular RX list. */ 1604 if (wb_list_rx_init(sc) == ENOBUFS) { 1605 device_printf(sc->wb_dev, 1606 "initialization failed: no memory for rx buffers\n"); 1607 wb_stop(sc); 1608 return; 1609 } 1610 1611 /* Init TX descriptors. */ 1612 wb_list_tx_init(sc); 1613 1614 /* If we want promiscuous mode, set the allframes bit. */ 1615 if (ifp->if_flags & IFF_PROMISC) { 1616 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1617 } else { 1618 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1619 } 1620 1621 /* 1622 * Set capture broadcast bit to capture broadcast frames. 1623 */ 1624 if (ifp->if_flags & IFF_BROADCAST) { 1625 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1626 } else { 1627 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1628 } 1629 1630 /* 1631 * Program the multicast filter, if necessary. 1632 */ 1633 wb_setmulti(sc); 1634 1635 /* 1636 * Load the address of the RX list. 1637 */ 1638 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1639 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1640 1641 /* 1642 * Enable interrupts. 1643 */ 1644 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1645 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1646 1647 /* Enable receiver and transmitter. */ 1648 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1649 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1650 1651 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1652 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1653 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1654 1655 mii_mediachg(mii); 1656 1657 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1658 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1659 1660 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 1661 1662 return; 1663} 1664 1665/* 1666 * Set media options. 1667 */ 1668static int 1669wb_ifmedia_upd(ifp) 1670 struct ifnet *ifp; 1671{ 1672 struct wb_softc *sc; 1673 1674 sc = ifp->if_softc; 1675 1676 WB_LOCK(sc); 1677 if (ifp->if_flags & IFF_UP) 1678 wb_init_locked(sc); 1679 WB_UNLOCK(sc); 1680 1681 return(0); 1682} 1683 1684/* 1685 * Report current media status. 1686 */ 1687static void 1688wb_ifmedia_sts(ifp, ifmr) 1689 struct ifnet *ifp; 1690 struct ifmediareq *ifmr; 1691{ 1692 struct wb_softc *sc; 1693 struct mii_data *mii; 1694 1695 sc = ifp->if_softc; 1696 1697 WB_LOCK(sc); 1698 mii = device_get_softc(sc->wb_miibus); 1699 1700 mii_pollstat(mii); 1701 ifmr->ifm_active = mii->mii_media_active; 1702 ifmr->ifm_status = mii->mii_media_status; 1703 WB_UNLOCK(sc); 1704 1705 return; 1706} 1707 1708static int 1709wb_ioctl(ifp, command, data) 1710 struct ifnet *ifp; 1711 u_long command; 1712 caddr_t data; 1713{ 1714 struct wb_softc *sc = ifp->if_softc; 1715 struct mii_data *mii; 1716 struct ifreq *ifr = (struct ifreq *) data; 1717 int error = 0; 1718 1719 switch(command) { 1720 case SIOCSIFFLAGS: 1721 WB_LOCK(sc); 1722 if (ifp->if_flags & IFF_UP) { 1723 wb_init_locked(sc); 1724 } else { 1725 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1726 wb_stop(sc); 1727 } 1728 WB_UNLOCK(sc); 1729 error = 0; 1730 break; 1731 case SIOCADDMULTI: 1732 case SIOCDELMULTI: 1733 WB_LOCK(sc); 1734 wb_setmulti(sc); 1735 WB_UNLOCK(sc); 1736 error = 0; 1737 break; 1738 case SIOCGIFMEDIA: 1739 case SIOCSIFMEDIA: 1740 mii = device_get_softc(sc->wb_miibus); 1741 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1742 break; 1743 default: 1744 error = ether_ioctl(ifp, command, data); 1745 break; 1746 } 1747 1748 return(error); 1749} 1750 1751static void 1752wb_watchdog(sc) 1753 struct wb_softc *sc; 1754{ 1755 struct ifnet *ifp; 1756 1757 WB_LOCK_ASSERT(sc); 1758 ifp = sc->wb_ifp; 1759 ifp->if_oerrors++; 1760 if_printf(ifp, "watchdog timeout\n"); 1761#ifdef foo 1762 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1763 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 1764#endif 1765 wb_stop(sc); 1766 wb_reset(sc); 1767 wb_init_locked(sc); 1768 1769 if (ifp->if_snd.ifq_head != NULL) 1770 wb_start_locked(ifp); 1771 1772 return; 1773} 1774 1775/* 1776 * Stop the adapter and free any mbufs allocated to the 1777 * RX and TX lists. 1778 */ 1779static void 1780wb_stop(sc) 1781 struct wb_softc *sc; 1782{ 1783 register int i; 1784 struct ifnet *ifp; 1785 1786 WB_LOCK_ASSERT(sc); 1787 ifp = sc->wb_ifp; 1788 sc->wb_timer = 0; 1789 1790 callout_stop(&sc->wb_stat_callout); 1791 1792 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1793 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1794 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1795 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1796 1797 /* 1798 * Free data in the RX lists. 1799 */ 1800 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1801 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1802 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1803 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1804 } 1805 } 1806 bzero((char *)&sc->wb_ldata->wb_rx_list, 1807 sizeof(sc->wb_ldata->wb_rx_list)); 1808 1809 /* 1810 * Free the TX list buffers. 1811 */ 1812 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1813 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1814 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1815 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1816 } 1817 } 1818 1819 bzero((char *)&sc->wb_ldata->wb_tx_list, 1820 sizeof(sc->wb_ldata->wb_tx_list)); 1821 1822 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1823 1824 return; 1825} 1826 1827/* 1828 * Stop all chip I/O so that the kernel's probe routines don't 1829 * get confused by errant DMAs when rebooting. 1830 */ 1831static int 1832wb_shutdown(dev) 1833 device_t dev; 1834{ 1835 struct wb_softc *sc; 1836 1837 sc = device_get_softc(dev); 1838 1839 WB_LOCK(sc); 1840 wb_stop(sc); 1841 WB_UNLOCK(sc); 1842 1843 return (0); 1844} 1845