if_wb.c revision 122678
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 122678 2003-11-14 17:16:58Z obrien $"); 35 36/* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "opt_bdg.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95#include <sys/queue.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102 103#include <net/bpf.h> 104 105#include <vm/vm.h> /* for vtophys */ 106#include <vm/pmap.h> /* for vtophys */ 107#include <machine/bus_memio.h> 108#include <machine/bus_pio.h> 109#include <machine/bus.h> 110#include <machine/resource.h> 111#include <sys/bus.h> 112#include <sys/rman.h> 113 114#include <dev/pci/pcireg.h> 115#include <dev/pci/pcivar.h> 116 117#include <dev/mii/mii.h> 118#include <dev/mii/miivar.h> 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#define WB_USEIOSPACE 124 125#include <pci/if_wbreg.h> 126 127MODULE_DEPEND(wb, pci, 1, 1, 1); 128MODULE_DEPEND(wb, ether, 1, 1, 1); 129MODULE_DEPEND(wb, miibus, 1, 1, 1); 130 131/* 132 * Various supported device vendors/types and their names. 133 */ 134static struct wb_type wb_devs[] = { 135 { WB_VENDORID, WB_DEVICEID_840F, 136 "Winbond W89C840F 10/100BaseTX" }, 137 { CP_VENDORID, CP_DEVICEID_RL100, 138 "Compex RL100-ATX 10/100baseTX" }, 139 { 0, 0, NULL } 140}; 141 142static int wb_probe (device_t); 143static int wb_attach (device_t); 144static int wb_detach (device_t); 145 146static void wb_bfree (void *addr, void *args); 147static int wb_newbuf (struct wb_softc *, 148 struct wb_chain_onefrag *, 149 struct mbuf *); 150static int wb_encap (struct wb_softc *, struct wb_chain *, 151 struct mbuf *); 152 153static void wb_rxeof (struct wb_softc *); 154static void wb_rxeoc (struct wb_softc *); 155static void wb_txeof (struct wb_softc *); 156static void wb_txeoc (struct wb_softc *); 157static void wb_intr (void *); 158static void wb_tick (void *); 159static void wb_start (struct ifnet *); 160static int wb_ioctl (struct ifnet *, u_long, caddr_t); 161static void wb_init (void *); 162static void wb_stop (struct wb_softc *); 163static void wb_watchdog (struct ifnet *); 164static void wb_shutdown (device_t); 165static int wb_ifmedia_upd (struct ifnet *); 166static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 167 168static void wb_eeprom_putbyte (struct wb_softc *, int); 169static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 170static void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 171static void wb_mii_sync (struct wb_softc *); 172static void wb_mii_send (struct wb_softc *, u_int32_t, int); 173static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 174static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 175 176static void wb_setcfg (struct wb_softc *, u_int32_t); 177static u_int32_t wb_mchash (caddr_t); 178static void wb_setmulti (struct wb_softc *); 179static void wb_reset (struct wb_softc *); 180static void wb_fixmedia (struct wb_softc *); 181static int wb_list_rx_init (struct wb_softc *); 182static int wb_list_tx_init (struct wb_softc *); 183 184static int wb_miibus_readreg (device_t, int, int); 185static int wb_miibus_writereg (device_t, int, int, int); 186static void wb_miibus_statchg (device_t); 187 188#ifdef WB_USEIOSPACE 189#define WB_RES SYS_RES_IOPORT 190#define WB_RID WB_PCI_LOIO 191#else 192#define WB_RES SYS_RES_MEMORY 193#define WB_RID WB_PCI_LOMEM 194#endif 195 196static device_method_t wb_methods[] = { 197 /* Device interface */ 198 DEVMETHOD(device_probe, wb_probe), 199 DEVMETHOD(device_attach, wb_attach), 200 DEVMETHOD(device_detach, wb_detach), 201 DEVMETHOD(device_shutdown, wb_shutdown), 202 203 /* bus interface, for miibus */ 204 DEVMETHOD(bus_print_child, bus_generic_print_child), 205 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 206 207 /* MII interface */ 208 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 209 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 210 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 211 { 0, 0 } 212}; 213 214static driver_t wb_driver = { 215 "wb", 216 wb_methods, 217 sizeof(struct wb_softc) 218}; 219 220static devclass_t wb_devclass; 221 222DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 223DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 224 225#define WB_SETBIT(sc, reg, x) \ 226 CSR_WRITE_4(sc, reg, \ 227 CSR_READ_4(sc, reg) | (x)) 228 229#define WB_CLRBIT(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, \ 231 CSR_READ_4(sc, reg) & ~(x)) 232 233#define SIO_SET(x) \ 234 CSR_WRITE_4(sc, WB_SIO, \ 235 CSR_READ_4(sc, WB_SIO) | (x)) 236 237#define SIO_CLR(x) \ 238 CSR_WRITE_4(sc, WB_SIO, \ 239 CSR_READ_4(sc, WB_SIO) & ~(x)) 240 241/* 242 * Send a read command and address to the EEPROM, check for ACK. 243 */ 244static void 245wb_eeprom_putbyte(sc, addr) 246 struct wb_softc *sc; 247 int addr; 248{ 249 register int d, i; 250 251 d = addr | WB_EECMD_READ; 252 253 /* 254 * Feed in each bit and stobe the clock. 255 */ 256 for (i = 0x400; i; i >>= 1) { 257 if (d & i) { 258 SIO_SET(WB_SIO_EE_DATAIN); 259 } else { 260 SIO_CLR(WB_SIO_EE_DATAIN); 261 } 262 DELAY(100); 263 SIO_SET(WB_SIO_EE_CLK); 264 DELAY(150); 265 SIO_CLR(WB_SIO_EE_CLK); 266 DELAY(100); 267 } 268 269 return; 270} 271 272/* 273 * Read a word of data stored in the EEPROM at address 'addr.' 274 */ 275static void 276wb_eeprom_getword(sc, addr, dest) 277 struct wb_softc *sc; 278 int addr; 279 u_int16_t *dest; 280{ 281 register int i; 282 u_int16_t word = 0; 283 284 /* Enter EEPROM access mode. */ 285 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 286 287 /* 288 * Send address of word we want to read. 289 */ 290 wb_eeprom_putbyte(sc, addr); 291 292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 293 294 /* 295 * Start reading bits from EEPROM. 296 */ 297 for (i = 0x8000; i; i >>= 1) { 298 SIO_SET(WB_SIO_EE_CLK); 299 DELAY(100); 300 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 301 word |= i; 302 SIO_CLR(WB_SIO_EE_CLK); 303 DELAY(100); 304 } 305 306 /* Turn off EEPROM access mode. */ 307 CSR_WRITE_4(sc, WB_SIO, 0); 308 309 *dest = word; 310 311 return; 312} 313 314/* 315 * Read a sequence of words from the EEPROM. 316 */ 317static void 318wb_read_eeprom(sc, dest, off, cnt, swap) 319 struct wb_softc *sc; 320 caddr_t dest; 321 int off; 322 int cnt; 323 int swap; 324{ 325 int i; 326 u_int16_t word = 0, *ptr; 327 328 for (i = 0; i < cnt; i++) { 329 wb_eeprom_getword(sc, off + i, &word); 330 ptr = (u_int16_t *)(dest + (i * 2)); 331 if (swap) 332 *ptr = ntohs(word); 333 else 334 *ptr = word; 335 } 336 337 return; 338} 339 340/* 341 * Sync the PHYs by setting data bit and strobing the clock 32 times. 342 */ 343static void 344wb_mii_sync(sc) 345 struct wb_softc *sc; 346{ 347 register int i; 348 349 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 350 351 for (i = 0; i < 32; i++) { 352 SIO_SET(WB_SIO_MII_CLK); 353 DELAY(1); 354 SIO_CLR(WB_SIO_MII_CLK); 355 DELAY(1); 356 } 357 358 return; 359} 360 361/* 362 * Clock a series of bits through the MII. 363 */ 364static void 365wb_mii_send(sc, bits, cnt) 366 struct wb_softc *sc; 367 u_int32_t bits; 368 int cnt; 369{ 370 int i; 371 372 SIO_CLR(WB_SIO_MII_CLK); 373 374 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 375 if (bits & i) { 376 SIO_SET(WB_SIO_MII_DATAIN); 377 } else { 378 SIO_CLR(WB_SIO_MII_DATAIN); 379 } 380 DELAY(1); 381 SIO_CLR(WB_SIO_MII_CLK); 382 DELAY(1); 383 SIO_SET(WB_SIO_MII_CLK); 384 } 385} 386 387/* 388 * Read an PHY register through the MII. 389 */ 390static int 391wb_mii_readreg(sc, frame) 392 struct wb_softc *sc; 393 struct wb_mii_frame *frame; 394 395{ 396 int i, ack; 397 398 WB_LOCK(sc); 399 400 /* 401 * Set up frame for RX. 402 */ 403 frame->mii_stdelim = WB_MII_STARTDELIM; 404 frame->mii_opcode = WB_MII_READOP; 405 frame->mii_turnaround = 0; 406 frame->mii_data = 0; 407 408 CSR_WRITE_4(sc, WB_SIO, 0); 409 410 /* 411 * Turn on data xmit. 412 */ 413 SIO_SET(WB_SIO_MII_DIR); 414 415 wb_mii_sync(sc); 416 417 /* 418 * Send command/address info. 419 */ 420 wb_mii_send(sc, frame->mii_stdelim, 2); 421 wb_mii_send(sc, frame->mii_opcode, 2); 422 wb_mii_send(sc, frame->mii_phyaddr, 5); 423 wb_mii_send(sc, frame->mii_regaddr, 5); 424 425 /* Idle bit */ 426 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 427 DELAY(1); 428 SIO_SET(WB_SIO_MII_CLK); 429 DELAY(1); 430 431 /* Turn off xmit. */ 432 SIO_CLR(WB_SIO_MII_DIR); 433 /* Check for ack */ 434 SIO_CLR(WB_SIO_MII_CLK); 435 DELAY(1); 436 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 437 SIO_SET(WB_SIO_MII_CLK); 438 DELAY(1); 439 SIO_CLR(WB_SIO_MII_CLK); 440 DELAY(1); 441 SIO_SET(WB_SIO_MII_CLK); 442 DELAY(1); 443 444 /* 445 * Now try reading data bits. If the ack failed, we still 446 * need to clock through 16 cycles to keep the PHY(s) in sync. 447 */ 448 if (ack) { 449 for(i = 0; i < 16; i++) { 450 SIO_CLR(WB_SIO_MII_CLK); 451 DELAY(1); 452 SIO_SET(WB_SIO_MII_CLK); 453 DELAY(1); 454 } 455 goto fail; 456 } 457 458 for (i = 0x8000; i; i >>= 1) { 459 SIO_CLR(WB_SIO_MII_CLK); 460 DELAY(1); 461 if (!ack) { 462 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 463 frame->mii_data |= i; 464 DELAY(1); 465 } 466 SIO_SET(WB_SIO_MII_CLK); 467 DELAY(1); 468 } 469 470fail: 471 472 SIO_CLR(WB_SIO_MII_CLK); 473 DELAY(1); 474 SIO_SET(WB_SIO_MII_CLK); 475 DELAY(1); 476 477 WB_UNLOCK(sc); 478 479 if (ack) 480 return(1); 481 return(0); 482} 483 484/* 485 * Write to a PHY register through the MII. 486 */ 487static int 488wb_mii_writereg(sc, frame) 489 struct wb_softc *sc; 490 struct wb_mii_frame *frame; 491 492{ 493 WB_LOCK(sc); 494 495 /* 496 * Set up frame for TX. 497 */ 498 499 frame->mii_stdelim = WB_MII_STARTDELIM; 500 frame->mii_opcode = WB_MII_WRITEOP; 501 frame->mii_turnaround = WB_MII_TURNAROUND; 502 503 /* 504 * Turn on data output. 505 */ 506 SIO_SET(WB_SIO_MII_DIR); 507 508 wb_mii_sync(sc); 509 510 wb_mii_send(sc, frame->mii_stdelim, 2); 511 wb_mii_send(sc, frame->mii_opcode, 2); 512 wb_mii_send(sc, frame->mii_phyaddr, 5); 513 wb_mii_send(sc, frame->mii_regaddr, 5); 514 wb_mii_send(sc, frame->mii_turnaround, 2); 515 wb_mii_send(sc, frame->mii_data, 16); 516 517 /* Idle bit. */ 518 SIO_SET(WB_SIO_MII_CLK); 519 DELAY(1); 520 SIO_CLR(WB_SIO_MII_CLK); 521 DELAY(1); 522 523 /* 524 * Turn off xmit. 525 */ 526 SIO_CLR(WB_SIO_MII_DIR); 527 528 WB_UNLOCK(sc); 529 530 return(0); 531} 532 533static int 534wb_miibus_readreg(dev, phy, reg) 535 device_t dev; 536 int phy, reg; 537{ 538 struct wb_softc *sc; 539 struct wb_mii_frame frame; 540 541 sc = device_get_softc(dev); 542 543 bzero((char *)&frame, sizeof(frame)); 544 545 frame.mii_phyaddr = phy; 546 frame.mii_regaddr = reg; 547 wb_mii_readreg(sc, &frame); 548 549 return(frame.mii_data); 550} 551 552static int 553wb_miibus_writereg(dev, phy, reg, data) 554 device_t dev; 555 int phy, reg, data; 556{ 557 struct wb_softc *sc; 558 struct wb_mii_frame frame; 559 560 sc = device_get_softc(dev); 561 562 bzero((char *)&frame, sizeof(frame)); 563 564 frame.mii_phyaddr = phy; 565 frame.mii_regaddr = reg; 566 frame.mii_data = data; 567 568 wb_mii_writereg(sc, &frame); 569 570 return(0); 571} 572 573static void 574wb_miibus_statchg(dev) 575 device_t dev; 576{ 577 struct wb_softc *sc; 578 struct mii_data *mii; 579 580 sc = device_get_softc(dev); 581 WB_LOCK(sc); 582 mii = device_get_softc(sc->wb_miibus); 583 wb_setcfg(sc, mii->mii_media_active); 584 WB_UNLOCK(sc); 585 586 return; 587} 588 589static u_int32_t 590wb_mchash(addr) 591 caddr_t addr; 592{ 593 u_int32_t crc, carry; 594 int idx, bit; 595 u_int8_t data; 596 597 /* Compute CRC for the address value. */ 598 crc = 0xFFFFFFFF; /* initial value */ 599 600 for (idx = 0; idx < 6; idx++) { 601 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 602 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 603 crc <<= 1; 604 if (carry) 605 crc = (crc ^ 0x04c11db6) | carry; 606 } 607 } 608 609 /* 610 * return the filter bit position 611 * Note: I arrived at the following nonsense 612 * through experimentation. It's not the usual way to 613 * generate the bit position but it's the only thing 614 * I could come up with that works. 615 */ 616 return(~(crc >> 26) & 0x0000003F); 617} 618 619/* 620 * Program the 64-bit multicast hash filter. 621 */ 622static void 623wb_setmulti(sc) 624 struct wb_softc *sc; 625{ 626 struct ifnet *ifp; 627 int h = 0; 628 u_int32_t hashes[2] = { 0, 0 }; 629 struct ifmultiaddr *ifma; 630 u_int32_t rxfilt; 631 int mcnt = 0; 632 633 ifp = &sc->arpcom.ac_if; 634 635 rxfilt = CSR_READ_4(sc, WB_NETCFG); 636 637 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 638 rxfilt |= WB_NETCFG_RX_MULTI; 639 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 640 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 641 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 642 return; 643 } 644 645 /* first, zot all the existing hash bits */ 646 CSR_WRITE_4(sc, WB_MAR0, 0); 647 CSR_WRITE_4(sc, WB_MAR1, 0); 648 649 /* now program new ones */ 650 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 651 if (ifma->ifma_addr->sa_family != AF_LINK) 652 continue; 653 h = wb_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 654 if (h < 32) 655 hashes[0] |= (1 << h); 656 else 657 hashes[1] |= (1 << (h - 32)); 658 mcnt++; 659 } 660 661 if (mcnt) 662 rxfilt |= WB_NETCFG_RX_MULTI; 663 else 664 rxfilt &= ~WB_NETCFG_RX_MULTI; 665 666 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 667 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 668 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 669 670 return; 671} 672 673/* 674 * The Winbond manual states that in order to fiddle with the 675 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 676 * first have to put the transmit and/or receive logic in the idle state. 677 */ 678static void 679wb_setcfg(sc, media) 680 struct wb_softc *sc; 681 u_int32_t media; 682{ 683 int i, restart = 0; 684 685 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 686 restart = 1; 687 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 688 689 for (i = 0; i < WB_TIMEOUT; i++) { 690 DELAY(10); 691 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 692 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 693 break; 694 } 695 696 if (i == WB_TIMEOUT) 697 printf("wb%d: failed to force tx and " 698 "rx to idle state\n", sc->wb_unit); 699 } 700 701 if (IFM_SUBTYPE(media) == IFM_10_T) 702 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 703 else 704 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 705 706 if ((media & IFM_GMASK) == IFM_FDX) 707 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 708 else 709 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 710 711 if (restart) 712 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 713 714 return; 715} 716 717static void 718wb_reset(sc) 719 struct wb_softc *sc; 720{ 721 register int i; 722 struct mii_data *mii; 723 724 CSR_WRITE_4(sc, WB_NETCFG, 0); 725 CSR_WRITE_4(sc, WB_BUSCTL, 0); 726 CSR_WRITE_4(sc, WB_TXADDR, 0); 727 CSR_WRITE_4(sc, WB_RXADDR, 0); 728 729 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 730 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 731 732 for (i = 0; i < WB_TIMEOUT; i++) { 733 DELAY(10); 734 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 735 break; 736 } 737 if (i == WB_TIMEOUT) 738 printf("wb%d: reset never completed!\n", sc->wb_unit); 739 740 /* Wait a little while for the chip to get its brains in order. */ 741 DELAY(1000); 742 743 if (sc->wb_miibus == NULL) 744 return; 745 746 mii = device_get_softc(sc->wb_miibus); 747 if (mii == NULL) 748 return; 749 750 if (mii->mii_instance) { 751 struct mii_softc *miisc; 752 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 753 mii_phy_reset(miisc); 754 } 755 756 return; 757} 758 759static void 760wb_fixmedia(sc) 761 struct wb_softc *sc; 762{ 763 struct mii_data *mii = NULL; 764 struct ifnet *ifp; 765 u_int32_t media; 766 767 if (sc->wb_miibus == NULL) 768 return; 769 770 mii = device_get_softc(sc->wb_miibus); 771 ifp = &sc->arpcom.ac_if; 772 773 mii_pollstat(mii); 774 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 775 media = mii->mii_media_active & ~IFM_10_T; 776 media |= IFM_100_TX; 777 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 778 media = mii->mii_media_active & ~IFM_100_TX; 779 media |= IFM_10_T; 780 } else 781 return; 782 783 ifmedia_set(&mii->mii_media, media); 784 785 return; 786} 787 788/* 789 * Probe for a Winbond chip. Check the PCI vendor and device 790 * IDs against our list and return a device name if we find a match. 791 */ 792static int 793wb_probe(dev) 794 device_t dev; 795{ 796 struct wb_type *t; 797 798 t = wb_devs; 799 800 while(t->wb_name != NULL) { 801 if ((pci_get_vendor(dev) == t->wb_vid) && 802 (pci_get_device(dev) == t->wb_did)) { 803 device_set_desc(dev, t->wb_name); 804 return(0); 805 } 806 t++; 807 } 808 809 return(ENXIO); 810} 811 812/* 813 * Attach the interface. Allocate softc structures, do ifmedia 814 * setup and ethernet/BPF attach. 815 */ 816static int 817wb_attach(dev) 818 device_t dev; 819{ 820 u_char eaddr[ETHER_ADDR_LEN]; 821 struct wb_softc *sc; 822 struct ifnet *ifp; 823 int unit, error = 0, rid; 824 825 sc = device_get_softc(dev); 826 unit = device_get_unit(dev); 827 828 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 829 MTX_DEF | MTX_RECURSE); 830#ifndef BURN_BRIDGES 831 /* 832 * Handle power management nonsense. 833 */ 834 835 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 836 u_int32_t iobase, membase, irq; 837 838 /* Save important PCI config data. */ 839 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 840 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 841 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 842 843 /* Reset the power state. */ 844 printf("wb%d: chip is in D%d power mode " 845 "-- setting to D0\n", unit, 846 pci_get_powerstate(dev)); 847 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 848 849 /* Restore PCI config data. */ 850 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 851 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 852 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 853 } 854#endif 855 /* 856 * Map control/status registers. 857 */ 858 pci_enable_busmaster(dev); 859 860 rid = WB_RID; 861 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 862 0, ~0, 1, RF_ACTIVE); 863 864 if (sc->wb_res == NULL) { 865 printf("wb%d: couldn't map ports/memory\n", unit); 866 error = ENXIO; 867 goto fail; 868 } 869 870 sc->wb_btag = rman_get_bustag(sc->wb_res); 871 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 872 873 /* Allocate interrupt */ 874 rid = 0; 875 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 876 RF_SHAREABLE | RF_ACTIVE); 877 878 if (sc->wb_irq == NULL) { 879 printf("wb%d: couldn't map interrupt\n", unit); 880 error = ENXIO; 881 goto fail; 882 } 883 884 /* Save the cache line size. */ 885 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 886 887 /* Reset the adapter. */ 888 wb_reset(sc); 889 890 /* 891 * Get station address from the EEPROM. 892 */ 893 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 894 895 /* 896 * A Winbond chip was detected. Inform the world. 897 */ 898 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 899 900 sc->wb_unit = unit; 901 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 902 903 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 904 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 905 906 if (sc->wb_ldata == NULL) { 907 printf("wb%d: no memory for list buffers!\n", unit); 908 error = ENXIO; 909 goto fail; 910 } 911 912 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 913 914 ifp = &sc->arpcom.ac_if; 915 ifp->if_softc = sc; 916 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 917 ifp->if_mtu = ETHERMTU; 918 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 919 ifp->if_ioctl = wb_ioctl; 920 ifp->if_output = ether_output; 921 ifp->if_start = wb_start; 922 ifp->if_watchdog = wb_watchdog; 923 ifp->if_init = wb_init; 924 ifp->if_baudrate = 10000000; 925 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 926 927 /* 928 * Do MII setup. 929 */ 930 if (mii_phy_probe(dev, &sc->wb_miibus, 931 wb_ifmedia_upd, wb_ifmedia_sts)) { 932 error = ENXIO; 933 goto fail; 934 } 935 936 /* 937 * Call MI attach routine. 938 */ 939 ether_ifattach(ifp, eaddr); 940 941 /* Hook interrupt last to avoid having to lock softc */ 942 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 943 wb_intr, sc, &sc->wb_intrhand); 944 945 if (error) { 946 printf("wb%d: couldn't set up irq\n", unit); 947 ether_ifdetach(ifp); 948 goto fail; 949 } 950 951fail: 952 if (error) 953 wb_detach(dev); 954 955 return(error); 956} 957 958/* 959 * Shutdown hardware and free up resources. This can be called any 960 * time after the mutex has been initialized. It is called in both 961 * the error case in attach and the normal detach case so it needs 962 * to be careful about only freeing resources that have actually been 963 * allocated. 964 */ 965static int 966wb_detach(dev) 967 device_t dev; 968{ 969 struct wb_softc *sc; 970 struct ifnet *ifp; 971 972 sc = device_get_softc(dev); 973 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 974 WB_LOCK(sc); 975 ifp = &sc->arpcom.ac_if; 976 977 /* 978 * Delete any miibus and phy devices attached to this interface. 979 * This should only be done if attach succeeded. 980 */ 981 if (device_is_attached(dev)) { 982 wb_stop(sc); 983 ether_ifdetach(ifp); 984 } 985 if (sc->wb_miibus) 986 device_delete_child(dev, sc->wb_miibus); 987 bus_generic_detach(dev); 988 989 if (sc->wb_intrhand) 990 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 991 if (sc->wb_irq) 992 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 993 if (sc->wb_res) 994 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 995 996 if (sc->wb_ldata) { 997 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 998 M_DEVBUF); 999 } 1000 1001 WB_UNLOCK(sc); 1002 mtx_destroy(&sc->wb_mtx); 1003 1004 return(0); 1005} 1006 1007/* 1008 * Initialize the transmit descriptors. 1009 */ 1010static int 1011wb_list_tx_init(sc) 1012 struct wb_softc *sc; 1013{ 1014 struct wb_chain_data *cd; 1015 struct wb_list_data *ld; 1016 int i; 1017 1018 cd = &sc->wb_cdata; 1019 ld = sc->wb_ldata; 1020 1021 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1022 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1023 if (i == (WB_TX_LIST_CNT - 1)) { 1024 cd->wb_tx_chain[i].wb_nextdesc = 1025 &cd->wb_tx_chain[0]; 1026 } else { 1027 cd->wb_tx_chain[i].wb_nextdesc = 1028 &cd->wb_tx_chain[i + 1]; 1029 } 1030 } 1031 1032 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1033 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1034 1035 return(0); 1036} 1037 1038 1039/* 1040 * Initialize the RX descriptors and allocate mbufs for them. Note that 1041 * we arrange the descriptors in a closed ring, so that the last descriptor 1042 * points back to the first. 1043 */ 1044static int 1045wb_list_rx_init(sc) 1046 struct wb_softc *sc; 1047{ 1048 struct wb_chain_data *cd; 1049 struct wb_list_data *ld; 1050 int i; 1051 1052 cd = &sc->wb_cdata; 1053 ld = sc->wb_ldata; 1054 1055 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1056 cd->wb_rx_chain[i].wb_ptr = 1057 (struct wb_desc *)&ld->wb_rx_list[i]; 1058 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1059 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1060 return(ENOBUFS); 1061 if (i == (WB_RX_LIST_CNT - 1)) { 1062 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1063 ld->wb_rx_list[i].wb_next = 1064 vtophys(&ld->wb_rx_list[0]); 1065 } else { 1066 cd->wb_rx_chain[i].wb_nextdesc = 1067 &cd->wb_rx_chain[i + 1]; 1068 ld->wb_rx_list[i].wb_next = 1069 vtophys(&ld->wb_rx_list[i + 1]); 1070 } 1071 } 1072 1073 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1074 1075 return(0); 1076} 1077 1078static void 1079wb_bfree(buf, args) 1080 void *buf; 1081 void *args; 1082{ 1083 return; 1084} 1085 1086/* 1087 * Initialize an RX descriptor and attach an MBUF cluster. 1088 */ 1089static int 1090wb_newbuf(sc, c, m) 1091 struct wb_softc *sc; 1092 struct wb_chain_onefrag *c; 1093 struct mbuf *m; 1094{ 1095 struct mbuf *m_new = NULL; 1096 1097 if (m == NULL) { 1098 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1099 if (m_new == NULL) 1100 return(ENOBUFS); 1101 m_new->m_data = c->wb_buf; 1102 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1103 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1104 EXT_NET_DRV); 1105 } else { 1106 m_new = m; 1107 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1108 m_new->m_data = m_new->m_ext.ext_buf; 1109 } 1110 1111 m_adj(m_new, sizeof(u_int64_t)); 1112 1113 c->wb_mbuf = m_new; 1114 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1115 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1116 c->wb_ptr->wb_status = WB_RXSTAT; 1117 1118 return(0); 1119} 1120 1121/* 1122 * A frame has been uploaded: pass the resulting mbuf chain up to 1123 * the higher level protocols. 1124 */ 1125static void 1126wb_rxeof(sc) 1127 struct wb_softc *sc; 1128{ 1129 struct mbuf *m = NULL; 1130 struct ifnet *ifp; 1131 struct wb_chain_onefrag *cur_rx; 1132 int total_len = 0; 1133 u_int32_t rxstat; 1134 1135 ifp = &sc->arpcom.ac_if; 1136 1137 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1138 WB_RXSTAT_OWN)) { 1139 struct mbuf *m0 = NULL; 1140 1141 cur_rx = sc->wb_cdata.wb_rx_head; 1142 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1143 1144 m = cur_rx->wb_mbuf; 1145 1146 if ((rxstat & WB_RXSTAT_MIIERR) || 1147 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1148 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1149 !(rxstat & WB_RXSTAT_LASTFRAG) || 1150 !(rxstat & WB_RXSTAT_RXCMP)) { 1151 ifp->if_ierrors++; 1152 wb_newbuf(sc, cur_rx, m); 1153 printf("wb%x: receiver babbling: possible chip " 1154 "bug, forcing reset\n", sc->wb_unit); 1155 wb_fixmedia(sc); 1156 wb_reset(sc); 1157 wb_init(sc); 1158 return; 1159 } 1160 1161 if (rxstat & WB_RXSTAT_RXERR) { 1162 ifp->if_ierrors++; 1163 wb_newbuf(sc, cur_rx, m); 1164 break; 1165 } 1166 1167 /* No errors; receive the packet. */ 1168 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1169 1170 /* 1171 * XXX The Winbond chip includes the CRC with every 1172 * received frame, and there's no way to turn this 1173 * behavior off (at least, I can't find anything in 1174 * the manual that explains how to do it) so we have 1175 * to trim off the CRC manually. 1176 */ 1177 total_len -= ETHER_CRC_LEN; 1178 1179 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1180 NULL); 1181 wb_newbuf(sc, cur_rx, m); 1182 if (m0 == NULL) { 1183 ifp->if_ierrors++; 1184 break; 1185 } 1186 m = m0; 1187 1188 ifp->if_ipackets++; 1189 (*ifp->if_input)(ifp, m); 1190 } 1191} 1192 1193static void 1194wb_rxeoc(sc) 1195 struct wb_softc *sc; 1196{ 1197 wb_rxeof(sc); 1198 1199 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1200 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1201 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1202 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1203 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1204 1205 return; 1206} 1207 1208/* 1209 * A frame was downloaded to the chip. It's safe for us to clean up 1210 * the list buffers. 1211 */ 1212static void 1213wb_txeof(sc) 1214 struct wb_softc *sc; 1215{ 1216 struct wb_chain *cur_tx; 1217 struct ifnet *ifp; 1218 1219 ifp = &sc->arpcom.ac_if; 1220 1221 /* Clear the timeout timer. */ 1222 ifp->if_timer = 0; 1223 1224 if (sc->wb_cdata.wb_tx_head == NULL) 1225 return; 1226 1227 /* 1228 * Go through our tx list and free mbufs for those 1229 * frames that have been transmitted. 1230 */ 1231 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1232 u_int32_t txstat; 1233 1234 cur_tx = sc->wb_cdata.wb_tx_head; 1235 txstat = WB_TXSTATUS(cur_tx); 1236 1237 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1238 break; 1239 1240 if (txstat & WB_TXSTAT_TXERR) { 1241 ifp->if_oerrors++; 1242 if (txstat & WB_TXSTAT_ABORT) 1243 ifp->if_collisions++; 1244 if (txstat & WB_TXSTAT_LATECOLL) 1245 ifp->if_collisions++; 1246 } 1247 1248 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1249 1250 ifp->if_opackets++; 1251 m_freem(cur_tx->wb_mbuf); 1252 cur_tx->wb_mbuf = NULL; 1253 1254 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1255 sc->wb_cdata.wb_tx_head = NULL; 1256 sc->wb_cdata.wb_tx_tail = NULL; 1257 break; 1258 } 1259 1260 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1261 } 1262 1263 return; 1264} 1265 1266/* 1267 * TX 'end of channel' interrupt handler. 1268 */ 1269static void 1270wb_txeoc(sc) 1271 struct wb_softc *sc; 1272{ 1273 struct ifnet *ifp; 1274 1275 ifp = &sc->arpcom.ac_if; 1276 1277 ifp->if_timer = 0; 1278 1279 if (sc->wb_cdata.wb_tx_head == NULL) { 1280 ifp->if_flags &= ~IFF_OACTIVE; 1281 sc->wb_cdata.wb_tx_tail = NULL; 1282 } else { 1283 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1284 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1285 ifp->if_timer = 5; 1286 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1287 } 1288 } 1289 1290 return; 1291} 1292 1293static void 1294wb_intr(arg) 1295 void *arg; 1296{ 1297 struct wb_softc *sc; 1298 struct ifnet *ifp; 1299 u_int32_t status; 1300 1301 sc = arg; 1302 WB_LOCK(sc); 1303 ifp = &sc->arpcom.ac_if; 1304 1305 if (!(ifp->if_flags & IFF_UP)) { 1306 WB_UNLOCK(sc); 1307 return; 1308 } 1309 1310 /* Disable interrupts. */ 1311 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1312 1313 for (;;) { 1314 1315 status = CSR_READ_4(sc, WB_ISR); 1316 if (status) 1317 CSR_WRITE_4(sc, WB_ISR, status); 1318 1319 if ((status & WB_INTRS) == 0) 1320 break; 1321 1322 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1323 ifp->if_ierrors++; 1324 wb_reset(sc); 1325 if (status & WB_ISR_RX_ERR) 1326 wb_fixmedia(sc); 1327 wb_init(sc); 1328 continue; 1329 } 1330 1331 if (status & WB_ISR_RX_OK) 1332 wb_rxeof(sc); 1333 1334 if (status & WB_ISR_RX_IDLE) 1335 wb_rxeoc(sc); 1336 1337 if (status & WB_ISR_TX_OK) 1338 wb_txeof(sc); 1339 1340 if (status & WB_ISR_TX_NOBUF) 1341 wb_txeoc(sc); 1342 1343 if (status & WB_ISR_TX_IDLE) { 1344 wb_txeof(sc); 1345 if (sc->wb_cdata.wb_tx_head != NULL) { 1346 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1347 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1348 } 1349 } 1350 1351 if (status & WB_ISR_TX_UNDERRUN) { 1352 ifp->if_oerrors++; 1353 wb_txeof(sc); 1354 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1355 /* Jack up TX threshold */ 1356 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1357 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1358 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1359 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1360 } 1361 1362 if (status & WB_ISR_BUS_ERR) { 1363 wb_reset(sc); 1364 wb_init(sc); 1365 } 1366 1367 } 1368 1369 /* Re-enable interrupts. */ 1370 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1371 1372 if (ifp->if_snd.ifq_head != NULL) { 1373 wb_start(ifp); 1374 } 1375 1376 WB_UNLOCK(sc); 1377 1378 return; 1379} 1380 1381static void 1382wb_tick(xsc) 1383 void *xsc; 1384{ 1385 struct wb_softc *sc; 1386 struct mii_data *mii; 1387 1388 sc = xsc; 1389 WB_LOCK(sc); 1390 mii = device_get_softc(sc->wb_miibus); 1391 1392 mii_tick(mii); 1393 1394 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1395 1396 WB_UNLOCK(sc); 1397 1398 return; 1399} 1400 1401/* 1402 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1403 * pointers to the fragment pointers. 1404 */ 1405static int 1406wb_encap(sc, c, m_head) 1407 struct wb_softc *sc; 1408 struct wb_chain *c; 1409 struct mbuf *m_head; 1410{ 1411 int frag = 0; 1412 struct wb_desc *f = NULL; 1413 int total_len; 1414 struct mbuf *m; 1415 1416 /* 1417 * Start packing the mbufs in this chain into 1418 * the fragment pointers. Stop when we run out 1419 * of fragments or hit the end of the mbuf chain. 1420 */ 1421 m = m_head; 1422 total_len = 0; 1423 1424 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1425 if (m->m_len != 0) { 1426 if (frag == WB_MAXFRAGS) 1427 break; 1428 total_len += m->m_len; 1429 f = &c->wb_ptr->wb_frag[frag]; 1430 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1431 if (frag == 0) { 1432 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1433 f->wb_status = 0; 1434 } else 1435 f->wb_status = WB_TXSTAT_OWN; 1436 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1437 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1438 frag++; 1439 } 1440 } 1441 1442 /* 1443 * Handle special case: we used up all 16 fragments, 1444 * but we have more mbufs left in the chain. Copy the 1445 * data into an mbuf cluster. Note that we don't 1446 * bother clearing the values in the other fragment 1447 * pointers/counters; it wouldn't gain us anything, 1448 * and would waste cycles. 1449 */ 1450 if (m != NULL) { 1451 struct mbuf *m_new = NULL; 1452 1453 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1454 if (m_new == NULL) 1455 return(1); 1456 if (m_head->m_pkthdr.len > MHLEN) { 1457 MCLGET(m_new, M_DONTWAIT); 1458 if (!(m_new->m_flags & M_EXT)) { 1459 m_freem(m_new); 1460 return(1); 1461 } 1462 } 1463 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1464 mtod(m_new, caddr_t)); 1465 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1466 m_freem(m_head); 1467 m_head = m_new; 1468 f = &c->wb_ptr->wb_frag[0]; 1469 f->wb_status = 0; 1470 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1471 f->wb_ctl = total_len = m_new->m_len; 1472 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1473 frag = 1; 1474 } 1475 1476 if (total_len < WB_MIN_FRAMELEN) { 1477 f = &c->wb_ptr->wb_frag[frag]; 1478 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1479 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1480 f->wb_ctl |= WB_TXCTL_TLINK; 1481 f->wb_status = WB_TXSTAT_OWN; 1482 frag++; 1483 } 1484 1485 c->wb_mbuf = m_head; 1486 c->wb_lastdesc = frag - 1; 1487 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1488 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1489 1490 return(0); 1491} 1492 1493/* 1494 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1495 * to the mbuf data regions directly in the transmit lists. We also save a 1496 * copy of the pointers since the transmit list fragment pointers are 1497 * physical addresses. 1498 */ 1499 1500static void 1501wb_start(ifp) 1502 struct ifnet *ifp; 1503{ 1504 struct wb_softc *sc; 1505 struct mbuf *m_head = NULL; 1506 struct wb_chain *cur_tx = NULL, *start_tx; 1507 1508 sc = ifp->if_softc; 1509 WB_LOCK(sc); 1510 1511 /* 1512 * Check for an available queue slot. If there are none, 1513 * punt. 1514 */ 1515 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1516 ifp->if_flags |= IFF_OACTIVE; 1517 WB_UNLOCK(sc); 1518 return; 1519 } 1520 1521 start_tx = sc->wb_cdata.wb_tx_free; 1522 1523 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1524 IF_DEQUEUE(&ifp->if_snd, m_head); 1525 if (m_head == NULL) 1526 break; 1527 1528 /* Pick a descriptor off the free list. */ 1529 cur_tx = sc->wb_cdata.wb_tx_free; 1530 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1531 1532 /* Pack the data into the descriptor. */ 1533 wb_encap(sc, cur_tx, m_head); 1534 1535 if (cur_tx != start_tx) 1536 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1537 1538 /* 1539 * If there's a BPF listener, bounce a copy of this frame 1540 * to him. 1541 */ 1542 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1543 } 1544 1545 /* 1546 * If there are no packets queued, bail. 1547 */ 1548 if (cur_tx == NULL) { 1549 WB_UNLOCK(sc); 1550 return; 1551 } 1552 1553 /* 1554 * Place the request for the upload interrupt 1555 * in the last descriptor in the chain. This way, if 1556 * we're chaining several packets at once, we'll only 1557 * get an interupt once for the whole chain rather than 1558 * once for each packet. 1559 */ 1560 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1561 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1562 sc->wb_cdata.wb_tx_tail = cur_tx; 1563 1564 if (sc->wb_cdata.wb_tx_head == NULL) { 1565 sc->wb_cdata.wb_tx_head = start_tx; 1566 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1567 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1568 } else { 1569 /* 1570 * We need to distinguish between the case where 1571 * the own bit is clear because the chip cleared it 1572 * and where the own bit is clear because we haven't 1573 * set it yet. The magic value WB_UNSET is just some 1574 * ramdomly chosen number which doesn't have the own 1575 * bit set. When we actually transmit the frame, the 1576 * status word will have _only_ the own bit set, so 1577 * the txeoc handler will be able to tell if it needs 1578 * to initiate another transmission to flush out pending 1579 * frames. 1580 */ 1581 WB_TXOWN(start_tx) = WB_UNSENT; 1582 } 1583 1584 /* 1585 * Set a timeout in case the chip goes out to lunch. 1586 */ 1587 ifp->if_timer = 5; 1588 WB_UNLOCK(sc); 1589 1590 return; 1591} 1592 1593static void 1594wb_init(xsc) 1595 void *xsc; 1596{ 1597 struct wb_softc *sc = xsc; 1598 struct ifnet *ifp = &sc->arpcom.ac_if; 1599 int i; 1600 struct mii_data *mii; 1601 1602 WB_LOCK(sc); 1603 mii = device_get_softc(sc->wb_miibus); 1604 1605 /* 1606 * Cancel pending I/O and free all RX/TX buffers. 1607 */ 1608 wb_stop(sc); 1609 wb_reset(sc); 1610 1611 sc->wb_txthresh = WB_TXTHRESH_INIT; 1612 1613 /* 1614 * Set cache alignment and burst length. 1615 */ 1616#ifdef foo 1617 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1618 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1619 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1620#endif 1621 1622 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1623 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1624 switch(sc->wb_cachesize) { 1625 case 32: 1626 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1627 break; 1628 case 16: 1629 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1630 break; 1631 case 8: 1632 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1633 break; 1634 case 0: 1635 default: 1636 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1637 break; 1638 } 1639 1640 /* This doesn't tend to work too well at 100Mbps. */ 1641 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1642 1643 /* Init our MAC address */ 1644 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1645 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1646 } 1647 1648 /* Init circular RX list. */ 1649 if (wb_list_rx_init(sc) == ENOBUFS) { 1650 printf("wb%d: initialization failed: no " 1651 "memory for rx buffers\n", sc->wb_unit); 1652 wb_stop(sc); 1653 WB_UNLOCK(sc); 1654 return; 1655 } 1656 1657 /* Init TX descriptors. */ 1658 wb_list_tx_init(sc); 1659 1660 /* If we want promiscuous mode, set the allframes bit. */ 1661 if (ifp->if_flags & IFF_PROMISC) { 1662 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1663 } else { 1664 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1665 } 1666 1667 /* 1668 * Set capture broadcast bit to capture broadcast frames. 1669 */ 1670 if (ifp->if_flags & IFF_BROADCAST) { 1671 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1672 } else { 1673 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1674 } 1675 1676 /* 1677 * Program the multicast filter, if necessary. 1678 */ 1679 wb_setmulti(sc); 1680 1681 /* 1682 * Load the address of the RX list. 1683 */ 1684 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1685 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1686 1687 /* 1688 * Enable interrupts. 1689 */ 1690 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1691 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1692 1693 /* Enable receiver and transmitter. */ 1694 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1695 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1696 1697 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1698 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1699 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1700 1701 mii_mediachg(mii); 1702 1703 ifp->if_flags |= IFF_RUNNING; 1704 ifp->if_flags &= ~IFF_OACTIVE; 1705 1706 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1707 WB_UNLOCK(sc); 1708 1709 return; 1710} 1711 1712/* 1713 * Set media options. 1714 */ 1715static int 1716wb_ifmedia_upd(ifp) 1717 struct ifnet *ifp; 1718{ 1719 struct wb_softc *sc; 1720 1721 sc = ifp->if_softc; 1722 1723 if (ifp->if_flags & IFF_UP) 1724 wb_init(sc); 1725 1726 return(0); 1727} 1728 1729/* 1730 * Report current media status. 1731 */ 1732static void 1733wb_ifmedia_sts(ifp, ifmr) 1734 struct ifnet *ifp; 1735 struct ifmediareq *ifmr; 1736{ 1737 struct wb_softc *sc; 1738 struct mii_data *mii; 1739 1740 sc = ifp->if_softc; 1741 1742 mii = device_get_softc(sc->wb_miibus); 1743 1744 mii_pollstat(mii); 1745 ifmr->ifm_active = mii->mii_media_active; 1746 ifmr->ifm_status = mii->mii_media_status; 1747 1748 return; 1749} 1750 1751static int 1752wb_ioctl(ifp, command, data) 1753 struct ifnet *ifp; 1754 u_long command; 1755 caddr_t data; 1756{ 1757 struct wb_softc *sc = ifp->if_softc; 1758 struct mii_data *mii; 1759 struct ifreq *ifr = (struct ifreq *) data; 1760 int error = 0; 1761 1762 WB_LOCK(sc); 1763 1764 switch(command) { 1765 case SIOCSIFFLAGS: 1766 if (ifp->if_flags & IFF_UP) { 1767 wb_init(sc); 1768 } else { 1769 if (ifp->if_flags & IFF_RUNNING) 1770 wb_stop(sc); 1771 } 1772 error = 0; 1773 break; 1774 case SIOCADDMULTI: 1775 case SIOCDELMULTI: 1776 wb_setmulti(sc); 1777 error = 0; 1778 break; 1779 case SIOCGIFMEDIA: 1780 case SIOCSIFMEDIA: 1781 mii = device_get_softc(sc->wb_miibus); 1782 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1783 break; 1784 default: 1785 error = ether_ioctl(ifp, command, data); 1786 break; 1787 } 1788 1789 WB_UNLOCK(sc); 1790 1791 return(error); 1792} 1793 1794static void 1795wb_watchdog(ifp) 1796 struct ifnet *ifp; 1797{ 1798 struct wb_softc *sc; 1799 1800 sc = ifp->if_softc; 1801 1802 WB_LOCK(sc); 1803 ifp->if_oerrors++; 1804 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1805#ifdef foo 1806 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1807 printf("wb%d: no carrier - transceiver cable problem?\n", 1808 sc->wb_unit); 1809#endif 1810 wb_stop(sc); 1811 wb_reset(sc); 1812 wb_init(sc); 1813 1814 if (ifp->if_snd.ifq_head != NULL) 1815 wb_start(ifp); 1816 WB_UNLOCK(sc); 1817 1818 return; 1819} 1820 1821/* 1822 * Stop the adapter and free any mbufs allocated to the 1823 * RX and TX lists. 1824 */ 1825static void 1826wb_stop(sc) 1827 struct wb_softc *sc; 1828{ 1829 register int i; 1830 struct ifnet *ifp; 1831 1832 WB_LOCK(sc); 1833 ifp = &sc->arpcom.ac_if; 1834 ifp->if_timer = 0; 1835 1836 untimeout(wb_tick, sc, sc->wb_stat_ch); 1837 1838 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1839 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1840 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1841 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1842 1843 /* 1844 * Free data in the RX lists. 1845 */ 1846 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1847 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1848 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1849 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1850 } 1851 } 1852 bzero((char *)&sc->wb_ldata->wb_rx_list, 1853 sizeof(sc->wb_ldata->wb_rx_list)); 1854 1855 /* 1856 * Free the TX list buffers. 1857 */ 1858 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1859 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1860 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1861 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1862 } 1863 } 1864 1865 bzero((char *)&sc->wb_ldata->wb_tx_list, 1866 sizeof(sc->wb_ldata->wb_tx_list)); 1867 1868 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1869 WB_UNLOCK(sc); 1870 1871 return; 1872} 1873 1874/* 1875 * Stop all chip I/O so that the kernel's probe routines don't 1876 * get confused by errant DMAs when rebooting. 1877 */ 1878static void 1879wb_shutdown(dev) 1880 device_t dev; 1881{ 1882 struct wb_softc *sc; 1883 1884 sc = device_get_softc(dev); 1885 wb_stop(sc); 1886 1887 return; 1888} 1889