1/*- 2 * Copyright(c) 2002-2011 Exar Corp. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification are permitted provided the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Exar Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31/*$FreeBSD: releng/11.0/sys/dev/vxge/vxgehal/vxgehal-fifo.h 221167 2011-04-28 14:33:15Z gnn $*/ 32 33#ifndef VXGE_HAL_FIFO_H 34#define VXGE_HAL_FIFO_H 35 36__EXTERN_BEGIN_DECLS 37 38/* 39 * struct __hal_fifo_t - Fifo. 40 * @channel: Channel "base" of this fifo, the common part of all HAL 41 * channels. 42 * @mempool: Memory pool, from which descriptors get allocated. 43 * @config: Fifo configuration, part of device configuration 44 * (see vxge_hal_device_config_t {}). 45 * @interrupt_type: Interrupt type to be used 46 * @no_snoop_bits: See vxge_hal_fifo_config_t {}. 47 * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size 48 * bytes. Setting @memblock_size to page size ensures 49 * by-page allocation of descriptors. 128K bytes is the 50 * maximum supported block size. 51 * @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock. 52 * on TxDL please refer to X3100 UG. 53 * @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus 54 * per-TxDL HAL private space (__hal_fifo_txdl_priv_t). 55 * @txdl_priv_size: Per-TxDL space reserved for HAL and ULD 56 * @per_txdl_space: Per txdl private space for the ULD 57 * @txdlblock_priv_size: Total private space per TXDL memory block 58 * @align_size: Cache alignment size 59 * @callback: Fifo completion callback. HAL invokes the callback when there 60 * are new completions on that fifo. In many implementations 61 * the @callback executes in the hw interrupt context. 62 * @txdl_init: Fifo's descriptor-initialize callback. 63 * See vxge_hal_fifo_txdl_init_f {}. 64 * If not NULL, HAL invokes the callback when opening 65 * the fifo via vxge_hal_vpath_open(). 66 * @txdl_term: Fifo's descriptor-terminate callback. If not NULL, 67 * HAL invokes the callback when closing the corresponding fifo. 68 * See also vxge_hal_fifo_txdl_term_f {}. 69 * @stats: Statistics of this fifo 70 * 71 * Fifo channel. 72 * Note: The structure is cache line aligned. 73 */ 74typedef struct __hal_fifo_t { 75 __hal_channel_t channel; 76 vxge_hal_mempool_t *mempool; 77 vxge_hal_fifo_config_t *config; 78 u64 interrupt_type; 79 u32 no_snoop_bits; 80 u32 memblock_size; 81 u32 txdl_per_memblock; 82 u32 txdl_size; 83 u32 txdl_priv_size; 84 u32 per_txdl_space; 85 u32 txdlblock_priv_size; 86 u32 align_size; 87 vxge_hal_fifo_callback_f callback; 88 vxge_hal_fifo_txdl_init_f txdl_init; 89 vxge_hal_fifo_txdl_term_f txdl_term; 90 vxge_hal_vpath_stats_sw_fifo_info_t *stats; 91} __vxge_os_attr_cacheline_aligned __hal_fifo_t; 92 93/* 94 * struct __hal_fifo_txdl_priv_t - Transmit descriptor HAL-private data. 95 * @dma_addr: DMA (mapped) address of _this_ descriptor. 96 * @dma_handle: DMA handle used to map the descriptor onto device. 97 * @dma_offset: Descriptor's offset in the memory block. HAL allocates 98 * descriptors in memory blocks (see vxge_hal_fifo_config_t {}) 99 * Each memblock is a contiguous block of DMA-able memory. 100 * @frags: Total number of fragments (that is, contiguous data buffers) 101 * carried by this TxDL. 102 * @align_vaddr_start: Aligned virtual address start 103 * @align_vaddr: Virtual address of the per-TxDL area in memory used for 104 * alignement. Used to place one or more mis-aligned fragments 105 * (the maximum defined by configration variable 106 * @max_aligned_frags). 107 * @align_dma_addr: DMA address translated from the @align_vaddr. 108 * @align_dma_handle: DMA handle that corresponds to @align_dma_addr. 109 * @align_dma_acch: DMA access handle corresponds to @align_dma_addr. 110 * @align_dma_offset: The current offset into the @align_vaddr area. 111 * Grows while filling the descriptor, gets reset. 112 * @align_used_frags: Number of fragments used. 113 * @alloc_frags: Total number of fragments allocated. 114 * @dang_frags: Number of fragments kept from release until this TxDL is freed. 115 * @bytes_sent: 116 * @unused: 117 * @dang_txdl: 118 * @next_txdl_priv: 119 * @first_txdp: 120 * @dang_txdlh: Pointer to TxDL (list) kept from release until this TxDL 121 * is freed. 122 * @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous 123 * TxDL list. 124 * @txdlh: Corresponding txdlh to this TxDL. 125 * @memblock: Pointer to the TxDL memory block or memory page. 126 * on the next send operation. 127 * @dma_object: DMA address and handle of the memory block that contains 128 * the descriptor. This member is used only in the "checked" 129 * version of the HAL (to enforce certain assertions); 130 * otherwise it gets compiled out. 131 * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage. 132 * 133 * Per-transmit decsriptor HAL-private data. HAL uses the space to keep DMA 134 * information associated with the descriptor. Note that ULD can ask HAL 135 * to allocate additional per-descriptor space for its own (ULD-specific) 136 * purposes. 137 * 138 * See also: vxge_hal_ring_rxd_priv_t {}. 139 */ 140typedef struct __hal_fifo_txdl_priv_t { 141 dma_addr_t dma_addr; 142 pci_dma_h dma_handle; 143 ptrdiff_t dma_offset; 144 u32 frags; 145 u8 *align_vaddr_start; 146 u8 *align_vaddr; 147 dma_addr_t align_dma_addr; 148 pci_dma_h align_dma_handle; 149 pci_dma_acc_h align_dma_acch; 150 ptrdiff_t align_dma_offset; 151 u32 align_used_frags; 152 u32 alloc_frags; 153 u32 dang_frags; 154 u32 bytes_sent; 155 u32 unused; 156 vxge_hal_fifo_txd_t *dang_txdl; 157 struct __hal_fifo_txdl_priv_t *next_txdl_priv; 158 vxge_hal_fifo_txd_t *first_txdp; 159 void *memblock; 160#if defined(VXGE_DEBUG_ASSERT) 161 vxge_hal_mempool_dma_t *dma_object; 162#endif 163#if defined(VXGE_OS_MEMORY_CHECK) 164 u32 allocated; 165#endif 166} __hal_fifo_txdl_priv_t; 167 168#define VXGE_HAL_FIFO_ULD_PRIV(fifo, txdh) \ 169 fifo->channel.dtr_arr[ \ 170 ((vxge_hal_fifo_txd_t *)(txdh))->host_control].uld_priv 171 172#define VXGE_HAL_FIFO_HAL_PRIV(fifo, txdh) \ 173 ((__hal_fifo_txdl_priv_t *)(fifo->channel.dtr_arr[ \ 174 ((vxge_hal_fifo_txd_t *)(txdh))->host_control].hal_priv)) 175 176#define VXGE_HAL_FIFO_MAX_FRAG_CNT(fifo) fifo->config->max_frags 177 178#define VXGE_HAL_FIFO_TXDL_INDEX(txdp) \ 179 (u32)((vxge_hal_fifo_txd_t *)txdp)->host_control 180 181/* ========================= FIFO PRIVATE API ============================= */ 182 183vxge_hal_status_e 184__hal_fifo_create( 185 vxge_hal_vpath_h vpath_handle, 186 vxge_hal_fifo_attr_t *attr); 187 188void 189__hal_fifo_abort( 190 vxge_hal_fifo_h fifoh, 191 vxge_hal_reopen_e reopen); 192 193vxge_hal_status_e 194__hal_fifo_reset( 195 vxge_hal_fifo_h ringh); 196 197void 198__hal_fifo_delete( 199 vxge_hal_vpath_h vpath_handle); 200 201void 202__hal_fifo_txdl_free_many( 203 __hal_fifo_t *fifo, 204 vxge_hal_fifo_txd_t *txdp, 205 u32 list_size, 206 u32 frags); 207 208#if defined(VXGE_HAL_ALIGN_XMIT) 209void 210__hal_fifo_txdl_align_free_unmap( 211 __hal_fifo_t *fifo, 212 vxge_hal_fifo_txd_t *txdp); 213 214vxge_hal_status_e 215__hal_fifo_txdl_align_alloc_map( 216 __hal_fifo_t *fifo, 217 vxge_hal_fifo_txd_t *txdp); 218 219#endif 220 221__EXTERN_END_DECLS 222 223#endif /* VXGE_HAL_FIFO_H */ 224