at91dci.c revision 190183
1239310Sdim#include <sys/cdefs.h> 2239310Sdim__FBSDID("$FreeBSD: head/sys/dev/usb/controller/at91dci.c 190183 2009-03-20 21:57:54Z thompsa $"); 3239310Sdim 4239310Sdim/*- 5239310Sdim * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. 6239310Sdim * 7239310Sdim * Redistribution and use in source and binary forms, with or without 8239310Sdim * modification, are permitted provided that the following conditions 9239310Sdim * are met: 10239310Sdim * 1. Redistributions of source code must retain the above copyright 11239310Sdim * notice, this list of conditions and the following disclaimer. 12239310Sdim * 2. Redistributions in binary form must reproduce the above copyright 13239310Sdim * notice, this list of conditions and the following disclaimer in the 14239310Sdim * documentation and/or other materials provided with the distribution. 15239310Sdim * 16239310Sdim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17239310Sdim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18239310Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19276479Sdim * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20276479Sdim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21276479Sdim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22296417Sdim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23296417Sdim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24239310Sdim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25276479Sdim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26239310Sdim * SUCH DAMAGE. 27239310Sdim */ 28276479Sdim 29276479Sdim/* 30276479Sdim * This file contains the driver for the AT91 series USB Device 31239310Sdim * Controller 32239310Sdim */ 33251662Sdim 34239310Sdim/* 35239310Sdim * Thanks to "David Brownell" for helping out regarding the hardware 36239310Sdim * endpoint profiles. 37276479Sdim */ 38276479Sdim 39296417Sdim/* 40296417Sdim * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is 41296417Sdim * reset ! 42296417Sdim * 43251662Sdim * NOTE: When the chip detects BUS-reset it will also reset the 44296417Sdim * endpoints, Function-address and more. 45296417Sdim */ 46251662Sdim 47296417Sdim#include <dev/usb/usb.h> 48296417Sdim#include <dev/usb/usb_mfunc.h> 49296417Sdim#include <dev/usb/usb_error.h> 50296417Sdim 51296417Sdim#define USB_DEBUG_VAR at91dcidebug 52296417Sdim 53296417Sdim#include <dev/usb/usb_core.h> 54296417Sdim#include <dev/usb/usb_debug.h> 55296417Sdim#include <dev/usb/usb_busdma.h> 56251662Sdim#include <dev/usb/usb_process.h> 57288943Sdim#include <dev/usb/usb_sw_transfer.h> 58251662Sdim#include <dev/usb/usb_transfer.h> 59251662Sdim#include <dev/usb/usb_device.h> 60251662Sdim#include <dev/usb/usb_hub.h> 61251662Sdim#include <dev/usb/usb_util.h> 62239310Sdim 63239310Sdim#include <dev/usb/usb_controller.h> 64239310Sdim#include <dev/usb/usb_bus.h> 65239310Sdim#include <dev/usb/controller/at91dci.h> 66251662Sdim 67251662Sdim#define AT9100_DCI_BUS2SC(bus) \ 68251662Sdim ((struct at91dci_softc *)(((uint8_t *)(bus)) - \ 69239310Sdim ((uint8_t *)&(((struct at91dci_softc *)0)->sc_bus)))) 70276479Sdim 71239310Sdim#define AT9100_DCI_PC2SC(pc) \ 72296417Sdim AT9100_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 73296417Sdim 74239310Sdim#if USB_DEBUG 75296417Sdimstatic int at91dcidebug = 0; 76239310Sdim 77239310SdimSYSCTL_NODE(_hw_usb2, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci"); 78239310SdimSYSCTL_INT(_hw_usb2_at91dci, OID_AUTO, debug, CTLFLAG_RW, 79239310Sdim &at91dcidebug, 0, "at91dci debug level"); 80276479Sdim#endif 81239310Sdim 82239310Sdim#define AT9100_DCI_INTR_ENDPT 1 83276479Sdim 84239310Sdim/* prototypes */ 85239310Sdim 86296417Sdimstruct usb2_bus_methods at91dci_bus_methods; 87296417Sdimstruct usb2_pipe_methods at91dci_device_bulk_methods; 88296417Sdimstruct usb2_pipe_methods at91dci_device_ctrl_methods; 89239310Sdimstruct usb2_pipe_methods at91dci_device_intr_methods; 90296417Sdimstruct usb2_pipe_methods at91dci_device_isoc_fs_methods; 91296417Sdimstruct usb2_pipe_methods at91dci_root_ctrl_methods; 92239310Sdimstruct usb2_pipe_methods at91dci_root_intr_methods; 93296417Sdim 94296417Sdimstatic at91dci_cmd_t at91dci_setup_rx; 95296417Sdimstatic at91dci_cmd_t at91dci_data_rx; 96296417Sdimstatic at91dci_cmd_t at91dci_data_tx; 97296417Sdimstatic at91dci_cmd_t at91dci_data_tx_sync; 98296417Sdimstatic void at91dci_device_done(struct usb2_xfer *, usb2_error_t); 99296417Sdimstatic void at91dci_do_poll(struct usb2_bus *); 100296417Sdimstatic void at91dci_root_ctrl_poll(struct at91dci_softc *); 101239310Sdimstatic void at91dci_standard_done(struct usb2_xfer *); 102239310Sdim 103296417Sdimstatic usb2_sw_transfer_func_t at91dci_root_intr_done; 104296417Sdimstatic usb2_sw_transfer_func_t at91dci_root_ctrl_done; 105296417Sdim 106296417Sdim/* 107296417Sdim * NOTE: Some of the bits in the CSR register have inverse meaning so 108296417Sdim * we need a helper macro when acknowledging events: 109296417Sdim */ 110239310Sdim#define AT91_CSR_ACK(csr, what) do { \ 111296417Sdim (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \ 112296417Sdim AT91_UDP_CSR_TXPKTRDY| \ 113296417Sdim AT91_UDP_CSR_RXBYTECNT) ^ (what));\ 114296417Sdim (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \ 115296417Sdim AT91_UDP_CSR_RX_DATA_BK1| \ 116296417Sdim AT91_UDP_CSR_TXCOMP| \ 117296417Sdim AT91_UDP_CSR_RXSETUP| \ 118296417Sdim AT91_UDP_CSR_STALLSENT) ^ (what)); \ 119296417Sdim} while (0) 120296417Sdim 121296417Sdim/* 122296417Sdim * Here is a list of what the chip supports. 123239310Sdim * Probably it supports more than listed here! 124251662Sdim */ 125296417Sdimstatic const struct usb2_hw_ep_profile 126296417Sdim at91dci_ep_profile[AT91_UDP_EP_MAX] = { 127296417Sdim 128296417Sdim [0] = { 129296417Sdim .max_in_frame_size = 8, 130296417Sdim .max_out_frame_size = 8, 131296417Sdim .is_simplex = 1, 132251662Sdim .support_control = 1, 133296417Sdim }, 134296417Sdim [1] = { 135296417Sdim .max_in_frame_size = 64, 136296417Sdim .max_out_frame_size = 64, 137296417Sdim .is_simplex = 1, 138296417Sdim .support_multi_buffer = 1, 139296417Sdim .support_bulk = 1, 140296417Sdim .support_interrupt = 1, 141296417Sdim .support_isochronous = 1, 142296417Sdim .support_in = 1, 143296417Sdim .support_out = 1, 144296417Sdim }, 145296417Sdim [2] = { 146296417Sdim .max_in_frame_size = 64, 147239310Sdim .max_out_frame_size = 64, 148296417Sdim .is_simplex = 1, 149296417Sdim .support_multi_buffer = 1, 150296417Sdim .support_bulk = 1, 151296417Sdim .support_interrupt = 1, 152296417Sdim .support_isochronous = 1, 153296417Sdim .support_in = 1, 154239310Sdim .support_out = 1, 155296417Sdim }, 156296417Sdim [3] = { 157296417Sdim /* can also do BULK */ 158296417Sdim .max_in_frame_size = 8, 159239310Sdim .max_out_frame_size = 8, 160296417Sdim .is_simplex = 1, 161296417Sdim .support_interrupt = 1, 162296417Sdim .support_in = 1, 163296417Sdim .support_out = 1, 164296417Sdim }, 165296417Sdim [4] = { 166296417Sdim .max_in_frame_size = 256, 167296417Sdim .max_out_frame_size = 256, 168239310Sdim .is_simplex = 1, 169239310Sdim .support_multi_buffer = 1, 170296417Sdim .support_bulk = 1, 171296417Sdim .support_interrupt = 1, 172296417Sdim .support_isochronous = 1, 173239310Sdim .support_in = 1, 174296417Sdim .support_out = 1, 175296417Sdim }, 176296417Sdim [5] = { 177296417Sdim .max_in_frame_size = 256, 178296417Sdim .max_out_frame_size = 256, 179239310Sdim .is_simplex = 1, 180296417Sdim .support_multi_buffer = 1, 181296417Sdim .support_bulk = 1, 182251662Sdim .support_interrupt = 1, 183239310Sdim .support_isochronous = 1, 184296417Sdim .support_in = 1, 185239310Sdim .support_out = 1, 186239310Sdim }, 187239310Sdim}; 188239310Sdim 189239310Sdimstatic void 190239310Sdimat91dci_get_hw_ep_profile(struct usb2_device *udev, 191239310Sdim const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 192239310Sdim{ 193239310Sdim if (ep_addr < AT91_UDP_EP_MAX) { 194239310Sdim *ppf = (at91dci_ep_profile + ep_addr); 195239310Sdim } else { 196239310Sdim *ppf = NULL; 197239310Sdim } 198239310Sdim} 199296417Sdim 200296417Sdimstatic void 201296417Sdimat91dci_clocks_on(struct at91dci_softc *sc) 202239310Sdim{ 203296417Sdim if (sc->sc_flags.clocks_off && 204239310Sdim sc->sc_flags.port_powered) { 205296417Sdim 206296417Sdim DPRINTFN(5, "\n"); 207239310Sdim 208296417Sdim if (sc->sc_clocks_on) { 209239310Sdim (sc->sc_clocks_on) (sc->sc_clocks_arg); 210239310Sdim } 211239310Sdim sc->sc_flags.clocks_off = 0; 212239310Sdim 213296417Sdim /* enable Transceiver */ 214296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0); 215296417Sdim } 216296417Sdim} 217296417Sdim 218296417Sdimstatic void 219296417Sdimat91dci_clocks_off(struct at91dci_softc *sc) 220296417Sdim{ 221296417Sdim if (!sc->sc_flags.clocks_off) { 222296417Sdim 223296417Sdim DPRINTFN(5, "\n"); 224296417Sdim 225296417Sdim /* disable Transceiver */ 226296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS); 227296417Sdim 228296417Sdim if (sc->sc_clocks_off) { 229296417Sdim (sc->sc_clocks_off) (sc->sc_clocks_arg); 230296417Sdim } 231296417Sdim sc->sc_flags.clocks_off = 1; 232239310Sdim } 233296417Sdim} 234239310Sdim 235239310Sdimstatic void 236239310Sdimat91dci_pull_up(struct at91dci_softc *sc) 237296417Sdim{ 238239310Sdim /* pullup D+, if possible */ 239239310Sdim 240239310Sdim if (!sc->sc_flags.d_pulled_up && 241239310Sdim sc->sc_flags.port_powered) { 242296417Sdim sc->sc_flags.d_pulled_up = 1; 243296417Sdim (sc->sc_pull_up) (sc->sc_pull_arg); 244296417Sdim } 245296417Sdim} 246296417Sdim 247239310Sdimstatic void 248239310Sdimat91dci_pull_down(struct at91dci_softc *sc) 249296417Sdim{ 250296417Sdim /* pulldown D+, if possible */ 251239310Sdim 252239310Sdim if (sc->sc_flags.d_pulled_up) { 253296417Sdim sc->sc_flags.d_pulled_up = 0; 254296417Sdim (sc->sc_pull_down) (sc->sc_pull_arg); 255296417Sdim } 256296417Sdim} 257296417Sdim 258296417Sdimstatic void 259296417Sdimat91dci_wakeup_peer(struct usb2_xfer *xfer) 260296417Sdim{ 261296417Sdim struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 262239310Sdim 263239310Sdim if (!(sc->sc_flags.status_suspend)) { 264239310Sdim return; 265296417Sdim } 266296417Sdim 267296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, AT91_UDP_GSTATE_ESR); 268296417Sdim 269239310Sdim /* wait 8 milliseconds */ 270239310Sdim /* Wait for reset to complete. */ 271296417Sdim usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 272296417Sdim 273239310Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, 0); 274239310Sdim} 275296417Sdim 276296417Sdimstatic void 277296417Sdimat91dci_set_address(struct at91dci_softc *sc, uint8_t addr) 278239310Sdim{ 279239310Sdim DPRINTFN(5, "addr=%d\n", addr); 280296417Sdim 281296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr | 282239310Sdim AT91_UDP_FADDR_EN); 283296417Sdim} 284239310Sdim 285239310Sdimstatic uint8_t 286239310Sdimat91dci_setup_rx(struct at91dci_td *td) 287239310Sdim{ 288239310Sdim struct at91dci_softc *sc; 289239310Sdim struct usb2_device_request req; 290296417Sdim uint32_t csr; 291296417Sdim uint32_t temp; 292296417Sdim uint16_t count; 293239310Sdim 294239310Sdim /* read out FIFO status */ 295296417Sdim csr = bus_space_read_4(td->io_tag, td->io_hdl, 296296417Sdim td->status_reg); 297239310Sdim 298239310Sdim DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 299296417Sdim 300239310Sdim temp = csr; 301288943Sdim temp &= (AT91_UDP_CSR_RX_DATA_BK0 | 302239310Sdim AT91_UDP_CSR_RX_DATA_BK1 | 303239310Sdim AT91_UDP_CSR_STALLSENT | 304239310Sdim AT91_UDP_CSR_RXSETUP | 305239310Sdim AT91_UDP_CSR_TXCOMP); 306239310Sdim 307296417Sdim if (!(csr & AT91_UDP_CSR_RXSETUP)) { 308239310Sdim /* abort any ongoing transfer */ 309239310Sdim if (!td->did_stall) { 310239310Sdim DPRINTFN(5, "stalling\n"); 311239310Sdim temp |= AT91_UDP_CSR_FORCESTALL; 312296417Sdim td->did_stall = 1; 313296417Sdim } 314239310Sdim goto not_complete; 315296417Sdim } 316296417Sdim /* get the packet byte count */ 317296417Sdim count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 318239310Sdim 319239310Sdim /* verify data length */ 320239310Sdim if (count != td->remainder) { 321239310Sdim DPRINTFN(0, "Invalid SETUP packet " 322296417Sdim "length, %d bytes\n", count); 323296417Sdim goto not_complete; 324296417Sdim } 325296417Sdim if (count != sizeof(req)) { 326296417Sdim DPRINTFN(0, "Unsupported SETUP packet " 327239310Sdim "length, %d bytes\n", count); 328239310Sdim goto not_complete; 329296417Sdim } 330296417Sdim /* receive data */ 331296417Sdim bus_space_read_multi_1(td->io_tag, td->io_hdl, 332296417Sdim td->fifo_reg, (void *)&req, sizeof(req)); 333296417Sdim 334296417Sdim /* copy data into real buffer */ 335296417Sdim usb2_copy_in(td->pc, 0, &req, sizeof(req)); 336296417Sdim 337296417Sdim td->offset = sizeof(req); 338296417Sdim td->remainder = 0; 339296417Sdim 340296417Sdim /* get pointer to softc */ 341296417Sdim sc = AT9100_DCI_PC2SC(td->pc); 342296417Sdim 343296417Sdim /* sneak peek the set address */ 344296417Sdim if ((req.bmRequestType == UT_WRITE_DEVICE) && 345296417Sdim (req.bRequest == UR_SET_ADDRESS)) { 346296417Sdim sc->sc_dv_addr = req.wValue[0] & 0x7F; 347296417Sdim } else { 348296417Sdim sc->sc_dv_addr = 0xFF; 349296417Sdim } 350296417Sdim 351296417Sdim /* sneak peek the endpoint direction */ 352296417Sdim if (req.bmRequestType & UE_DIR_IN) { 353296417Sdim csr |= AT91_UDP_CSR_DIR; 354239310Sdim } else { 355296417Sdim csr &= ~AT91_UDP_CSR_DIR; 356296417Sdim } 357296417Sdim 358296417Sdim /* write the direction of the control transfer */ 359296417Sdim AT91_CSR_ACK(csr, temp); 360239310Sdim bus_space_write_4(td->io_tag, td->io_hdl, 361239310Sdim td->status_reg, csr); 362296417Sdim return (0); /* complete */ 363296417Sdim 364296417Sdimnot_complete: 365296417Sdim /* clear interrupts, if any */ 366296417Sdim if (temp) { 367296417Sdim DPRINTFN(5, "clearing 0x%08x\n", temp); 368296417Sdim AT91_CSR_ACK(csr, temp); 369296417Sdim bus_space_write_4(td->io_tag, td->io_hdl, 370239310Sdim td->status_reg, csr); 371296417Sdim } 372296417Sdim return (1); /* not complete */ 373296417Sdim 374239310Sdim} 375296417Sdim 376296417Sdimstatic uint8_t 377296417Sdimat91dci_data_rx(struct at91dci_td *td) 378296417Sdim{ 379296417Sdim struct usb2_page_search buf_res; 380296417Sdim uint32_t csr; 381296417Sdim uint32_t temp; 382296417Sdim uint16_t count; 383296417Sdim uint8_t to; 384296417Sdim uint8_t got_short; 385296417Sdim 386296417Sdim to = 2; /* don't loop forever! */ 387296417Sdim got_short = 0; 388296417Sdim 389296417Sdim /* check if any of the FIFO banks have data */ 390296417Sdimrepeat: 391296417Sdim /* read out FIFO status */ 392296417Sdim csr = bus_space_read_4(td->io_tag, td->io_hdl, 393296417Sdim td->status_reg); 394296417Sdim 395296417Sdim DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 396296417Sdim 397296417Sdim if (csr & AT91_UDP_CSR_RXSETUP) { 398296417Sdim if (td->remainder == 0) { 399296417Sdim /* 400296417Sdim * We are actually complete and have 401296417Sdim * received the next SETUP 402296417Sdim */ 403296417Sdim DPRINTFN(5, "faking complete\n"); 404296417Sdim return (0); /* complete */ 405296417Sdim } 406296417Sdim /* 407296417Sdim * USB Host Aborted the transfer. 408296417Sdim */ 409296417Sdim td->error = 1; 410296417Sdim return (0); /* complete */ 411296417Sdim } 412296417Sdim /* Make sure that "STALLSENT" gets cleared */ 413296417Sdim temp = csr; 414296417Sdim temp &= AT91_UDP_CSR_STALLSENT; 415239310Sdim 416239310Sdim /* check status */ 417239310Sdim if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 | 418296417Sdim AT91_UDP_CSR_RX_DATA_BK1))) { 419239310Sdim if (temp) { 420296417Sdim /* write command */ 421296417Sdim AT91_CSR_ACK(csr, temp); 422239310Sdim bus_space_write_4(td->io_tag, td->io_hdl, 423239310Sdim td->status_reg, csr); 424239310Sdim } 425296417Sdim return (1); /* not complete */ 426296417Sdim } 427296417Sdim /* get the packet byte count */ 428239310Sdim count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 429239310Sdim 430239310Sdim /* verify the packet byte count */ 431261991Sdim if (count != td->max_packet_size) { 432261991Sdim if (count < td->max_packet_size) { 433261991Sdim /* we have a short packet */ 434261991Sdim td->short_pkt = 1; 435261991Sdim got_short = 1; 436239310Sdim } else { 437261991Sdim /* invalid USB packet */ 438261991Sdim td->error = 1; 439296417Sdim return (0); /* we are complete */ 440296417Sdim } 441296417Sdim } 442261991Sdim /* verify the packet byte count */ 443296417Sdim if (count > td->remainder) { 444261991Sdim /* invalid USB packet */ 445261991Sdim td->error = 1; 446239310Sdim return (0); /* we are complete */ 447239310Sdim } 448296417Sdim while (count > 0) { 449296417Sdim usb2_get_page(td->pc, td->offset, &buf_res); 450296417Sdim 451239310Sdim /* get correct length */ 452239310Sdim if (buf_res.length > count) { 453239310Sdim buf_res.length = count; 454239310Sdim } 455296417Sdim /* receive data */ 456296417Sdim bus_space_read_multi_1(td->io_tag, td->io_hdl, 457296417Sdim td->fifo_reg, buf_res.buffer, buf_res.length); 458296417Sdim 459239310Sdim /* update counters */ 460296417Sdim count -= buf_res.length; 461296417Sdim td->offset += buf_res.length; 462296417Sdim td->remainder -= buf_res.length; 463239310Sdim } 464296417Sdim 465296417Sdim /* clear status bits */ 466239310Sdim if (td->support_multi_buffer) { 467296417Sdim if (td->fifo_bank) { 468296417Sdim td->fifo_bank = 0; 469239310Sdim temp |= AT91_UDP_CSR_RX_DATA_BK1; 470239310Sdim } else { 471296417Sdim td->fifo_bank = 1; 472239310Sdim temp |= AT91_UDP_CSR_RX_DATA_BK0; 473296417Sdim } 474296417Sdim } else { 475239310Sdim temp |= (AT91_UDP_CSR_RX_DATA_BK0 | 476239310Sdim AT91_UDP_CSR_RX_DATA_BK1); 477239310Sdim } 478239310Sdim 479239310Sdim /* write command */ 480239310Sdim AT91_CSR_ACK(csr, temp); 481296417Sdim bus_space_write_4(td->io_tag, td->io_hdl, 482296417Sdim td->status_reg, csr); 483239310Sdim 484296417Sdim /* 485239310Sdim * NOTE: We may have to delay a little bit before 486239310Sdim * proceeding after clearing the DATA_BK bits. 487296417Sdim */ 488296417Sdim 489296417Sdim /* check if we are complete */ 490296417Sdim if ((td->remainder == 0) || got_short) { 491296417Sdim if (td->short_pkt) { 492296417Sdim /* we are complete */ 493296417Sdim return (0); 494296417Sdim } 495296417Sdim /* else need to receive a zero length packet */ 496296417Sdim } 497296417Sdim if (--to) { 498296417Sdim goto repeat; 499296417Sdim } 500296417Sdim return (1); /* not complete */ 501296417Sdim} 502296417Sdim 503296417Sdimstatic uint8_t 504296417Sdimat91dci_data_tx(struct at91dci_td *td) 505296417Sdim{ 506296417Sdim struct usb2_page_search buf_res; 507296417Sdim uint32_t csr; 508239310Sdim uint32_t temp; 509239310Sdim uint16_t count; 510239310Sdim uint8_t to; 511239310Sdim 512296417Sdim to = 2; /* don't loop forever! */ 513296417Sdim 514239310Sdimrepeat: 515239310Sdim 516296417Sdim /* read out FIFO status */ 517239310Sdim csr = bus_space_read_4(td->io_tag, td->io_hdl, 518239310Sdim td->status_reg); 519239310Sdim 520296417Sdim DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 521296417Sdim 522239310Sdim if (csr & AT91_UDP_CSR_RXSETUP) { 523239310Sdim /* 524296417Sdim * The current transfer was aborted 525296417Sdim * by the USB Host 526261991Sdim */ 527296417Sdim td->error = 1; 528239310Sdim return (0); /* complete */ 529239310Sdim } 530296417Sdim /* Make sure that "STALLSENT" gets cleared */ 531296417Sdim temp = csr; 532296417Sdim temp &= AT91_UDP_CSR_STALLSENT; 533239310Sdim 534239310Sdim if (csr & AT91_UDP_CSR_TXPKTRDY) { 535239310Sdim if (temp) { 536239310Sdim /* write command */ 537296417Sdim AT91_CSR_ACK(csr, temp); 538296417Sdim bus_space_write_4(td->io_tag, td->io_hdl, 539296417Sdim td->status_reg, csr); 540296417Sdim } 541296417Sdim return (1); /* not complete */ 542239310Sdim } else { 543296417Sdim /* clear TXCOMP and set TXPKTRDY */ 544296417Sdim temp |= (AT91_UDP_CSR_TXCOMP | 545296417Sdim AT91_UDP_CSR_TXPKTRDY); 546296417Sdim } 547296417Sdim 548239310Sdim count = td->max_packet_size; 549239310Sdim if (td->remainder < count) { 550239310Sdim /* we have a short packet */ 551239310Sdim td->short_pkt = 1; 552239310Sdim count = td->remainder; 553296417Sdim } 554296417Sdim while (count > 0) { 555239310Sdim 556239310Sdim usb2_get_page(td->pc, td->offset, &buf_res); 557239310Sdim 558296417Sdim /* get correct length */ 559296417Sdim if (buf_res.length > count) { 560296417Sdim buf_res.length = count; 561296417Sdim } 562296417Sdim /* transmit data */ 563296417Sdim bus_space_write_multi_1(td->io_tag, td->io_hdl, 564296417Sdim td->fifo_reg, buf_res.buffer, buf_res.length); 565239310Sdim 566239310Sdim /* update counters */ 567239310Sdim count -= buf_res.length; 568296417Sdim td->offset += buf_res.length; 569296417Sdim td->remainder -= buf_res.length; 570296417Sdim } 571239310Sdim 572261991Sdim /* write command */ 573296417Sdim AT91_CSR_ACK(csr, temp); 574296417Sdim bus_space_write_4(td->io_tag, td->io_hdl, 575239310Sdim td->status_reg, csr); 576239310Sdim 577239310Sdim /* check remainder */ 578296417Sdim if (td->remainder == 0) { 579239310Sdim if (td->short_pkt) { 580239310Sdim return (0); /* complete */ 581276479Sdim } 582239310Sdim /* else we need to transmit a short packet */ 583296417Sdim } 584296417Sdim if (--to) { 585296417Sdim goto repeat; 586296417Sdim } 587296417Sdim return (1); /* not complete */ 588296417Sdim} 589296417Sdim 590239310Sdimstatic uint8_t 591239310Sdimat91dci_data_tx_sync(struct at91dci_td *td) 592296417Sdim{ 593296417Sdim struct at91dci_softc *sc; 594239310Sdim uint32_t csr; 595296417Sdim uint32_t temp; 596296417Sdim 597296417Sdim#if 0 598296417Sdimrepeat: 599296417Sdim#endif 600296417Sdim 601296417Sdim /* read out FIFO status */ 602239310Sdim csr = bus_space_read_4(td->io_tag, td->io_hdl, 603239310Sdim td->status_reg); 604296417Sdim 605296417Sdim DPRINTFN(5, "csr=0x%08x\n", csr); 606239310Sdim 607239310Sdim if (csr & AT91_UDP_CSR_RXSETUP) { 608239310Sdim DPRINTFN(5, "faking complete\n"); 609239310Sdim /* Race condition */ 610239310Sdim return (0); /* complete */ 611239310Sdim } 612239310Sdim temp = csr; 613239310Sdim temp &= (AT91_UDP_CSR_STALLSENT | 614296417Sdim AT91_UDP_CSR_TXCOMP); 615296417Sdim 616296417Sdim /* check status */ 617296417Sdim if (csr & AT91_UDP_CSR_TXPKTRDY) { 618239310Sdim goto not_complete; 619239310Sdim } 620239310Sdim if (!(csr & AT91_UDP_CSR_TXCOMP)) { 621239310Sdim goto not_complete; 622239310Sdim } 623239310Sdim sc = AT9100_DCI_PC2SC(td->pc); 624239310Sdim if (sc->sc_dv_addr != 0xFF) { 625239310Sdim /* 626239310Sdim * The AT91 has a special requirement with regard to 627239310Sdim * setting the address and that is to write the new 628239310Sdim * address before clearing TXCOMP: 629239310Sdim */ 630239310Sdim at91dci_set_address(sc, sc->sc_dv_addr); 631296417Sdim } 632296417Sdim /* write command */ 633239310Sdim AT91_CSR_ACK(csr, temp); 634239310Sdim bus_space_write_4(td->io_tag, td->io_hdl, 635239310Sdim td->status_reg, csr); 636239310Sdim 637239310Sdim return (0); /* complete */ 638296417Sdim 639296417Sdimnot_complete: 640239310Sdim if (temp) { 641239310Sdim /* write command */ 642296417Sdim AT91_CSR_ACK(csr, temp); 643239310Sdim bus_space_write_4(td->io_tag, td->io_hdl, 644239310Sdim td->status_reg, csr); 645296417Sdim } 646296417Sdim return (1); /* not complete */ 647239310Sdim} 648239310Sdim 649239310Sdimstatic uint8_t 650276479Sdimat91dci_xfer_do_fifo(struct usb2_xfer *xfer) 651239310Sdim{ 652239310Sdim struct at91dci_softc *sc; 653239310Sdim struct at91dci_td *td; 654296417Sdim uint8_t temp; 655239310Sdim 656296417Sdim DPRINTFN(9, "\n"); 657296417Sdim 658296417Sdim td = xfer->td_transfer_cache; 659296417Sdim while (1) { 660239310Sdim if ((td->func) (td)) { 661239310Sdim /* operation in progress */ 662239310Sdim break; 663239310Sdim } 664296417Sdim if (((void *)td) == xfer->td_transfer_last) { 665296417Sdim goto done; 666296417Sdim } 667296417Sdim if (td->error) { 668296417Sdim goto done; 669296417Sdim } else if (td->remainder > 0) { 670296417Sdim /* 671296417Sdim * We had a short transfer. If there is no alternate 672296417Sdim * next, stop processing ! 673296417Sdim */ 674296417Sdim if (!td->alt_next) { 675296417Sdim goto done; 676296417Sdim } 677296417Sdim } 678296417Sdim /* 679296417Sdim * Fetch the next transfer descriptor and transfer 680296417Sdim * some flags to the next transfer descriptor 681296417Sdim */ 682296417Sdim temp = 0; 683296417Sdim if (td->fifo_bank) 684296417Sdim temp |= 1; 685296417Sdim td = td->obj_next; 686239310Sdim xfer->td_transfer_cache = td; 687239310Sdim if (temp & 1) 688239310Sdim td->fifo_bank = 1; 689239310Sdim } 690296417Sdim return (1); /* not complete */ 691296417Sdim 692296417Sdimdone: 693296417Sdim sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 694296417Sdim temp = (xfer->endpoint & UE_ADDR); 695239310Sdim 696239310Sdim /* update FIFO bank flag and multi buffer */ 697296417Sdim if (td->fifo_bank) { 698239310Sdim sc->sc_ep_flags[temp].fifo_bank = 1; 699296417Sdim } else { 700239310Sdim sc->sc_ep_flags[temp].fifo_bank = 0; 701239310Sdim } 702239310Sdim 703239310Sdim /* compute all actual lengths */ 704239310Sdim 705239310Sdim at91dci_standard_done(xfer); 706239310Sdim 707296417Sdim return (0); /* complete */ 708296417Sdim} 709296417Sdim 710296417Sdimstatic void 711296417Sdimat91dci_interrupt_poll(struct at91dci_softc *sc) 712296417Sdim{ 713296417Sdim struct usb2_xfer *xfer; 714239310Sdim 715239310Sdimrepeat: 716239310Sdim TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 717239310Sdim if (!at91dci_xfer_do_fifo(xfer)) { 718239310Sdim /* queue has been modified */ 719296417Sdim goto repeat; 720296417Sdim } 721296417Sdim } 722249423Sdim} 723296417Sdim 724239310Sdimvoid 725239310Sdimat91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on) 726239310Sdim{ 727239310Sdim DPRINTFN(5, "vbus = %u\n", is_on); 728239310Sdim 729296417Sdim USB_BUS_LOCK(&sc->sc_bus); 730296417Sdim if (is_on) { 731296417Sdim if (!sc->sc_flags.status_vbus) { 732296417Sdim sc->sc_flags.status_vbus = 1; 733296417Sdim 734296417Sdim /* complete root HUB interrupt endpoint */ 735296417Sdim 736296417Sdim usb2_sw_transfer(&sc->sc_root_intr, 737296417Sdim &at91dci_root_intr_done); 738296417Sdim } 739296417Sdim } else { 740296417Sdim if (sc->sc_flags.status_vbus) { 741296417Sdim sc->sc_flags.status_vbus = 0; 742296417Sdim sc->sc_flags.status_bus_reset = 0; 743296417Sdim sc->sc_flags.status_suspend = 0; 744296417Sdim sc->sc_flags.change_suspend = 0; 745296417Sdim sc->sc_flags.change_connect = 1; 746296417Sdim 747296417Sdim /* complete root HUB interrupt endpoint */ 748296417Sdim 749296417Sdim usb2_sw_transfer(&sc->sc_root_intr, 750239310Sdim &at91dci_root_intr_done); 751296417Sdim } 752296417Sdim } 753296417Sdim USB_BUS_UNLOCK(&sc->sc_bus); 754296417Sdim} 755296417Sdim 756296417Sdimvoid 757296417Sdimat91dci_interrupt(struct at91dci_softc *sc) 758239310Sdim{ 759239310Sdim uint32_t status; 760296417Sdim 761296417Sdim USB_BUS_LOCK(&sc->sc_bus); 762296417Sdim 763296417Sdim status = AT91_UDP_READ_4(sc, AT91_UDP_ISR); 764296417Sdim status &= AT91_UDP_INT_DEFAULT; 765296417Sdim 766296417Sdim if (!status) { 767296417Sdim USB_BUS_UNLOCK(&sc->sc_bus); 768296417Sdim return; 769239310Sdim } 770296417Sdim /* acknowledge interrupts */ 771296417Sdim 772296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status); 773296417Sdim 774239310Sdim /* check for any bus state change interrupts */ 775239310Sdim 776239310Sdim if (status & AT91_UDP_INT_BUS) { 777296417Sdim 778296417Sdim DPRINTFN(5, "real bus interrupt 0x%08x\n", status); 779239310Sdim 780239310Sdim if (status & AT91_UDP_INT_END_BR) { 781239310Sdim 782239310Sdim /* set correct state */ 783296417Sdim sc->sc_flags.status_bus_reset = 1; 784296417Sdim sc->sc_flags.status_suspend = 0; 785296417Sdim sc->sc_flags.change_suspend = 0; 786239310Sdim sc->sc_flags.change_connect = 1; 787239310Sdim 788239310Sdim /* disable resume interrupt */ 789296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 790296417Sdim AT91_UDP_INT_RXRSM); 791296417Sdim /* enable suspend interrupt */ 792280031Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 793239310Sdim AT91_UDP_INT_RXSUSP); 794296417Sdim } 795239310Sdim /* 796296417Sdim * If RXRSM and RXSUSP is set at the same time we interpret 797296417Sdim * that like RESUME. Resume is set when there is at least 3 798239310Sdim * milliseconds of inactivity on the USB BUS. 799239310Sdim */ 800296417Sdim if (status & AT91_UDP_INT_RXRSM) { 801239310Sdim if (sc->sc_flags.status_suspend) { 802296417Sdim sc->sc_flags.status_suspend = 0; 803296417Sdim sc->sc_flags.change_suspend = 1; 804296417Sdim 805239310Sdim /* disable resume interrupt */ 806239310Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 807296417Sdim AT91_UDP_INT_RXRSM); 808296417Sdim /* enable suspend interrupt */ 809296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 810239310Sdim AT91_UDP_INT_RXSUSP); 811239310Sdim } 812239310Sdim } else if (status & AT91_UDP_INT_RXSUSP) { 813239310Sdim if (!sc->sc_flags.status_suspend) { 814239310Sdim sc->sc_flags.status_suspend = 1; 815239310Sdim sc->sc_flags.change_suspend = 1; 816239310Sdim 817239310Sdim /* disable suspend interrupt */ 818239310Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 819261991Sdim AT91_UDP_INT_RXSUSP); 820261991Sdim 821261991Sdim /* enable resume interrupt */ 822261991Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 823261991Sdim AT91_UDP_INT_RXRSM); 824261991Sdim } 825261991Sdim } 826296417Sdim /* complete root HUB interrupt endpoint */ 827261991Sdim 828261991Sdim usb2_sw_transfer(&sc->sc_root_intr, 829261991Sdim &at91dci_root_intr_done); 830261991Sdim } 831261991Sdim /* check for any endpoint interrupts */ 832261991Sdim 833261991Sdim if (status & AT91_UDP_INT_EPS) { 834261991Sdim 835261991Sdim DPRINTFN(5, "real endpoint interrupt 0x%08x\n", status); 836239310Sdim 837296417Sdim at91dci_interrupt_poll(sc); 838296417Sdim } 839296417Sdim USB_BUS_UNLOCK(&sc->sc_bus); 840261991Sdim} 841261991Sdim 842296417Sdimstatic void 843296417Sdimat91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp) 844239310Sdim{ 845239310Sdim struct at91dci_td *td; 846296417Sdim 847296417Sdim /* get current Transfer Descriptor */ 848239310Sdim td = temp->td_next; 849239310Sdim temp->td = td; 850239310Sdim 851296417Sdim /* prepare for next TD */ 852239310Sdim temp->td_next = td->obj_next; 853239310Sdim 854296417Sdim /* fill out the Transfer Descriptor */ 855296417Sdim td->func = temp->func; 856239310Sdim td->pc = temp->pc; 857239310Sdim td->offset = temp->offset; 858296417Sdim td->remainder = temp->len; 859296417Sdim td->fifo_bank = 0; 860296417Sdim td->error = 0; 861239310Sdim td->did_stall = 0; 862239310Sdim td->short_pkt = temp->short_pkt; 863296417Sdim td->alt_next = temp->setup_alt_next; 864296417Sdim} 865296417Sdim 866296417Sdimstatic void 867296417Sdimat91dci_setup_standard_chain(struct usb2_xfer *xfer) 868239310Sdim{ 869239310Sdim struct at91dci_std_temp temp; 870239310Sdim struct at91dci_softc *sc; 871239310Sdim struct at91dci_td *td; 872296417Sdim uint32_t x; 873296417Sdim uint8_t ep_no; 874296417Sdim uint8_t need_sync; 875296417Sdim 876239310Sdim DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 877296417Sdim xfer->address, UE_GET_ADDR(xfer->endpoint), 878296417Sdim xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 879296417Sdim 880296417Sdim temp.max_frame_size = xfer->max_frame_size; 881296417Sdim 882296417Sdim td = xfer->td_start[0]; 883296417Sdim xfer->td_transfer_first = td; 884296417Sdim xfer->td_transfer_cache = td; 885296417Sdim 886239310Sdim /* setup temp */ 887239310Sdim 888239310Sdim temp.td = NULL; 889239310Sdim temp.td_next = xfer->td_start[0]; 890239310Sdim temp.offset = 0; 891296417Sdim temp.setup_alt_next = xfer->flags_int.short_frames_ok; 892296417Sdim 893296417Sdim sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 894296417Sdim ep_no = (xfer->endpoint & UE_ADDR); 895296417Sdim 896296417Sdim /* check if we should prepend a setup message */ 897296417Sdim 898296417Sdim if (xfer->flags_int.control_xfr) { 899296417Sdim if (xfer->flags_int.control_hdr) { 900296417Sdim 901296417Sdim temp.func = &at91dci_setup_rx; 902239310Sdim temp.len = xfer->frlengths[0]; 903239310Sdim temp.pc = xfer->frbuffers + 0; 904296417Sdim temp.short_pkt = temp.len ? 1 : 0; 905239310Sdim /* check for last frame */ 906239310Sdim if (xfer->nframes == 1) { 907239310Sdim /* no STATUS stage yet, SETUP is last */ 908239310Sdim if (xfer->flags_int.control_act) 909239310Sdim temp.setup_alt_next = 0; 910239310Sdim } 911239310Sdim 912239310Sdim at91dci_setup_standard_chain_sub(&temp); 913296417Sdim } 914296417Sdim x = 1; 915296417Sdim } else { 916239310Sdim x = 0; 917239310Sdim } 918239310Sdim 919288943Sdim if (x != xfer->nframes) { 920288943Sdim if (xfer->endpoint & UE_DIR_IN) { 921288943Sdim temp.func = &at91dci_data_tx; 922296417Sdim need_sync = 1; 923239310Sdim } else { 924239310Sdim temp.func = &at91dci_data_rx; 925239310Sdim need_sync = 0; 926296417Sdim } 927296417Sdim 928296417Sdim /* setup "pc" pointer */ 929296417Sdim temp.pc = xfer->frbuffers + x; 930296417Sdim } else { 931239310Sdim need_sync = 0; 932296417Sdim } 933239310Sdim while (x != xfer->nframes) { 934239310Sdim 935239310Sdim /* DATA0 / DATA1 message */ 936239310Sdim 937296417Sdim temp.len = xfer->frlengths[x]; 938288943Sdim 939288943Sdim x++; 940239310Sdim 941296417Sdim if (x == xfer->nframes) { 942296417Sdim if (xfer->flags_int.control_xfr) { 943296417Sdim if (xfer->flags_int.control_act) { 944296417Sdim temp.setup_alt_next = 0; 945296417Sdim } 946296417Sdim } else { 947239310Sdim temp.setup_alt_next = 0; 948239310Sdim } 949239310Sdim } 950239310Sdim if (temp.len == 0) { 951239310Sdim 952296417Sdim /* make sure that we send an USB packet */ 953239310Sdim 954239310Sdim temp.short_pkt = 0; 955296417Sdim 956296417Sdim } else { 957296417Sdim 958296417Sdim /* regular data transfer */ 959296417Sdim 960296417Sdim temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 961239310Sdim } 962239310Sdim 963239310Sdim at91dci_setup_standard_chain_sub(&temp); 964239310Sdim 965296417Sdim if (xfer->flags_int.isochronous_xfr) { 966296417Sdim temp.offset += temp.len; 967296417Sdim } else { 968296417Sdim /* get next Page Cache pointer */ 969296417Sdim temp.pc = xfer->frbuffers + x; 970296417Sdim } 971296417Sdim } 972296417Sdim 973296417Sdim /* check for control transfer */ 974296417Sdim if (xfer->flags_int.control_xfr) { 975296417Sdim 976296417Sdim /* always setup a valid "pc" pointer for status and sync */ 977296417Sdim temp.pc = xfer->frbuffers + 0; 978239310Sdim temp.len = 0; 979296417Sdim temp.short_pkt = 0; 980296417Sdim temp.setup_alt_next = 0; 981296417Sdim 982296417Sdim /* check if we need to sync */ 983296417Sdim if (need_sync) { 984296417Sdim /* we need a SYNC point after TX */ 985296417Sdim temp.func = &at91dci_data_tx_sync; 986239310Sdim at91dci_setup_standard_chain_sub(&temp); 987296417Sdim } 988296417Sdim 989296417Sdim /* check if we should append a status stage */ 990296417Sdim if (!xfer->flags_int.control_act) { 991239310Sdim 992239310Sdim /* 993296417Sdim * Send a DATA1 message and invert the current 994296417Sdim * endpoint direction. 995296417Sdim */ 996296417Sdim if (xfer->endpoint & UE_DIR_IN) { 997296417Sdim temp.func = &at91dci_data_rx; 998239310Sdim need_sync = 0; 999296417Sdim } else { 1000296417Sdim temp.func = &at91dci_data_tx; 1001296417Sdim need_sync = 1; 1002296417Sdim } 1003296417Sdim 1004296417Sdim at91dci_setup_standard_chain_sub(&temp); 1005296417Sdim if (need_sync) { 1006296417Sdim /* we need a SYNC point after TX */ 1007296417Sdim temp.func = &at91dci_data_tx_sync; 1008296417Sdim at91dci_setup_standard_chain_sub(&temp); 1009296417Sdim } 1010296417Sdim } 1011296417Sdim } 1012296417Sdim 1013296417Sdim /* must have at least one frame! */ 1014296417Sdim td = temp.td; 1015296417Sdim xfer->td_transfer_last = td; 1016296417Sdim 1017296417Sdim /* setup the correct fifo bank */ 1018296417Sdim if (sc->sc_ep_flags[ep_no].fifo_bank) { 1019296417Sdim td = xfer->td_transfer_first; 1020296417Sdim td->fifo_bank = 1; 1021296417Sdim } 1022296417Sdim} 1023296417Sdim 1024296417Sdimstatic void 1025296417Sdimat91dci_timeout(void *arg) 1026296417Sdim{ 1027239310Sdim struct usb2_xfer *xfer = arg; 1028296417Sdim 1029239310Sdim DPRINTF("xfer=%p\n", xfer); 1030296417Sdim 1031296417Sdim USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1032296417Sdim 1033296417Sdim /* transfer is transferred */ 1034296417Sdim at91dci_device_done(xfer, USB_ERR_TIMEOUT); 1035296417Sdim} 1036296417Sdim 1037239310Sdimstatic void 1038296417Sdimat91dci_start_standard_chain(struct usb2_xfer *xfer) 1039296417Sdim{ 1040239310Sdim DPRINTFN(9, "\n"); 1041296417Sdim 1042296417Sdim /* poll one time */ 1043296417Sdim if (at91dci_xfer_do_fifo(xfer)) { 1044296417Sdim 1045296417Sdim struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1046296417Sdim uint8_t ep_no = xfer->endpoint & UE_ADDR; 1047239310Sdim 1048296417Sdim /* 1049239310Sdim * Only enable the endpoint interrupt when we are actually 1050296417Sdim * waiting for data, hence we are dealing with level 1051296417Sdim * triggered interrupts ! 1052296417Sdim */ 1053296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no)); 1054296417Sdim 1055296417Sdim DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no); 1056239310Sdim 1057239310Sdim /* put transfer on interrupt queue */ 1058296417Sdim usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1059296417Sdim 1060296417Sdim /* start timeout, if any */ 1061296417Sdim if (xfer->timeout != 0) { 1062296417Sdim usb2_transfer_timeout_ms(xfer, 1063296417Sdim &at91dci_timeout, xfer->timeout); 1064296417Sdim } 1065296417Sdim } 1066296417Sdim} 1067296417Sdim 1068296417Sdimstatic void 1069296417Sdimat91dci_root_intr_done(struct usb2_xfer *xfer, 1070296417Sdim struct usb2_sw_transfer *std) 1071296417Sdim{ 1072296417Sdim struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1073296417Sdim 1074296417Sdim DPRINTFN(9, "\n"); 1075296417Sdim 1076296417Sdim USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1077296417Sdim 1078296417Sdim if (std->state != USB_SW_TR_PRE_DATA) { 1079296417Sdim if (std->state == USB_SW_TR_PRE_CALLBACK) { 1080296417Sdim /* transfer transferred */ 1081296417Sdim at91dci_device_done(xfer, std->err); 1082296417Sdim } 1083296417Sdim goto done; 1084296417Sdim } 1085296417Sdim /* setup buffer */ 1086296417Sdim std->ptr = sc->sc_hub_idata; 1087296417Sdim std->len = sizeof(sc->sc_hub_idata); 1088296417Sdim 1089296417Sdim /* set port bit */ 1090296417Sdim sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1091296417Sdim 1092296417Sdimdone: 1093296417Sdim return; 1094296417Sdim} 1095296417Sdim 1096296417Sdimstatic usb2_error_t 1097296417Sdimat91dci_standard_done_sub(struct usb2_xfer *xfer) 1098239310Sdim{ 1099239310Sdim struct at91dci_td *td; 1100296417Sdim uint32_t len; 1101296417Sdim uint8_t error; 1102296417Sdim 1103296417Sdim DPRINTFN(9, "\n"); 1104296417Sdim 1105296417Sdim td = xfer->td_transfer_cache; 1106296417Sdim 1107296417Sdim do { 1108296417Sdim len = td->remainder; 1109296417Sdim 1110296417Sdim if (xfer->aframes != xfer->nframes) { 1111296417Sdim /* 1112296417Sdim * Verify the length and subtract 1113296417Sdim * the remainder from "frlengths[]": 1114296417Sdim */ 1115296417Sdim if (len > xfer->frlengths[xfer->aframes]) { 1116296417Sdim td->error = 1; 1117296417Sdim } else { 1118296417Sdim xfer->frlengths[xfer->aframes] -= len; 1119296417Sdim } 1120296417Sdim } 1121239310Sdim /* Check for transfer error */ 1122239310Sdim if (td->error) { 1123296417Sdim /* the transfer is finished */ 1124296417Sdim error = 1; 1125239310Sdim td = NULL; 1126296417Sdim break; 1127296417Sdim } 1128296417Sdim /* Check for short transfer */ 1129296417Sdim if (len > 0) { 1130296417Sdim if (xfer->flags_int.short_frames_ok) { 1131296417Sdim /* follow alt next */ 1132296417Sdim if (td->alt_next) { 1133296417Sdim td = td->obj_next; 1134296417Sdim } else { 1135296417Sdim td = NULL; 1136296417Sdim } 1137296417Sdim } else { 1138296417Sdim /* the transfer is finished */ 1139296417Sdim td = NULL; 1140296417Sdim } 1141296417Sdim error = 0; 1142296417Sdim break; 1143296417Sdim } 1144296417Sdim td = td->obj_next; 1145288943Sdim 1146239310Sdim /* this USB frame is complete */ 1147296417Sdim error = 0; 1148296417Sdim break; 1149288943Sdim 1150239310Sdim } while (0); 1151296417Sdim 1152296417Sdim /* update transfer cache */ 1153296417Sdim 1154296417Sdim xfer->td_transfer_cache = td; 1155296417Sdim 1156288943Sdim return (error ? 1157239310Sdim USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1158288943Sdim} 1159288943Sdim 1160288943Sdimstatic void 1161296417Sdimat91dci_standard_done(struct usb2_xfer *xfer) 1162288943Sdim{ 1163239310Sdim usb2_error_t err = 0; 1164288943Sdim 1165296417Sdim DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1166296417Sdim xfer, xfer->pipe); 1167239310Sdim 1168296417Sdim /* reset scanner */ 1169288943Sdim 1170239310Sdim xfer->td_transfer_cache = xfer->td_transfer_first; 1171296417Sdim 1172296417Sdim if (xfer->flags_int.control_xfr) { 1173296417Sdim 1174296417Sdim if (xfer->flags_int.control_hdr) { 1175296417Sdim 1176288943Sdim err = at91dci_standard_done_sub(xfer); 1177288943Sdim } 1178239310Sdim xfer->aframes = 1; 1179296417Sdim 1180288943Sdim if (xfer->td_transfer_cache == NULL) { 1181288943Sdim goto done; 1182288943Sdim } 1183288943Sdim } 1184288943Sdim while (xfer->aframes != xfer->nframes) { 1185288943Sdim 1186288943Sdim err = at91dci_standard_done_sub(xfer); 1187296417Sdim xfer->aframes++; 1188296417Sdim 1189288943Sdim if (xfer->td_transfer_cache == NULL) { 1190288943Sdim goto done; 1191288943Sdim } 1192296417Sdim } 1193296417Sdim 1194296417Sdim if (xfer->flags_int.control_xfr && 1195296417Sdim !xfer->flags_int.control_act) { 1196296417Sdim 1197296417Sdim err = at91dci_standard_done_sub(xfer); 1198239310Sdim } 1199296417Sdimdone: 1200296417Sdim at91dci_device_done(xfer, err); 1201288943Sdim} 1202296417Sdim 1203239310Sdim/*------------------------------------------------------------------------* 1204239310Sdim * at91dci_device_done 1205296417Sdim * 1206296417Sdim * NOTE: this function can be called more than one time on the 1207296417Sdim * same USB transfer! 1208239310Sdim *------------------------------------------------------------------------*/ 1209296417Sdimstatic void 1210296417Sdimat91dci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1211296417Sdim{ 1212296417Sdim struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1213296417Sdim uint8_t ep_no; 1214296417Sdim 1215296417Sdim USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1216296417Sdim 1217296417Sdim DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1218296417Sdim xfer, xfer->pipe, error); 1219296417Sdim 1220296417Sdim if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1221296417Sdim ep_no = (xfer->endpoint & UE_ADDR); 1222296417Sdim 1223296417Sdim /* disable endpoint interrupt */ 1224296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no)); 1225296417Sdim 1226296417Sdim DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no); 1227296417Sdim } 1228296417Sdim /* dequeue transfer and start next transfer */ 1229296417Sdim usb2_transfer_done(xfer, error); 1230296417Sdim} 1231296417Sdim 1232296417Sdimstatic void 1233296417Sdimat91dci_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1234296417Sdim struct usb2_pipe *pipe) 1235296417Sdim{ 1236296417Sdim struct at91dci_softc *sc; 1237296417Sdim uint32_t csr_val; 1238296417Sdim uint8_t csr_reg; 1239296417Sdim 1240296417Sdim USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1241296417Sdim 1242296417Sdim DPRINTFN(5, "pipe=%p\n", pipe); 1243296417Sdim 1244296417Sdim if (xfer) { 1245296417Sdim /* cancel any ongoing transfers */ 1246296417Sdim at91dci_device_done(xfer, USB_ERR_STALLED); 1247239310Sdim } 1248296417Sdim /* set FORCESTALL */ 1249296417Sdim sc = AT9100_DCI_BUS2SC(udev->bus); 1250296417Sdim csr_reg = (pipe->edesc->bEndpointAddress & UE_ADDR); 1251296417Sdim csr_reg = AT91_UDP_CSR(csr_reg); 1252296417Sdim csr_val = AT91_UDP_READ_4(sc, csr_reg); 1253296417Sdim AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL); 1254296417Sdim AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1255296417Sdim} 1256296417Sdim 1257296417Sdimstatic void 1258296417Sdimat91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no, 1259296417Sdim uint8_t ep_type, uint8_t ep_dir) 1260296417Sdim{ 1261296417Sdim const struct usb2_hw_ep_profile *pf; 1262296417Sdim uint32_t csr_val; 1263296417Sdim uint32_t temp; 1264296417Sdim uint8_t csr_reg; 1265296417Sdim uint8_t to; 1266296417Sdim 1267296417Sdim if (ep_type == UE_CONTROL) { 1268296417Sdim /* clearing stall is not needed */ 1269296417Sdim return; 1270296417Sdim } 1271239310Sdim /* compute CSR register offset */ 1272296417Sdim csr_reg = AT91_UDP_CSR(ep_no); 1273296417Sdim 1274296417Sdim /* compute default CSR value */ 1275239310Sdim csr_val = 0; 1276296417Sdim AT91_CSR_ACK(csr_val, 0); 1277296417Sdim 1278296417Sdim /* disable endpoint */ 1279296417Sdim AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1280296417Sdim 1281296417Sdim /* get endpoint profile */ 1282296417Sdim at91dci_get_hw_ep_profile(NULL, &pf, ep_no); 1283239310Sdim 1284296417Sdim /* reset FIFO */ 1285296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no)); 1286296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0); 1287239310Sdim 1288296417Sdim /* 1289296417Sdim * NOTE: One would assume that a FIFO reset would release the 1290296417Sdim * FIFO banks aswell, but it doesn't! We have to do this 1291296417Sdim * manually! 1292296417Sdim */ 1293296417Sdim 1294296417Sdim /* release FIFO banks, if any */ 1295296417Sdim for (to = 0; to != 2; to++) { 1296239310Sdim 1297296417Sdim /* get csr value */ 1298296417Sdim csr_val = AT91_UDP_READ_4(sc, csr_reg); 1299296417Sdim 1300239310Sdim if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 | 1301296417Sdim AT91_UDP_CSR_RX_DATA_BK1)) { 1302296417Sdim /* clear status bits */ 1303296417Sdim if (pf->support_multi_buffer) { 1304296417Sdim if (sc->sc_ep_flags[ep_no].fifo_bank) { 1305296417Sdim sc->sc_ep_flags[ep_no].fifo_bank = 0; 1306239310Sdim temp = AT91_UDP_CSR_RX_DATA_BK1; 1307296417Sdim } else { 1308296417Sdim sc->sc_ep_flags[ep_no].fifo_bank = 1; 1309296417Sdim temp = AT91_UDP_CSR_RX_DATA_BK0; 1310296417Sdim } 1311296417Sdim } else { 1312239310Sdim temp = (AT91_UDP_CSR_RX_DATA_BK0 | 1313296417Sdim AT91_UDP_CSR_RX_DATA_BK1); 1314296417Sdim } 1315239310Sdim } else { 1316296417Sdim temp = 0; 1317296417Sdim } 1318296417Sdim 1319296417Sdim /* clear FORCESTALL */ 1320296417Sdim temp |= AT91_UDP_CSR_STALLSENT; 1321296417Sdim 1322296417Sdim AT91_CSR_ACK(csr_val, temp); 1323296417Sdim AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1324296417Sdim } 1325296417Sdim 1326296417Sdim /* compute default CSR value */ 1327296417Sdim csr_val = 0; 1328296417Sdim AT91_CSR_ACK(csr_val, 0); 1329239310Sdim 1330296417Sdim /* enable endpoint */ 1331296417Sdim csr_val &= ~AT91_UDP_CSR_ET_MASK; 1332296417Sdim csr_val |= AT91_UDP_CSR_EPEDS; 1333296417Sdim 1334296417Sdim if (ep_type == UE_CONTROL) { 1335296417Sdim csr_val |= AT91_UDP_CSR_ET_CTRL; 1336239310Sdim } else { 1337296417Sdim if (ep_type == UE_BULK) { 1338296417Sdim csr_val |= AT91_UDP_CSR_ET_BULK; 1339296417Sdim } else if (ep_type == UE_INTERRUPT) { 1340296417Sdim csr_val |= AT91_UDP_CSR_ET_INT; 1341296417Sdim } else { 1342296417Sdim csr_val |= AT91_UDP_CSR_ET_ISO; 1343296417Sdim } 1344296417Sdim if (ep_dir & UE_DIR_IN) { 1345296417Sdim csr_val |= AT91_UDP_CSR_ET_DIR_IN; 1346296417Sdim } 1347239310Sdim } 1348239310Sdim 1349239310Sdim /* enable endpoint */ 1350239310Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val); 1351296417Sdim} 1352296417Sdim 1353296417Sdimstatic void 1354296417Sdimat91dci_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1355296417Sdim{ 1356296417Sdim struct at91dci_softc *sc; 1357296417Sdim struct usb2_endpoint_descriptor *ed; 1358239310Sdim 1359239310Sdim DPRINTFN(5, "pipe=%p\n", pipe); 1360239310Sdim 1361296417Sdim USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1362296417Sdim 1363296417Sdim /* check mode */ 1364239310Sdim if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1365239310Sdim /* not supported */ 1366239310Sdim return; 1367296417Sdim } 1368296417Sdim /* get softc */ 1369296417Sdim sc = AT9100_DCI_BUS2SC(udev->bus); 1370296417Sdim 1371296417Sdim /* get endpoint descriptor */ 1372239310Sdim ed = pipe->edesc; 1373239310Sdim 1374296417Sdim /* reset endpoint */ 1375296417Sdim at91dci_clear_stall_sub(sc, 1376296417Sdim (ed->bEndpointAddress & UE_ADDR), 1377296417Sdim (ed->bmAttributes & UE_XFERTYPE), 1378296417Sdim (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1379296417Sdim} 1380296417Sdim 1381296417Sdimusb2_error_t 1382296417Sdimat91dci_init(struct at91dci_softc *sc) 1383296417Sdim{ 1384296417Sdim uint32_t csr_val; 1385296417Sdim uint8_t n; 1386296417Sdim 1387296417Sdim DPRINTF("start\n"); 1388296417Sdim 1389296417Sdim /* set up the bus structure */ 1390296417Sdim sc->sc_bus.usbrev = USB_REV_1_1; 1391296417Sdim sc->sc_bus.methods = &at91dci_bus_methods; 1392296417Sdim 1393296417Sdim USB_BUS_LOCK(&sc->sc_bus); 1394296417Sdim 1395296417Sdim /* turn on clocks */ 1396296417Sdim 1397296417Sdim if (sc->sc_clocks_on) { 1398296417Sdim (sc->sc_clocks_on) (sc->sc_clocks_arg); 1399296417Sdim } 1400296417Sdim /* wait a little for things to stabilise */ 1401239310Sdim usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1402296417Sdim 1403296417Sdim /* disable and clear all interrupts */ 1404296417Sdim 1405296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1406296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1407296417Sdim 1408296417Sdim /* compute default CSR value */ 1409239310Sdim 1410239310Sdim csr_val = 0; 1411296417Sdim AT91_CSR_ACK(csr_val, 0); 1412296417Sdim 1413296417Sdim /* disable all endpoints */ 1414296417Sdim 1415296417Sdim for (n = 0; n != AT91_UDP_EP_MAX; n++) { 1416239310Sdim 1417239310Sdim /* disable endpoint */ 1418239310Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val); 1419239310Sdim } 1420239310Sdim 1421296417Sdim /* enable the control endpoint */ 1422296417Sdim 1423239310Sdim AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL | 1424296417Sdim AT91_UDP_CSR_EPEDS); 1425296417Sdim 1426239310Sdim /* write to FIFO control register */ 1427296417Sdim 1428296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val); 1429239310Sdim 1430296417Sdim /* enable the interrupts we want */ 1431296417Sdim 1432296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS); 1433296417Sdim 1434239310Sdim /* turn off clocks */ 1435296417Sdim 1436296417Sdim at91dci_clocks_off(sc); 1437296417Sdim 1438296417Sdim USB_BUS_UNLOCK(&sc->sc_bus); 1439296417Sdim 1440296417Sdim /* catch any lost interrupts */ 1441296417Sdim 1442296417Sdim at91dci_do_poll(&sc->sc_bus); 1443239310Sdim 1444296417Sdim return (0); /* success */ 1445239310Sdim} 1446239310Sdim 1447296417Sdimvoid 1448239310Sdimat91dci_uninit(struct at91dci_softc *sc) 1449239310Sdim{ 1450296417Sdim USB_BUS_LOCK(&sc->sc_bus); 1451296417Sdim 1452296417Sdim /* disable and clear all interrupts */ 1453296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1454296417Sdim AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1455296417Sdim 1456296417Sdim sc->sc_flags.port_powered = 0; 1457296417Sdim sc->sc_flags.status_vbus = 0; 1458296417Sdim sc->sc_flags.status_bus_reset = 0; 1459296417Sdim sc->sc_flags.status_suspend = 0; 1460296417Sdim sc->sc_flags.change_suspend = 0; 1461239310Sdim sc->sc_flags.change_connect = 1; 1462296417Sdim 1463296417Sdim at91dci_pull_down(sc); 1464239310Sdim at91dci_clocks_off(sc); 1465296417Sdim USB_BUS_UNLOCK(&sc->sc_bus); 1466296417Sdim} 1467296417Sdim 1468296417Sdimvoid 1469296417Sdimat91dci_suspend(struct at91dci_softc *sc) 1470296417Sdim{ 1471296417Sdim return; 1472296417Sdim} 1473296417Sdim 1474239310Sdimvoid 1475296417Sdimat91dci_resume(struct at91dci_softc *sc) 1476296417Sdim{ 1477296417Sdim return; 1478296417Sdim} 1479296417Sdim 1480296417Sdimstatic void 1481296417Sdimat91dci_do_poll(struct usb2_bus *bus) 1482296417Sdim{ 1483296417Sdim struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 1484239310Sdim 1485296417Sdim USB_BUS_LOCK(&sc->sc_bus); 1486296417Sdim at91dci_interrupt_poll(sc); 1487239310Sdim at91dci_root_ctrl_poll(sc); 1488239310Sdim USB_BUS_UNLOCK(&sc->sc_bus); 1489296417Sdim} 1490296417Sdim 1491296417Sdim/*------------------------------------------------------------------------* 1492239310Sdim * at91dci bulk support 1493296417Sdim *------------------------------------------------------------------------*/ 1494296417Sdimstatic void 1495296417Sdimat91dci_device_bulk_open(struct usb2_xfer *xfer) 1496296417Sdim{ 1497296417Sdim return; 1498239310Sdim} 1499239310Sdim 1500296417Sdimstatic void 1501296417Sdimat91dci_device_bulk_close(struct usb2_xfer *xfer) 1502239310Sdim{ 1503296417Sdim at91dci_device_done(xfer, USB_ERR_CANCELLED); 1504296417Sdim} 1505296417Sdim 1506296417Sdimstatic void 1507296417Sdimat91dci_device_bulk_enter(struct usb2_xfer *xfer) 1508296417Sdim{ 1509296417Sdim return; 1510296417Sdim} 1511296417Sdim 1512296417Sdimstatic void 1513296417Sdimat91dci_device_bulk_start(struct usb2_xfer *xfer) 1514296417Sdim{ 1515296417Sdim /* setup TDs */ 1516239310Sdim at91dci_setup_standard_chain(xfer); 1517239310Sdim at91dci_start_standard_chain(xfer); 1518296417Sdim} 1519296417Sdim 1520296417Sdimstruct usb2_pipe_methods at91dci_device_bulk_methods = 1521296417Sdim{ 1522296417Sdim .open = at91dci_device_bulk_open, 1523296417Sdim .close = at91dci_device_bulk_close, 1524296417Sdim .enter = at91dci_device_bulk_enter, 1525296417Sdim .start = at91dci_device_bulk_start, 1526296417Sdim .enter_is_cancelable = 1, 1527296417Sdim .start_is_cancelable = 1, 1528296417Sdim}; 1529296417Sdim 1530296417Sdim/*------------------------------------------------------------------------* 1531296417Sdim * at91dci control support 1532296417Sdim *------------------------------------------------------------------------*/ 1533296417Sdimstatic void 1534296417Sdimat91dci_device_ctrl_open(struct usb2_xfer *xfer) 1535296417Sdim{ 1536296417Sdim return; 1537296417Sdim} 1538296417Sdim 1539296417Sdimstatic void 1540296417Sdimat91dci_device_ctrl_close(struct usb2_xfer *xfer) 1541296417Sdim{ 1542296417Sdim at91dci_device_done(xfer, USB_ERR_CANCELLED); 1543296417Sdim} 1544296417Sdim 1545296417Sdimstatic void 1546296417Sdimat91dci_device_ctrl_enter(struct usb2_xfer *xfer) 1547296417Sdim{ 1548296417Sdim return; 1549296417Sdim} 1550296417Sdim 1551296417Sdimstatic void 1552296417Sdimat91dci_device_ctrl_start(struct usb2_xfer *xfer) 1553296417Sdim{ 1554296417Sdim /* setup TDs */ 1555296417Sdim at91dci_setup_standard_chain(xfer); 1556296417Sdim at91dci_start_standard_chain(xfer); 1557296417Sdim} 1558296417Sdim 1559296417Sdimstruct usb2_pipe_methods at91dci_device_ctrl_methods = 1560296417Sdim{ 1561296417Sdim .open = at91dci_device_ctrl_open, 1562296417Sdim .close = at91dci_device_ctrl_close, 1563296417Sdim .enter = at91dci_device_ctrl_enter, 1564296417Sdim .start = at91dci_device_ctrl_start, 1565296417Sdim .enter_is_cancelable = 1, 1566296417Sdim .start_is_cancelable = 1, 1567296417Sdim}; 1568296417Sdim 1569296417Sdim/*------------------------------------------------------------------------* 1570296417Sdim * at91dci interrupt support 1571296417Sdim *------------------------------------------------------------------------*/ 1572296417Sdimstatic void 1573296417Sdimat91dci_device_intr_open(struct usb2_xfer *xfer) 1574296417Sdim{ 1575296417Sdim return; 1576296417Sdim} 1577296417Sdim 1578296417Sdimstatic void 1579296417Sdimat91dci_device_intr_close(struct usb2_xfer *xfer) 1580296417Sdim{ 1581296417Sdim at91dci_device_done(xfer, USB_ERR_CANCELLED); 1582296417Sdim} 1583296417Sdim 1584296417Sdimstatic void 1585296417Sdimat91dci_device_intr_enter(struct usb2_xfer *xfer) 1586296417Sdim{ 1587296417Sdim return; 1588296417Sdim} 1589296417Sdim 1590296417Sdimstatic void 1591296417Sdimat91dci_device_intr_start(struct usb2_xfer *xfer) 1592296417Sdim{ 1593296417Sdim /* setup TDs */ 1594239310Sdim at91dci_setup_standard_chain(xfer); 1595239310Sdim at91dci_start_standard_chain(xfer); 1596239310Sdim} 1597239310Sdim 1598239310Sdimstruct usb2_pipe_methods at91dci_device_intr_methods = 1599239310Sdim{ 1600239310Sdim .open = at91dci_device_intr_open, 1601239310Sdim .close = at91dci_device_intr_close, 1602 .enter = at91dci_device_intr_enter, 1603 .start = at91dci_device_intr_start, 1604 .enter_is_cancelable = 1, 1605 .start_is_cancelable = 1, 1606}; 1607 1608/*------------------------------------------------------------------------* 1609 * at91dci full speed isochronous support 1610 *------------------------------------------------------------------------*/ 1611static void 1612at91dci_device_isoc_fs_open(struct usb2_xfer *xfer) 1613{ 1614 return; 1615} 1616 1617static void 1618at91dci_device_isoc_fs_close(struct usb2_xfer *xfer) 1619{ 1620 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1621} 1622 1623static void 1624at91dci_device_isoc_fs_enter(struct usb2_xfer *xfer) 1625{ 1626 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1627 uint32_t temp; 1628 uint32_t nframes; 1629 1630 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1631 xfer, xfer->pipe->isoc_next, xfer->nframes); 1632 1633 /* get the current frame index */ 1634 1635 nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM); 1636 1637 /* 1638 * check if the frame index is within the window where the frames 1639 * will be inserted 1640 */ 1641 temp = (nframes - xfer->pipe->isoc_next) & AT91_UDP_FRM_MASK; 1642 1643 if ((xfer->pipe->is_synced == 0) || 1644 (temp < xfer->nframes)) { 1645 /* 1646 * If there is data underflow or the pipe queue is 1647 * empty we schedule the transfer a few frames ahead 1648 * of the current frame position. Else two isochronous 1649 * transfers might overlap. 1650 */ 1651 xfer->pipe->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK; 1652 xfer->pipe->is_synced = 1; 1653 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1654 } 1655 /* 1656 * compute how many milliseconds the insertion is ahead of the 1657 * current frame position: 1658 */ 1659 temp = (xfer->pipe->isoc_next - nframes) & AT91_UDP_FRM_MASK; 1660 1661 /* 1662 * pre-compute when the isochronous transfer will be finished: 1663 */ 1664 xfer->isoc_time_complete = 1665 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1666 xfer->nframes; 1667 1668 /* compute frame number for next insertion */ 1669 xfer->pipe->isoc_next += xfer->nframes; 1670 1671 /* setup TDs */ 1672 at91dci_setup_standard_chain(xfer); 1673} 1674 1675static void 1676at91dci_device_isoc_fs_start(struct usb2_xfer *xfer) 1677{ 1678 /* start TD chain */ 1679 at91dci_start_standard_chain(xfer); 1680} 1681 1682struct usb2_pipe_methods at91dci_device_isoc_fs_methods = 1683{ 1684 .open = at91dci_device_isoc_fs_open, 1685 .close = at91dci_device_isoc_fs_close, 1686 .enter = at91dci_device_isoc_fs_enter, 1687 .start = at91dci_device_isoc_fs_start, 1688 .enter_is_cancelable = 1, 1689 .start_is_cancelable = 1, 1690}; 1691 1692/*------------------------------------------------------------------------* 1693 * at91dci root control support 1694 *------------------------------------------------------------------------* 1695 * simulate a hardware HUB by handling 1696 * all the necessary requests 1697 *------------------------------------------------------------------------*/ 1698 1699static void 1700at91dci_root_ctrl_open(struct usb2_xfer *xfer) 1701{ 1702 return; 1703} 1704 1705static void 1706at91dci_root_ctrl_close(struct usb2_xfer *xfer) 1707{ 1708 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1709 1710 if (sc->sc_root_ctrl.xfer == xfer) { 1711 sc->sc_root_ctrl.xfer = NULL; 1712 } 1713 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1714} 1715 1716/* 1717 * USB descriptors for the virtual Root HUB: 1718 */ 1719 1720static const struct usb2_device_descriptor at91dci_devd = { 1721 .bLength = sizeof(struct usb2_device_descriptor), 1722 .bDescriptorType = UDESC_DEVICE, 1723 .bcdUSB = {0x00, 0x02}, 1724 .bDeviceClass = UDCLASS_HUB, 1725 .bDeviceSubClass = UDSUBCLASS_HUB, 1726 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1727 .bMaxPacketSize = 64, 1728 .bcdDevice = {0x00, 0x01}, 1729 .iManufacturer = 1, 1730 .iProduct = 2, 1731 .bNumConfigurations = 1, 1732}; 1733 1734static const struct usb2_device_qualifier at91dci_odevd = { 1735 .bLength = sizeof(struct usb2_device_qualifier), 1736 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1737 .bcdUSB = {0x00, 0x02}, 1738 .bDeviceClass = UDCLASS_HUB, 1739 .bDeviceSubClass = UDSUBCLASS_HUB, 1740 .bDeviceProtocol = UDPROTO_FSHUB, 1741 .bMaxPacketSize0 = 0, 1742 .bNumConfigurations = 0, 1743}; 1744 1745static const struct at91dci_config_desc at91dci_confd = { 1746 .confd = { 1747 .bLength = sizeof(struct usb2_config_descriptor), 1748 .bDescriptorType = UDESC_CONFIG, 1749 .wTotalLength[0] = sizeof(at91dci_confd), 1750 .bNumInterface = 1, 1751 .bConfigurationValue = 1, 1752 .iConfiguration = 0, 1753 .bmAttributes = UC_SELF_POWERED, 1754 .bMaxPower = 0, 1755 }, 1756 .ifcd = { 1757 .bLength = sizeof(struct usb2_interface_descriptor), 1758 .bDescriptorType = UDESC_INTERFACE, 1759 .bNumEndpoints = 1, 1760 .bInterfaceClass = UICLASS_HUB, 1761 .bInterfaceSubClass = UISUBCLASS_HUB, 1762 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 1763 }, 1764 1765 .endpd = { 1766 .bLength = sizeof(struct usb2_endpoint_descriptor), 1767 .bDescriptorType = UDESC_ENDPOINT, 1768 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT), 1769 .bmAttributes = UE_INTERRUPT, 1770 .wMaxPacketSize[0] = 8, 1771 .bInterval = 255, 1772 }, 1773}; 1774 1775static const struct usb2_hub_descriptor_min at91dci_hubd = { 1776 .bDescLength = sizeof(at91dci_hubd), 1777 .bDescriptorType = UDESC_HUB, 1778 .bNbrPorts = 1, 1779 .wHubCharacteristics[0] = 1780 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1781 .wHubCharacteristics[1] = 1782 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1783 .bPwrOn2PwrGood = 50, 1784 .bHubContrCurrent = 0, 1785 .DeviceRemovable = {0}, /* port is removable */ 1786}; 1787 1788#define STRING_LANG \ 1789 0x09, 0x04, /* American English */ 1790 1791#define STRING_VENDOR \ 1792 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'L', 0 1793 1794#define STRING_PRODUCT \ 1795 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1796 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1797 'U', 0, 'B', 0, 1798 1799USB_MAKE_STRING_DESC(STRING_LANG, at91dci_langtab); 1800USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor); 1801USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product); 1802 1803static void 1804at91dci_root_ctrl_enter(struct usb2_xfer *xfer) 1805{ 1806 return; 1807} 1808 1809static void 1810at91dci_root_ctrl_start(struct usb2_xfer *xfer) 1811{ 1812 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1813 1814 sc->sc_root_ctrl.xfer = xfer; 1815 1816 usb2_bus_roothub_exec(xfer->xroot->bus); 1817} 1818 1819static void 1820at91dci_root_ctrl_task(struct usb2_bus *bus) 1821{ 1822 at91dci_root_ctrl_poll(AT9100_DCI_BUS2SC(bus)); 1823} 1824 1825static void 1826at91dci_root_ctrl_done(struct usb2_xfer *xfer, 1827 struct usb2_sw_transfer *std) 1828{ 1829 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1830 uint16_t value; 1831 uint16_t index; 1832 1833 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1834 1835 if (std->state != USB_SW_TR_SETUP) { 1836 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1837 /* transfer transferred */ 1838 at91dci_device_done(xfer, std->err); 1839 } 1840 goto done; 1841 } 1842 /* buffer reset */ 1843 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 1844 std->len = 0; 1845 1846 value = UGETW(std->req.wValue); 1847 index = UGETW(std->req.wIndex); 1848 1849 /* demultiplex the control request */ 1850 1851 switch (std->req.bmRequestType) { 1852 case UT_READ_DEVICE: 1853 switch (std->req.bRequest) { 1854 case UR_GET_DESCRIPTOR: 1855 goto tr_handle_get_descriptor; 1856 case UR_GET_CONFIG: 1857 goto tr_handle_get_config; 1858 case UR_GET_STATUS: 1859 goto tr_handle_get_status; 1860 default: 1861 goto tr_stalled; 1862 } 1863 break; 1864 1865 case UT_WRITE_DEVICE: 1866 switch (std->req.bRequest) { 1867 case UR_SET_ADDRESS: 1868 goto tr_handle_set_address; 1869 case UR_SET_CONFIG: 1870 goto tr_handle_set_config; 1871 case UR_CLEAR_FEATURE: 1872 goto tr_valid; /* nop */ 1873 case UR_SET_DESCRIPTOR: 1874 goto tr_valid; /* nop */ 1875 case UR_SET_FEATURE: 1876 default: 1877 goto tr_stalled; 1878 } 1879 break; 1880 1881 case UT_WRITE_ENDPOINT: 1882 switch (std->req.bRequest) { 1883 case UR_CLEAR_FEATURE: 1884 switch (UGETW(std->req.wValue)) { 1885 case UF_ENDPOINT_HALT: 1886 goto tr_handle_clear_halt; 1887 case UF_DEVICE_REMOTE_WAKEUP: 1888 goto tr_handle_clear_wakeup; 1889 default: 1890 goto tr_stalled; 1891 } 1892 break; 1893 case UR_SET_FEATURE: 1894 switch (UGETW(std->req.wValue)) { 1895 case UF_ENDPOINT_HALT: 1896 goto tr_handle_set_halt; 1897 case UF_DEVICE_REMOTE_WAKEUP: 1898 goto tr_handle_set_wakeup; 1899 default: 1900 goto tr_stalled; 1901 } 1902 break; 1903 case UR_SYNCH_FRAME: 1904 goto tr_valid; /* nop */ 1905 default: 1906 goto tr_stalled; 1907 } 1908 break; 1909 1910 case UT_READ_ENDPOINT: 1911 switch (std->req.bRequest) { 1912 case UR_GET_STATUS: 1913 goto tr_handle_get_ep_status; 1914 default: 1915 goto tr_stalled; 1916 } 1917 break; 1918 1919 case UT_WRITE_INTERFACE: 1920 switch (std->req.bRequest) { 1921 case UR_SET_INTERFACE: 1922 goto tr_handle_set_interface; 1923 case UR_CLEAR_FEATURE: 1924 goto tr_valid; /* nop */ 1925 case UR_SET_FEATURE: 1926 default: 1927 goto tr_stalled; 1928 } 1929 break; 1930 1931 case UT_READ_INTERFACE: 1932 switch (std->req.bRequest) { 1933 case UR_GET_INTERFACE: 1934 goto tr_handle_get_interface; 1935 case UR_GET_STATUS: 1936 goto tr_handle_get_iface_status; 1937 default: 1938 goto tr_stalled; 1939 } 1940 break; 1941 1942 case UT_WRITE_CLASS_INTERFACE: 1943 case UT_WRITE_VENDOR_INTERFACE: 1944 /* XXX forward */ 1945 break; 1946 1947 case UT_READ_CLASS_INTERFACE: 1948 case UT_READ_VENDOR_INTERFACE: 1949 /* XXX forward */ 1950 break; 1951 1952 case UT_WRITE_CLASS_DEVICE: 1953 switch (std->req.bRequest) { 1954 case UR_CLEAR_FEATURE: 1955 goto tr_valid; 1956 case UR_SET_DESCRIPTOR: 1957 case UR_SET_FEATURE: 1958 break; 1959 default: 1960 goto tr_stalled; 1961 } 1962 break; 1963 1964 case UT_WRITE_CLASS_OTHER: 1965 switch (std->req.bRequest) { 1966 case UR_CLEAR_FEATURE: 1967 goto tr_handle_clear_port_feature; 1968 case UR_SET_FEATURE: 1969 goto tr_handle_set_port_feature; 1970 case UR_CLEAR_TT_BUFFER: 1971 case UR_RESET_TT: 1972 case UR_STOP_TT: 1973 goto tr_valid; 1974 1975 default: 1976 goto tr_stalled; 1977 } 1978 break; 1979 1980 case UT_READ_CLASS_OTHER: 1981 switch (std->req.bRequest) { 1982 case UR_GET_TT_STATE: 1983 goto tr_handle_get_tt_state; 1984 case UR_GET_STATUS: 1985 goto tr_handle_get_port_status; 1986 default: 1987 goto tr_stalled; 1988 } 1989 break; 1990 1991 case UT_READ_CLASS_DEVICE: 1992 switch (std->req.bRequest) { 1993 case UR_GET_DESCRIPTOR: 1994 goto tr_handle_get_class_descriptor; 1995 case UR_GET_STATUS: 1996 goto tr_handle_get_class_status; 1997 1998 default: 1999 goto tr_stalled; 2000 } 2001 break; 2002 default: 2003 goto tr_stalled; 2004 } 2005 goto tr_valid; 2006 2007tr_handle_get_descriptor: 2008 switch (value >> 8) { 2009 case UDESC_DEVICE: 2010 if (value & 0xff) { 2011 goto tr_stalled; 2012 } 2013 std->len = sizeof(at91dci_devd); 2014 std->ptr = USB_ADD_BYTES(&at91dci_devd, 0); 2015 goto tr_valid; 2016 case UDESC_CONFIG: 2017 if (value & 0xff) { 2018 goto tr_stalled; 2019 } 2020 std->len = sizeof(at91dci_confd); 2021 std->ptr = USB_ADD_BYTES(&at91dci_confd, 0); 2022 goto tr_valid; 2023 case UDESC_STRING: 2024 switch (value & 0xff) { 2025 case 0: /* Language table */ 2026 std->len = sizeof(at91dci_langtab); 2027 std->ptr = USB_ADD_BYTES(&at91dci_langtab, 0); 2028 goto tr_valid; 2029 2030 case 1: /* Vendor */ 2031 std->len = sizeof(at91dci_vendor); 2032 std->ptr = USB_ADD_BYTES(&at91dci_vendor, 0); 2033 goto tr_valid; 2034 2035 case 2: /* Product */ 2036 std->len = sizeof(at91dci_product); 2037 std->ptr = USB_ADD_BYTES(&at91dci_product, 0); 2038 goto tr_valid; 2039 default: 2040 break; 2041 } 2042 break; 2043 default: 2044 goto tr_stalled; 2045 } 2046 goto tr_stalled; 2047 2048tr_handle_get_config: 2049 std->len = 1; 2050 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2051 goto tr_valid; 2052 2053tr_handle_get_status: 2054 std->len = 2; 2055 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2056 goto tr_valid; 2057 2058tr_handle_set_address: 2059 if (value & 0xFF00) { 2060 goto tr_stalled; 2061 } 2062 sc->sc_rt_addr = value; 2063 goto tr_valid; 2064 2065tr_handle_set_config: 2066 if (value >= 2) { 2067 goto tr_stalled; 2068 } 2069 sc->sc_conf = value; 2070 goto tr_valid; 2071 2072tr_handle_get_interface: 2073 std->len = 1; 2074 sc->sc_hub_temp.wValue[0] = 0; 2075 goto tr_valid; 2076 2077tr_handle_get_tt_state: 2078tr_handle_get_class_status: 2079tr_handle_get_iface_status: 2080tr_handle_get_ep_status: 2081 std->len = 2; 2082 USETW(sc->sc_hub_temp.wValue, 0); 2083 goto tr_valid; 2084 2085tr_handle_set_halt: 2086tr_handle_set_interface: 2087tr_handle_set_wakeup: 2088tr_handle_clear_wakeup: 2089tr_handle_clear_halt: 2090 goto tr_valid; 2091 2092tr_handle_clear_port_feature: 2093 if (index != 1) { 2094 goto tr_stalled; 2095 } 2096 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2097 2098 switch (value) { 2099 case UHF_PORT_SUSPEND: 2100 at91dci_wakeup_peer(xfer); 2101 break; 2102 2103 case UHF_PORT_ENABLE: 2104 sc->sc_flags.port_enabled = 0; 2105 break; 2106 2107 case UHF_PORT_TEST: 2108 case UHF_PORT_INDICATOR: 2109 case UHF_C_PORT_ENABLE: 2110 case UHF_C_PORT_OVER_CURRENT: 2111 case UHF_C_PORT_RESET: 2112 /* nops */ 2113 break; 2114 case UHF_PORT_POWER: 2115 sc->sc_flags.port_powered = 0; 2116 at91dci_pull_down(sc); 2117 at91dci_clocks_off(sc); 2118 break; 2119 case UHF_C_PORT_CONNECTION: 2120 sc->sc_flags.change_connect = 0; 2121 break; 2122 case UHF_C_PORT_SUSPEND: 2123 sc->sc_flags.change_suspend = 0; 2124 break; 2125 default: 2126 std->err = USB_ERR_IOERROR; 2127 goto done; 2128 } 2129 goto tr_valid; 2130 2131tr_handle_set_port_feature: 2132 if (index != 1) { 2133 goto tr_stalled; 2134 } 2135 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2136 2137 switch (value) { 2138 case UHF_PORT_ENABLE: 2139 sc->sc_flags.port_enabled = 1; 2140 break; 2141 case UHF_PORT_SUSPEND: 2142 case UHF_PORT_RESET: 2143 case UHF_PORT_TEST: 2144 case UHF_PORT_INDICATOR: 2145 /* nops */ 2146 break; 2147 case UHF_PORT_POWER: 2148 sc->sc_flags.port_powered = 1; 2149 break; 2150 default: 2151 std->err = USB_ERR_IOERROR; 2152 goto done; 2153 } 2154 goto tr_valid; 2155 2156tr_handle_get_port_status: 2157 2158 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2159 2160 if (index != 1) { 2161 goto tr_stalled; 2162 } 2163 if (sc->sc_flags.status_vbus) { 2164 at91dci_clocks_on(sc); 2165 at91dci_pull_up(sc); 2166 } else { 2167 at91dci_pull_down(sc); 2168 at91dci_clocks_off(sc); 2169 } 2170 2171 /* Select FULL-speed and Device Side Mode */ 2172 2173 value = UPS_PORT_MODE_DEVICE; 2174 2175 if (sc->sc_flags.port_powered) { 2176 value |= UPS_PORT_POWER; 2177 } 2178 if (sc->sc_flags.port_enabled) { 2179 value |= UPS_PORT_ENABLED; 2180 } 2181 if (sc->sc_flags.status_vbus && 2182 sc->sc_flags.status_bus_reset) { 2183 value |= UPS_CURRENT_CONNECT_STATUS; 2184 } 2185 if (sc->sc_flags.status_suspend) { 2186 value |= UPS_SUSPEND; 2187 } 2188 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2189 2190 value = 0; 2191 2192 if (sc->sc_flags.change_connect) { 2193 value |= UPS_C_CONNECT_STATUS; 2194 2195 if (sc->sc_flags.status_vbus && 2196 sc->sc_flags.status_bus_reset) { 2197 /* reset endpoint flags */ 2198 bzero(sc->sc_ep_flags, sizeof(sc->sc_ep_flags)); 2199 } 2200 } 2201 if (sc->sc_flags.change_suspend) { 2202 value |= UPS_C_SUSPEND; 2203 } 2204 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2205 std->len = sizeof(sc->sc_hub_temp.ps); 2206 goto tr_valid; 2207 2208tr_handle_get_class_descriptor: 2209 if (value & 0xFF) { 2210 goto tr_stalled; 2211 } 2212 std->ptr = USB_ADD_BYTES(&at91dci_hubd, 0); 2213 std->len = sizeof(at91dci_hubd); 2214 goto tr_valid; 2215 2216tr_stalled: 2217 std->err = USB_ERR_STALLED; 2218tr_valid: 2219done: 2220 return; 2221} 2222 2223static void 2224at91dci_root_ctrl_poll(struct at91dci_softc *sc) 2225{ 2226 usb2_sw_transfer(&sc->sc_root_ctrl, 2227 &at91dci_root_ctrl_done); 2228} 2229 2230struct usb2_pipe_methods at91dci_root_ctrl_methods = 2231{ 2232 .open = at91dci_root_ctrl_open, 2233 .close = at91dci_root_ctrl_close, 2234 .enter = at91dci_root_ctrl_enter, 2235 .start = at91dci_root_ctrl_start, 2236 .enter_is_cancelable = 1, 2237 .start_is_cancelable = 0, 2238}; 2239 2240/*------------------------------------------------------------------------* 2241 * at91dci root interrupt support 2242 *------------------------------------------------------------------------*/ 2243static void 2244at91dci_root_intr_open(struct usb2_xfer *xfer) 2245{ 2246 return; 2247} 2248 2249static void 2250at91dci_root_intr_close(struct usb2_xfer *xfer) 2251{ 2252 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 2253 2254 if (sc->sc_root_intr.xfer == xfer) { 2255 sc->sc_root_intr.xfer = NULL; 2256 } 2257 at91dci_device_done(xfer, USB_ERR_CANCELLED); 2258} 2259 2260static void 2261at91dci_root_intr_enter(struct usb2_xfer *xfer) 2262{ 2263 return; 2264} 2265 2266static void 2267at91dci_root_intr_start(struct usb2_xfer *xfer) 2268{ 2269 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 2270 2271 sc->sc_root_intr.xfer = xfer; 2272} 2273 2274struct usb2_pipe_methods at91dci_root_intr_methods = 2275{ 2276 .open = at91dci_root_intr_open, 2277 .close = at91dci_root_intr_close, 2278 .enter = at91dci_root_intr_enter, 2279 .start = at91dci_root_intr_start, 2280 .enter_is_cancelable = 1, 2281 .start_is_cancelable = 1, 2282}; 2283 2284static void 2285at91dci_xfer_setup(struct usb2_setup_params *parm) 2286{ 2287 const struct usb2_hw_ep_profile *pf; 2288 struct at91dci_softc *sc; 2289 struct usb2_xfer *xfer; 2290 void *last_obj; 2291 uint32_t ntd; 2292 uint32_t n; 2293 uint8_t ep_no; 2294 2295 sc = AT9100_DCI_BUS2SC(parm->udev->bus); 2296 xfer = parm->curr_xfer; 2297 2298 /* 2299 * NOTE: This driver does not use any of the parameters that 2300 * are computed from the following values. Just set some 2301 * reasonable dummies: 2302 */ 2303 parm->hc_max_packet_size = 0x500; 2304 parm->hc_max_packet_count = 1; 2305 parm->hc_max_frame_size = 0x500; 2306 2307 usb2_transfer_setup_sub(parm); 2308 2309 /* 2310 * compute maximum number of TDs 2311 */ 2312 if (parm->methods == &at91dci_device_ctrl_methods) { 2313 2314 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2315 + 1 /* SYNC 2 */ ; 2316 2317 } else if (parm->methods == &at91dci_device_bulk_methods) { 2318 2319 ntd = xfer->nframes + 1 /* SYNC */ ; 2320 2321 } else if (parm->methods == &at91dci_device_intr_methods) { 2322 2323 ntd = xfer->nframes + 1 /* SYNC */ ; 2324 2325 } else if (parm->methods == &at91dci_device_isoc_fs_methods) { 2326 2327 ntd = xfer->nframes + 1 /* SYNC */ ; 2328 2329 } else { 2330 2331 ntd = 0; 2332 } 2333 2334 /* 2335 * check if "usb2_transfer_setup_sub" set an error 2336 */ 2337 if (parm->err) { 2338 return; 2339 } 2340 /* 2341 * allocate transfer descriptors 2342 */ 2343 last_obj = NULL; 2344 2345 /* 2346 * get profile stuff 2347 */ 2348 if (ntd) { 2349 2350 ep_no = xfer->endpoint & UE_ADDR; 2351 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2352 2353 if (pf == NULL) { 2354 /* should not happen */ 2355 parm->err = USB_ERR_INVAL; 2356 return; 2357 } 2358 } else { 2359 ep_no = 0; 2360 pf = NULL; 2361 } 2362 2363 /* align data */ 2364 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2365 2366 for (n = 0; n != ntd; n++) { 2367 2368 struct at91dci_td *td; 2369 2370 if (parm->buf) { 2371 2372 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2373 2374 /* init TD */ 2375 td->io_tag = sc->sc_io_tag; 2376 td->io_hdl = sc->sc_io_hdl; 2377 td->max_packet_size = xfer->max_packet_size; 2378 td->status_reg = AT91_UDP_CSR(ep_no); 2379 td->fifo_reg = AT91_UDP_FDR(ep_no); 2380 if (pf->support_multi_buffer) { 2381 td->support_multi_buffer = 1; 2382 } 2383 td->obj_next = last_obj; 2384 2385 last_obj = td; 2386 } 2387 parm->size[0] += sizeof(*td); 2388 } 2389 2390 xfer->td_start[0] = last_obj; 2391} 2392 2393static void 2394at91dci_xfer_unsetup(struct usb2_xfer *xfer) 2395{ 2396 return; 2397} 2398 2399static void 2400at91dci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2401 struct usb2_pipe *pipe) 2402{ 2403 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 2404 2405 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2406 pipe, udev->address, 2407 edesc->bEndpointAddress, udev->flags.usb2_mode, 2408 sc->sc_rt_addr); 2409 2410 if (udev->device_index == sc->sc_rt_addr) { 2411 2412 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2413 /* not supported */ 2414 return; 2415 } 2416 switch (edesc->bEndpointAddress) { 2417 case USB_CONTROL_ENDPOINT: 2418 pipe->methods = &at91dci_root_ctrl_methods; 2419 break; 2420 case UE_DIR_IN | AT9100_DCI_INTR_ENDPT: 2421 pipe->methods = &at91dci_root_intr_methods; 2422 break; 2423 default: 2424 /* do nothing */ 2425 break; 2426 } 2427 } else { 2428 2429 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2430 /* not supported */ 2431 return; 2432 } 2433 if (udev->speed != USB_SPEED_FULL) { 2434 /* not supported */ 2435 return; 2436 } 2437 switch (edesc->bmAttributes & UE_XFERTYPE) { 2438 case UE_CONTROL: 2439 pipe->methods = &at91dci_device_ctrl_methods; 2440 break; 2441 case UE_INTERRUPT: 2442 pipe->methods = &at91dci_device_intr_methods; 2443 break; 2444 case UE_ISOCHRONOUS: 2445 pipe->methods = &at91dci_device_isoc_fs_methods; 2446 break; 2447 case UE_BULK: 2448 pipe->methods = &at91dci_device_bulk_methods; 2449 break; 2450 default: 2451 /* do nothing */ 2452 break; 2453 } 2454 } 2455} 2456 2457struct usb2_bus_methods at91dci_bus_methods = 2458{ 2459 .pipe_init = &at91dci_pipe_init, 2460 .xfer_setup = &at91dci_xfer_setup, 2461 .xfer_unsetup = &at91dci_xfer_unsetup, 2462 .get_hw_ep_profile = &at91dci_get_hw_ep_profile, 2463 .set_stall = &at91dci_set_stall, 2464 .clear_stall = &at91dci_clear_stall, 2465 .roothub_exec = &at91dci_root_ctrl_task, 2466}; 2467